OSDN Git Service
Krzysztof Parzyszek [Mon, 14 May 2018 20:09:07 +0000 (20:09 +0000)]
[Hexagon] Add a target feature for memop generation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332285
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Sid Manning [Mon, 14 May 2018 19:46:08 +0000 (19:46 +0000)]
Hexagon: Put relocations after instructions not packets.
Change relocation output so that relocation information follows
individual instructions rather than clustering them at the end
of packets.
This change required shifting block of code but the actual change
is in HexagonPrettyPrinter's PrintInst.
Differential Revision: https://reviews.llvm.org/D46728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332283
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Nico Weber [Mon, 14 May 2018 19:23:31 +0000 (19:23 +0000)]
Inline a few CMake variables into their only uses.
No behavior change. Makes unittests CMakeLists.txt files more self-consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332280
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Nico Weber [Mon, 14 May 2018 19:13:23 +0000 (19:13 +0000)]
Remove a workaround that should be unneeded after r202806.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332278
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Simon Pilgrim [Mon, 14 May 2018 18:37:19 +0000 (18:37 +0000)]
[X86] Add NT load/store scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332274
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Nico Weber [Mon, 14 May 2018 18:23:05 +0000 (18:23 +0000)]
alphabetize list
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332272
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Craig Topper [Mon, 14 May 2018 18:21:22 +0000 (18:21 +0000)]
[X86] Remove and autoupgrade avx512.vbroadcast.ss/avx512.vbroadcast.sd intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332271
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Simon Pilgrim [Mon, 14 May 2018 18:20:40 +0000 (18:20 +0000)]
[llvm-mca][X86] Add missing SSE4A test file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332270
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Simon Pilgrim [Mon, 14 May 2018 18:07:28 +0000 (18:07 +0000)]
[X86][BtVer2] Fix MMX/YMM integer vector nt store schedules
MMX was missing and YMM was tagged as a fp nt store
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332269
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Craig Topper [Mon, 14 May 2018 18:02:21 +0000 (18:02 +0000)]
[X86] Remove GCCBuiltin from the intrinsics that clang stopped using in r332266.
Add a FIXME for their eventual removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332267
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Geoff Berry [Mon, 14 May 2018 17:31:18 +0000 (17:31 +0000)]
[BranchFolding] Allow hoisting to block with a single conditional branch.
Summary:
The BranchFolding pass is currently missing opportunities to hoist
common code if the hoisted-to block contains a single conditional branch
that has register uses. This occurs somewhat frequently on AArch64 with
CBZ/TBZ opcodes.
This change also eliminates some code differences when debug info is
present since the presence of e.g. DBG_VALUE instructions in the
hoisted-to block can enable hoisting that wouldn't have occurred without
them.
Reviewers: MatzeB, rnk, kparzysz, twoh, aprantl, javed.absar
Subscribers: kristof.beyls, JDevlieghere, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D46324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332265
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Simon Pilgrim [Mon, 14 May 2018 17:10:33 +0000 (17:10 +0000)]
[llvm-mca][x86] Add scalar nt-store instruction tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332262
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Krzysztof Parzyszek [Mon, 14 May 2018 16:41:40 +0000 (16:41 +0000)]
[Hexagon] Avoid predicate copies to integer registers from store-locked
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332260
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Simon Dardis [Mon, 14 May 2018 16:26:50 +0000 (16:26 +0000)]
[mips] Fix the predicates of round, ceiling, floor and trunc.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332258
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Simon Pilgrim [Mon, 14 May 2018 16:26:24 +0000 (16:26 +0000)]
[llvm-mca][x86] Add and/not/or/xor instruction tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332257
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Zaara Syeda [Mon, 14 May 2018 15:45:15 +0000 (15:45 +0000)]
[NFC] [Power] Fix instruction format for xsrqpi
xsrqpi is currently using Z23Form_1.
The instruction format is xsrqpi R,VRT,VRB,RMC.
Rathar than bits 11-15 being used for FRA, it should have
bits 11-14 reserved and bit 15 for R. This patch adds a new
class Z23Form_4 to fix the instruction format.
Differential Revision: https://reviews.llvm.org/D46761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332253
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Evandro Menezes [Mon, 14 May 2018 15:26:35 +0000 (15:26 +0000)]
[AArch64] Improve single vector lane stores
When storing the 0th lane of a vector, use a simpler and usually more efficient scalar store instead.
Differential revision: https://reviews.llvm.org/D46655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332251
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Andrea Di Biagio [Mon, 14 May 2018 15:08:22 +0000 (15:08 +0000)]
[llvm-mca] Improved support for dependency-breaking instructions.
The tool assumes that a zero-latency instruction that doesn't consume hardware
resources is an optimizable dependency-breaking instruction. That means, it
doesn't have to wait on register input operands, and it doesn't consume any
physical register. The PRF knows how to optimize it at register renaming stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332249
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Pavel Labath [Mon, 14 May 2018 14:13:20 +0000 (14:13 +0000)]
[CodeGen/AccelTable]: Handle -dwarf-linkage-names=Abstract correctly
Summary:
If we are not emitting a linkage name in the .debug_info sections, we
should not add it into the index either. This makes sure our index is
consistent with the actual debug info.
I am also explicitly setting the --dwarf-linkage-names=All in the
name-collsions test as that one would now fail on targets where this
defaults to "Abstract" (in fact, it would have failed already if there
wasn't a bug in the DWARF verifier, which I fix as well).
Reviewers: probinson, aprantl, JDevlieghere
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46748
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332246
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Nicola Zaghen [Mon, 14 May 2018 13:54:39 +0000 (13:54 +0000)]
Docs: Fix the title underline too short.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332245
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Sanjay Patel [Mon, 14 May 2018 13:43:32 +0000 (13:43 +0000)]
[AggressiveInstCombine] avoid crashing on unsimplified code (PR37446)
This bug:
https://bugs.llvm.org/show_bug.cgi?id=37446
...raises another question: why do we run aggressive-instcombine before
regular instcombine?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332243
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Simon Dardis [Mon, 14 May 2018 13:18:51 +0000 (13:18 +0000)]
[mips] Add missing test case from r332227
I did not commit this test from D46689.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332241
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Nicola Zaghen [Mon, 14 May 2018 12:53:11 +0000 (12:53 +0000)]
Rename DEBUG macro to LLVM_DEBUG.
The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.
In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.
Differential Revision: https://reviews.llvm.org/D43624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332240
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Simon Pilgrim [Mon, 14 May 2018 12:22:30 +0000 (12:22 +0000)]
Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332239
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Simon Pilgrim [Mon, 14 May 2018 12:20:19 +0000 (12:20 +0000)]
Fix "not all control paths return a value" MSVC warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332238
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Clement Courbet [Mon, 14 May 2018 12:00:35 +0000 (12:00 +0000)]
Re-land r332230 "[llvm-exegesis]Fix a warning in r332221"
comparison of integers of different signs: 'const unsigned long' and 'const int' [-Werror,-Wsign-compare]
unittests/tools/llvm-exegesis/BenchmarkResultTest.cpp:60:5: note: in instantiation of function template specialization 'testing::internal::EqHelper<false>::Compare<unsigned long, int>' requested here
ASSERT_EQ(FromDiskVector.size(), 1);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332235
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Sander de Smalen [Mon, 14 May 2018 11:54:41 +0000 (11:54 +0000)]
[AArch64][SVE] Extend parsing of Prefetch operation for SVE.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332234
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Clement Courbet [Mon, 14 May 2018 11:35:37 +0000 (11:35 +0000)]
[llvm-exegesis] Revert accidentally commited code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332231
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Clement Courbet [Mon, 14 May 2018 11:31:02 +0000 (11:31 +0000)]
[llvm-exegesis] Fix a warning in r332221
comparison of integers of different signs: 'const unsigned long' and 'const int' [-Werror,-Wsign-compare]
unittests/tools/llvm-exegesis/BenchmarkResultTest.cpp:60:5: note: in instantiation of function template specialization 'testing::internal::EqHelper<false>::Compare<unsigned long, int>' requested here
ASSERT_EQ(FromDiskVector.size(), 1);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332230
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Clement Courbet [Mon, 14 May 2018 11:30:56 +0000 (11:30 +0000)]
[llvm-exegesis] Add an analysis mode.
The analysis mode gives the user a clustered view of the measurement results and
highlights any inconsistencies with the checked-in data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332229
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Simon Dardis [Mon, 14 May 2018 10:53:15 +0000 (10:53 +0000)]
[mips] Correct the predicates of indexed floating point stores and loads.
Also, fix the register class for microMIPS.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332227
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Clement Courbet [Mon, 14 May 2018 09:01:22 +0000 (09:01 +0000)]
[llvm-exegesis] Allow lists of BenchmarkResults to be parsed as std::vector<BenchmarkResult>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332221
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Nicola Zaghen [Mon, 14 May 2018 08:24:29 +0000 (08:24 +0000)]
Test commit access.
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332220
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Robert Widmann [Mon, 14 May 2018 08:09:00 +0000 (08:09 +0000)]
[LLVM-C] Add Bindings For Module Flags
Summary:
The first foray into merging debug info into the echo tests.
- Add bindings to Module::getModuleFlagsMetadata() in the form of LLVMCopyModuleFlagsMetadata
- Add the opaque type LLVMModuleFlagEntry to represent Module::ModuleFlagEntry
- Add accessors for LLVMModuleFlagEntry's behavior, key, and metadata node.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: aprantl, JDevlieghere, llvm-commits, harlanhaskins
Differential Revision: https://reviews.llvm.org/D46792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332219
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Fangrui Song [Mon, 14 May 2018 05:56:48 +0000 (05:56 +0000)]
[llvm-ar] Make PositionalArgs static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332216
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Bill Wendling [Mon, 14 May 2018 05:25:36 +0000 (05:25 +0000)]
Correct compatibility with the GNU Assembler's handling of comparison ops
GAS returns -1 for a comparison operator if the result is true and 0 if false.
https://www.sourceware.org/binutils/docs-2.12/as.info/Infix-Ops.html#Infix%20Ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332215
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Craig Topper [Mon, 14 May 2018 05:09:41 +0000 (05:09 +0000)]
[X86] Add fast isel test cases for the clang output for 512-bit cvtps2pd related intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332214
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Craig Topper [Mon, 14 May 2018 00:17:52 +0000 (00:17 +0000)]
[X86] Cleanup a multiclass that doesn't need as many parameters after recent intrinsic removals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332207
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Craig Topper [Mon, 14 May 2018 00:06:49 +0000 (00:06 +0000)]
[X86] Remove and autoupgrade the cvtusi2sd intrinsic. Use uitofp+insertelement instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332206
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Craig Topper [Sun, 13 May 2018 23:24:21 +0000 (23:24 +0000)]
[X86] Add patterns for combining movss+uint_to_fp into the intrinsic instructions under AVX512.
This matches what we do for sint_to_fp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332205
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Craig Topper [Sun, 13 May 2018 23:24:19 +0000 (23:24 +0000)]
[X86] Add fast-isel test cases for _mm_cvtu32_sd, _mm_cvtu64_sd, _mm_cvtu32_ss, and _mm_cvtu64_ss.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332204
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Craig Topper [Sun, 13 May 2018 21:56:32 +0000 (21:56 +0000)]
[X86] Extend instcombine folds for pclmuldq intrinsics to the 256 and 512 bit version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332202
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Craig Topper [Sun, 13 May 2018 18:26:06 +0000 (18:26 +0000)]
[X86] Add missing test for the InstCombines of pclmulqdq.
Apparently this test was lost when r293151 was committed. It was present in the review, but not the commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332199
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Craig Topper [Sun, 13 May 2018 18:03:59 +0000 (18:03 +0000)]
[X86] Remove and autoupgrade masked vpermd/vpermps intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332198
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Dimitry Andric [Sun, 13 May 2018 14:32:23 +0000 (14:32 +0000)]
Follow-up to rL332176 by adding a test case for PR37264.
Noticed by Simon Pilgrim.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332197
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Matt Arsenault [Sun, 13 May 2018 10:04:48 +0000 (10:04 +0000)]
AMDGPU: Rename OpenCL lowering pass to be R600 specific.
This pass is
a) broken.
b) r600 specific.
Fixing (a) is a bit more non-trivial, but fixing (b)
is easy. Move this pass to being R600 only for now.
This pass does pass all the unit tests, however clang
no longer generates code that looks like the unit test
input, so fixing the pass requires fixing the tests and
the pass as one, and checking it works with clang still.
Patch by Dave Airlie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332196
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Matt Arsenault [Sun, 13 May 2018 10:04:38 +0000 (10:04 +0000)]
AMDGPU: Make undef legal for v2i16/v2f16
This is apparently necessary to stop undef from being
turned into a build_vector of 0s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332195
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Puyan Lotfi [Sun, 13 May 2018 06:50:55 +0000 (06:50 +0000)]
Fixing build bot error: adding const qualifiers to std::sort lambda.
Errors were not reproducible on clang-6.0 on ubuntu 16.04.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332192
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Puyan Lotfi [Sun, 13 May 2018 06:07:20 +0000 (06:07 +0000)]
[NFC] MIR-Canon: switching to a stable string sorting of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332191
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Craig Topper [Sun, 13 May 2018 01:54:33 +0000 (01:54 +0000)]
[X86] Add some load folding patterns for cvtsi2ss/sd into intrinsic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332189
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Craig Topper [Sun, 13 May 2018 00:58:23 +0000 (00:58 +0000)]
[X86] Remove some unused CHECK lines from tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332188
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Craig Topper [Sun, 13 May 2018 00:29:40 +0000 (00:29 +0000)]
[X86] Remove an autoupgrade legacy cvtss2sd intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332187
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Craig Topper [Sat, 12 May 2018 23:14:39 +0000 (23:14 +0000)]
[X86] Remove and autoupgrade cvtsi2ss/cvtsi2sd intrinsics to match what clang has used for a very long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332186
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Chandler Carruth [Sat, 12 May 2018 21:28:53 +0000 (21:28 +0000)]
[x86] Remove a comment obviated by r330269. Should have deleted the
comment in the same revision but missed it.
Thanks to Dimitry Andric for catching this!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332177
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Dimitry Andric [Sat, 12 May 2018 19:59:54 +0000 (19:59 +0000)]
Clear converters map after X86 Domain Reassignment to avoid crashes
Summary:
As reported in PR37264, in some cases the X86 Domain Reassignment
`runOnMachineFunction()` is called twice. Because it only deletes the
`.second` members of its `InstrConverterBaseMap`, and does not clean up
the map itself, this can lead to double frees and crashes.
Use `DeleteContainerSeconds()` instead, so the `Converters` map can
safely be reinitialized and its members re-deleted for each X86 Domain
Reassignment pass.
Reviewers: guyblank, craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332176
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JF Bastien [Sat, 12 May 2018 19:39:34 +0000 (19:39 +0000)]
[NFC] Remove inaccurate comment
Summary:
r271558 moved getManagedStaticMutex's mutex from a function-local
static to using call_once, but left a comment added in r211424. That comment is
now erroneous, remove it.
Reviewers: zturner, chandlerc
Subscribers: aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D46784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332175
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JF Bastien [Sat, 12 May 2018 19:38:44 +0000 (19:38 +0000)]
llc: don't call llvm_shutdown twice
Summary:
InitLLVM already calls llvm_shutdown, but llc registers for shutdown
with llvm_shutdown_obj so it gets called twice. It's not hurting anything, but
it's also not useful, so don't do it.
Reviewers: ruiu
Subscribers: aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D46788
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332174
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Simon Pilgrim [Sat, 12 May 2018 18:07:07 +0000 (18:07 +0000)]
[X86] Add WriteFCMOV scheduler class for x87 CMOVs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332173
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Simon Dardis [Sat, 12 May 2018 16:57:26 +0000 (16:57 +0000)]
[mips] Initialize the long branch pass for testing purposes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332172
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Craig Topper [Sat, 12 May 2018 02:34:28 +0000 (02:34 +0000)]
[X86] Remove some unused masked conversion intrinsics that can be replaced with an older intrinsic and a select.
This is what clang already uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332170
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Michael Zolotukhin [Sat, 12 May 2018 01:52:36 +0000 (01:52 +0000)]
Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading."
Stage3/stage4 bootstrap miscompares should be fixed by a non-determinism
fix in IDF (r332167).
This reverts commit r330446.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332168
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Michael Zolotukhin [Sat, 12 May 2018 01:44:32 +0000 (01:44 +0000)]
[IDF] Enforce the returned blocks to be sorted.
Summary:
Currently the order of blocks returned by `IDF::calculate` can be
non-deterministic. This was discovered in several attempts to enable
SSAUpdaterBulk for JumpThreading (which led to miscompare in bootstrap between
stage 3 and stage4). Originally, the blocks were put into a priority queue with
a depth level as their key, and this patch adds a DFSIn number as a second key
to specify a deterministic order across blocks from one level.
The solution was suggested by Daniel Berlin.
Reviewers: dberlin, davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332167
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Stanislav Mekhanoshin [Sat, 12 May 2018 01:41:56 +0000 (01:41 +0000)]
[AMDGPU] Fix amdgpu-waves-per-eu accounting in scheduler
We cannot query this attribute from a subtarget given a machine function.
At this point attribute itself is already unavailable and can only be
obtained through MFI.
Differential Revision: https://reviews.llvm.org/D46781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332166
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Chris Matthews [Sat, 12 May 2018 00:13:54 +0000 (00:13 +0000)]
Requirements can have & in them!
Lets escape those so the XML is valid!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332161
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Chris Matthews [Fri, 11 May 2018 23:15:11 +0000 (23:15 +0000)]
Add the message attribute to skipped
JUnit xml allows for a message attribute to be displayed on skips. Lets
populate that with an analysis of why we skipped the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332156
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Sanjay Patel [Fri, 11 May 2018 23:13:36 +0000 (23:13 +0000)]
[DAG] add convenience function to propagate FMF; NFC
There's only one use of this currently, but that could
change with D46563. Either way, we shouldn't have to
update code outside of the flags struct when those
flag definitions change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332155
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Tom Stellard [Fri, 11 May 2018 23:12:49 +0000 (23:12 +0000)]
AMDGPU/GlobalISel: Implement select() for >32-bit G_STORE
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D46153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332154
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Alina Sbirlea [Fri, 11 May 2018 22:59:37 +0000 (22:59 +0000)]
[MemorySSA] getIncomingValueForBlock should return a MemoryAccess.
Summary: getIncomingValueForBlock is just a wrapper API that should return a MemoryAccess, instead of a generic Value.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D46779
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332153
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Sergey Dmitriev [Fri, 11 May 2018 22:49:49 +0000 (22:49 +0000)]
[CodeExtractor] Allow extracting blocks with exception handling
This is a CodeExtractor improvement which adds support for extracting blocks
which have exception handling constructs if that is legal to do. CodeExtractor
performs validation checks to ensure that extraction is legal when it finds
invoke instructions or EH pads (landingpad, catchswitch, or cleanuppad) in
blocks to be extracted.
I have also added an option to allow extraction of blocks with alloca
instructions, but no validation is done for allocas. CodeExtractor caller has
to validate it himself before allowing alloca instructions to be extracted.
By default allocas are still not allowed in extraction blocks.
Differential Revision: https://reviews.llvm.org/D45904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332151
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Sanjay Patel [Fri, 11 May 2018 22:45:22 +0000 (22:45 +0000)]
[DAG] clean up flag propagation for binops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332150
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Chris Matthews [Fri, 11 May 2018 22:18:22 +0000 (22:18 +0000)]
Overhaul unicode handling in xunit output
I have seen a lot of errors where the xunit does not encode unicode
test output correctly. Handle that explicitly now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332148
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Changpeng Fang [Fri, 11 May 2018 22:17:57 +0000 (22:17 +0000)]
AMDGPU/SI: Don't promote alloca to vector for AddrSpaceCast instruction.
Summary:
We have no logic to promote alloca to vector for an AddrSpaceCast instruction.
Reviewer:
arsenm
Differential Revision:
https://reviews.llvm.org/D45993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332147
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Craig Topper [Fri, 11 May 2018 21:59:34 +0000 (21:59 +0000)]
[X86] Remove and autoupgrade a bunch of FMA instrinsics that are no longer used by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332146
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Artem Belevich [Fri, 11 May 2018 21:13:19 +0000 (21:13 +0000)]
[Split GEP] handle trunc() in separate-const-offset-from-gep pass.
Let separate-const-offset-from-gep pass handle trunc() when it calculates
constant offset relative to base. The pass itself may insert trunc()
instructions when it canonicalises array indices to pointer-size integers
and needs to handle trunc() in order to evaluate the offset.
Differential Revision: https://reviews.llvm.org/D46732
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332142
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Yaxun Liu [Fri, 11 May 2018 20:40:14 +0000 (20:40 +0000)]
[AMDGPU] Fix compilation failure when IR contains comdat
Remove a useless SwitchSection which also causes compilation failure
when IR contains comdat.
The SwitchSection is useless because the current section is already
correct text section for the function therefore no need to switch.
It causes compilation failure for comdat because functions with comdat
has specific text section, not the default .text section.
Since HIP uses comdat, this bug caused failures for HIP.
Differential Revision: https://reviews.llvm.org/D46770
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332137
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Sanjay Patel [Fri, 11 May 2018 20:08:23 +0000 (20:08 +0000)]
[DAG] reduce code duplication; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332133
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Daniel Neilson [Fri, 11 May 2018 20:04:50 +0000 (20:04 +0000)]
[InstCombine] Handle atomic memset in the same way as regular memset
Summary:
This change adds handling of the atomic memset intrinsic to the
code path that simplifies the regular memset. In practice this means
that we will now also expand a small constant-length atomic memset
into a single unordered atomic store.
Reviewers: apilipenko, skatkov, mkazantsev, anna, reames
Reviewed By: reames
Subscribers: reames, llvm-commits
Differential Revision: https://reviews.llvm.org/D46660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332132
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David Blaikie [Fri, 11 May 2018 19:21:40 +0000 (19:21 +0000)]
Move standard library inclusions to after internal inclusions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332124
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Vedant Kumar [Fri, 11 May 2018 18:40:10 +0000 (18:40 +0000)]
[DAGCombiner] Set the right SDLoc on extended SETCC uses (7/N)
ExtendSetCCUses updates SETCC nodes which use a load (OriginalLoad) to
reflect a simplification to the load (ExtLoad).
Based on my reading, ExtendSetCCUses may create new nodes to extend a
constant attached to a SETCC. It also creates fresh SETCC nodes which
refer to any updated operands.
ISTM that the location applied to the new constant and SETCC nodes
should be the same as the location of the ExtLoad.
This was suggested by Adrian in https://reviews.llvm.org/D45995.
Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D46216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332119
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Vedant Kumar [Fri, 11 May 2018 18:40:08 +0000 (18:40 +0000)]
[DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)
This teaches tryToFoldExtOfLoad to set the right location on a
newly-created extload. With that in place, the logic for performing a
certain ([s|z]ext (load ...)) combine becomes identical for sexts and
zexts, and we can get rid of one copy of the logic.
The test case churn is due to dependencies on IROrders inherited from
the wrong SDLoc.
Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D46158
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332118
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Vedant Kumar [Fri, 11 May 2018 18:40:02 +0000 (18:40 +0000)]
[DAGCombiner] Factor out duplicated logic for an extload combine, NFC (5/N)
Part of the logic for combining (zext (load ...)) and (sext (load ...))
is duplicated. This creates problems because bugs in one version have to
be fixed again in the other version.
To address this, as a first step, I've extracted the duplicate logic
into a helper. I'll fix the debug location bug in the helper and
eliminate the copy of its logic in a followup.
Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D46157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332117
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Chris Matthews [Fri, 11 May 2018 18:38:02 +0000 (18:38 +0000)]
[LIT] replace output escapes wit a cdata block
CDATA blocks don't need to have XML stuff escaped. Makes sense to wrap
output in them instead of escaping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332116
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Nico Weber [Fri, 11 May 2018 17:58:52 +0000 (17:58 +0000)]
make add_llvm_fuzzer calls slightly more consisten with other cmake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332112
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David Bolvansky [Fri, 11 May 2018 17:50:49 +0000 (17:50 +0000)]
[InstCombine] snprintf optimizations
Reviewers: spatel, efriedma, majnemer, rja, bkramer
Reviewed By: rja, bkramer
Subscribers: mstorsjo, rja, llvm-commits
Differential Revision: https://reviews.llvm.org/D46285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332110
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Simon Pilgrim [Fri, 11 May 2018 17:38:36 +0000 (17:38 +0000)]
[X86][BtVer2] Model ymm move as double pumped instructions
We still need to handle mmx/xmm moves as 'decode-only' no-pipe instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332109
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Alex Bradbury [Fri, 11 May 2018 17:30:28 +0000 (17:30 +0000)]
[RISCV] Support .option rvc and norvc assembler directives
These directives allow the 'C' (compressed) extension to be enabled/disabled
within a single file.
Differential Revision: https://reviews.llvm.org/D45864
Patch by Kito Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332107
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Martin Storsjo [Fri, 11 May 2018 16:53:56 +0000 (16:53 +0000)]
[Analysis] Validate the return type of s(n)printf like libcalls
If the sprintf function is static (as on mingw-w64, where many stdio
functions are static inline wrappers), earlier optimization passes
could optimize out the return value altogether, and make it void,
which could break optimizations of this libcall that touch the
return value.
This fixes the issue discussed in PR37408 for the sprintf function.
Differential Revision: https://reviews.llvm.org/D46752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332106
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Simon Pilgrim [Fri, 11 May 2018 16:38:59 +0000 (16:38 +0000)]
[X86][MMX] Tag MMX Move/Load/Store as WriteVec schedule classes
Fixes an issue on SLM/Btver2 where we had instructions were being treated as scalar loads/stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332104
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Geoff Berry [Fri, 11 May 2018 16:25:06 +0000 (16:25 +0000)]
[AArch64] Fix performPostLD1Combine to check for constant lane index.
Summary:
performPostLD1Combine in AArch64ISelLowering looks for vector
insert_vector_elt of a loaded value which it can optimize into a single
LD1LANE instruction. The code checking for the pattern was not checking
if the lane index was a constant which could cause two problems:
- an assert when lowering the LD1LANE ISD node since it assumes an
constant operand
- an assert in isel if the lane index value depends on the
post-incremented base register
Both of these issues are avoided by simply checking that the lane index
is a constant.
Fixes bug 35822.
Reviewers: t.p.northover, javed.absar
Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D46591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332103
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Simon Dardis [Fri, 11 May 2018 16:13:53 +0000 (16:13 +0000)]
[mips] Rename Filler to MipsDelaySlotFiller and initialize the pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332102
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Sanjoy Das [Fri, 11 May 2018 15:54:46 +0000 (15:54 +0000)]
Use iteration instead of recursion in CFIInserter
Summary: This recursive step can overflow the stack.
Reviewers: djokov, petarj
Subscribers: mcrosier, jlebar, bixia, llvm-commits
Differential Revision: https://reviews.llvm.org/D46671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332101
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Davide Italiano [Fri, 11 May 2018 15:45:36 +0000 (15:45 +0000)]
[Reassociate] Prevent infinite loops when processing PHIs.
Phi nodes can reside in live blocks but one of their incoming
arguments can come from a dead block. Dead blocks and reassociate
don't play nice together. In fact, reassociate performs an RPO
as a first step to avoid processing dead blocks.
The reason why Reassociate might not fixpoint when examining
dead blocks is that the following:
%xor0 = xor i16 %xor1, undef
%xor1 = xor i16 %xor0, undef
is perfectly valid LLVM IR (if it appears in a dead block),
so the worklist algorithm keeps pushing the two instructions for
reexamination. Note that this is not Reassociate fault, at least
not entirely. It's llvm that has a weird definition of dominance.
Fixes PR37390.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332100
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Nico Weber [Fri, 11 May 2018 15:25:38 +0000 (15:25 +0000)]
Remove unused SyncExecutor and make it clearer that the whole file is only used if LLVM_ENABLE_THREADS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332098
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Simon Dardis [Fri, 11 May 2018 15:21:40 +0000 (15:21 +0000)]
[mips] Enable disassembly of fused (negative) multiply add/sub instructions
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332097
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Simon Pilgrim [Fri, 11 May 2018 15:16:15 +0000 (15:16 +0000)]
[X86][SLM] Vector stores only use the MEC port.
Confirmed by both Agner and Intel's AOM - the IEC/FPC are not required for pure load/stores (even if its a partial update).
Can't fix WriteStore until all RMW instructions are cleaned up though....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332096
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Simon Pilgrim [Fri, 11 May 2018 14:30:54 +0000 (14:30 +0000)]
[X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector width
Fixes a SNB issue that was missing vlddqu/vmovntdqa ymm instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332094
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Daniel Neilson [Fri, 11 May 2018 14:30:02 +0000 (14:30 +0000)]
[InstCombine] Unify handling of atomic memtransfer with non-atomic memtransfer
Summary:
This change reworks the handling of atomic memcpy within the instcombine pass.
Previously, a constant length atomic memcpy would be lowered into loads & stores
as long as no more than 16 load/store pairs are created. This is quite different
from the lowering done for a non-atomic memcpy; which only ever lowers into a single
load/store pair of no more than 8 bytes. Larger constant-sized memcpy calls are
expanded to load/stores in later passes, such as SelectionDAG lowering.
In this change the behaviour for atomic memcpy is unified with non-atomic memcpy;
atomic memcpy is now treated in the same was as non-atomic memcpy has always been.
We leave it to later passes to lower longer-length atomic memcpy calls.
Due to the structure of the pass's handling of memtransfer intrinsics, this change
also gives us handling of atomic memmove that we did not previously have.
Reviewers: apilipenko, skatkov, mkazantsev, anna, reames
Reviewed By: reames
Subscribers: reames, llvm-commits
Differential Revision: https://reviews.llvm.org/D46658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332093
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Simon Pilgrim [Fri, 11 May 2018 12:46:54 +0000 (12:46 +0000)]
[X86] Added scheduler helper classes to split move/load/store by size
Nothing uses this yet but this will allow us to specialize MMX/XMM/YMM/ZMM vector moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332090
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Sven van Haastregt [Fri, 11 May 2018 09:45:42 +0000 (09:45 +0000)]
[APFloat] Set losesInfo on no-op convert
losesInfo would be left unset when no conversion needs to be done. A
caller such as InstCombine's fitsInFPType would then branch on an
uninitialized value.
Caught using valgrind on an out-of-tree target.
Differential Revision: https://reviews.llvm.org/D46645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332087
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Jakub Kuderski [Fri, 11 May 2018 09:30:29 +0000 (09:30 +0000)]
[IRTests] Verify PDT instead of DT
Summary: Fix two typos which result in verifying wrong data structures (DT) instead of PDT in DominatorTreeBatchUpdatesTest.
Reviewers: davide, kuhar, grosser, dberlin
Reviewed By: davide, kuhar, dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332086
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