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Craig Topper [Fri, 13 Jul 2018 06:25:31 +0000 (06:25 +0000)]
[X86] Prefer MOVSS/SD over BLEND under optsize in isel.
Previously we iseled to blend, commuted to another blend, and then commuted back to movss/movsd or blend depending on optsize. Now we do it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336976
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Dean Michael Berris [Fri, 13 Jul 2018 05:38:22 +0000 (05:38 +0000)]
[XRay][compiler-rt] Add PID field to llvm-xray tool and add PID metadata record entry in FDR mode
Summary:
llvm-xray changes:
- account-mode - process-id {...} shows after thread-id
- convert-mode - process {...} shows after thread
- parses FDR and basic mode pid entries
- Checks version number for FDR log parsing.
Basic logging changes:
- Update header version from 2 -> 3
FDR logging changes:
- Update header version from 2 -> 3
- in writeBufferPreamble, there is an additional PID Metadata record (after thread id record and tsc record)
Test cases changes:
- fdr-mode.cc, fdr-single-thread.cc, fdr-thread-order.cc modified to catch process id output in the log.
Reviewers: dberris
Reviewed By: dberris
Subscribers: hiraditya, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D49153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336974
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Craig Topper [Fri, 13 Jul 2018 04:50:39 +0000 (04:50 +0000)]
[X86] Remove isel patterns that turns packed add/sub/mul/div+movss/sd into scalar intrinsic instructions.
This is not an optimization we should be doing in isel. This is more suitable for a DAG combine.
My main concern is a future time when we support more FPENV. Changing a packed op to a scalar op could cause us to miss some exceptions that should have occured if we had done a packed op. A DAG combine would be better able to manage this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336971
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Chijun Sima [Fri, 13 Jul 2018 04:02:13 +0000 (04:02 +0000)]
[DomTreeUpdater] Ignore updates when both DT and PDT are nullptrs
Summary:
Previously, when both DT and PDT are nullptrs and the UpdateStrategy is Lazy, DomTreeUpdater still pends updates inside.
After this patch, DomTreeUpdater will ignore all updates from(`applyUpdates()/insertEdge*()/deleteEdge*()`) in this case. (call `delBB()` still pends BasicBlock deletion until a flush event according to the doc).
The behavior of DomTreeUpdater previously documented won't change after the patch.
Reviewers: dmgreen, davide, kuhar, brzycki, grosser
Reviewed By: kuhar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336968
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Joel E. Denny [Fri, 13 Jul 2018 03:08:23 +0000 (03:08 +0000)]
[FileCheck] Implement -v and -vv for tracing matches
-v prints all directive pattern matches.
-vv additionally prints info that might be noise to users but that can
be helpful to FileCheck developers.
To maximize code reuse and to make diagnostics more consistent, this
patch also adjusts and extends some of the existing diagnostics.
CHECK-NOT failures now report variables uses. Many more diagnostics
now report the check prefix and kind of directive.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336967
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Sanjay Patel [Fri, 13 Jul 2018 01:18:07 +0000 (01:18 +0000)]
[InstCombine] return when SimplifyAssociativeOrCommutative makes a change
This bug was created by rL335258 because we used to always call instsimplify
after trying the associative folds. After that change it became possible
for subsequent folds to encounter unsimplified code (and potentially assert
because of it).
Instead of carrying changed state through instcombine, we can just return
immediately. This allows instsimplify to run, so we can continue assuming
that easy folds have already occurred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336965
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Matthias Braun [Fri, 13 Jul 2018 00:08:38 +0000 (00:08 +0000)]
CodeGen: Remove pipeline dependencies on StackProtector; NFC
This re-applies r336929 with a fix to accomodate for the Mips target
scheduling multiple SelectionDAG instances into the pass pipeline.
PrologEpilogInserter and StackColoring depend on the StackProtector analysis
being alive from the point it is run until PEI, which requires that they are all
scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass
between StackProtector and PEI results in these passes being in separate
FunctionPassManagers and the StackProtector is not available for PEI.
PEI and StackColoring don't use much information from the StackProtector pass,
so transfering the required information to MachineFrameInfo is cleaner than
keeping the StackProtector pass around. This commit moves the SSP layout
information to MFI instead of keeping it in the pass.
This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587)
is a first draft of the pagerando implementation described in
http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html.
Patch by Stephen Crane <sjc@immunant.com>
Differential Revision: https://reviews.llvm.org/D49256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336964
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Piotr Padlewski [Thu, 12 Jul 2018 23:55:20 +0000 (23:55 +0000)]
Simplify recursive launder.invariant.group and strip
Summary:
This patch is crucial for proving equality laundered/stripped
pointers. eg:
bool foo(A *a) {
return a == std::launder(a);
}
Clang with -fstrict-vtable-pointers will emit something like:
define dso_local zeroext i1 @_Z3fooP1A(%struct.A* %a) {
entry:
%c = bitcast %struct.A* %a to i8*
%call = tail call i8* @llvm.launder.invariant.group.p0i8(i8* %c)
%0 = bitcast %struct.A* %a to i8*
%1 = tail call i8* @llvm.strip.invariant.group.p0i8(i8* %0)
%2 = tail call i8* @llvm.strip.invariant.group.p0i8(i8* %call)
%cmp = icmp eq i8* %1, %2
ret i1 %cmp
}
and because %2 can be replaced with @llvm.strip.invariant.group(%0)
and that %2 and %1 will produce the same value (because strip is readnone)
we can replace compare with true.
Reviewers: rsmith, hfinkel, majnemer, amharc, kuhar
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D47423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336963
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Matt Davis [Thu, 12 Jul 2018 23:19:30 +0000 (23:19 +0000)]
[llvm-mca] Constify SourceMgr::hasNext. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336961
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Matt Davis [Thu, 12 Jul 2018 22:59:53 +0000 (22:59 +0000)]
[llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage.
Summary:
This patch clears up some of the semantics within the Stage class. Now, preExecute
can be called multiple times per simulated cycle. Previously preExecute was
only called once per cycle, and postExecute could have been called multiple
times.
Now, cycleStart/cycleEnd are called only once per simulated cycle.
preExecute/postExecute can be called multiple times per cycle. This
occurs because multiple execution events can occur during a single cycle.
When stages are executed (Pipeline::runCycle), the postExecute hook will
be called only if all Stages return a success from their 'execute' callback.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D49250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336959
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Craig Topper [Thu, 12 Jul 2018 22:59:03 +0000 (22:59 +0000)]
[X86] Regenerate checks in sse-scalar-fp-arith.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336958
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Fangrui Song [Thu, 12 Jul 2018 22:56:23 +0000 (22:56 +0000)]
[InstCombine] Simplify isKnownNegation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336957
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Craig Topper [Thu, 12 Jul 2018 22:14:10 +0000 (22:14 +0000)]
[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions.
These are the patterns for matching fceil, ffloor, and sqrt to intrinsic instructions if they have a MOVSS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336954
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Craig Topper [Thu, 12 Jul 2018 21:58:03 +0000 (21:58 +0000)]
Revert r336950 and r336951 "[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions." and "foo"
One of them had a bad title and they should have been squashed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336953
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George Burgess IV [Thu, 12 Jul 2018 21:56:31 +0000 (21:56 +0000)]
Remove redundant *_or_null checks; NFC
For the first one, we dereference `NewDef` right before the `if` anyway.
For the second, we shouldn't have NULL users().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336952
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Craig Topper [Thu, 12 Jul 2018 21:53:23 +0000 (21:53 +0000)]
[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions.
These are the patterns for matching fceil, ffloor, and sqrt to intrinsic instructions if they have a MOVSS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336951
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Craig Topper [Thu, 12 Jul 2018 21:53:07 +0000 (21:53 +0000)]
foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336950
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Martin Storsjo [Thu, 12 Jul 2018 21:33:42 +0000 (21:33 +0000)]
Revert "[SLPVectorizer] Add initial alternate opcode support for cast instructions. (REAPPLIED)"
This reverts commit r336812, which broke compilation of a number
of projects, see PR38154.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336949
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Bill Wendling [Thu, 12 Jul 2018 20:35:58 +0000 (20:35 +0000)]
[gold-plugin] Disable section ordering for relocatable links
Not all programs want section ordering when compiled with LTO.
In particular, the Linux kernel is very sensitive when it comes to linking, and
doesn't boot when each function is placed in its own sections.
Reviewed By: pcc
Differential Revision: https://reviews.llvm.org/D48756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336943
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Matt Morehouse [Thu, 12 Jul 2018 20:24:58 +0000 (20:24 +0000)]
[SanitizerCoverage] Add associated metadata to 8-bit counters.
Summary:
This allows counters associated with unused functions to be
dead-stripped along with their functions. This approach is the same one
we used for PC tables.
Fixes an issue where LLD removes an unused PC table but leaves the 8-bit
counter.
Reviewers: eugenis
Reviewed By: eugenis
Subscribers: llvm-commits, hiraditya, kcc
Differential Revision: https://reviews.llvm.org/D49264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336941
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Stefan Pintilie [Thu, 12 Jul 2018 20:18:57 +0000 (20:18 +0000)]
[PowerPC] [NFC] Update __float128 tests
Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to
the __float128 tests. Then modify the tests as required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336940
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Craig Topper [Thu, 12 Jul 2018 19:58:06 +0000 (19:58 +0000)]
[X86][FastISel] Support EVEX version of sqrt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336939
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Craig Topper [Thu, 12 Jul 2018 19:58:01 +0000 (19:58 +0000)]
[X86] Add show-mc-encoding to some fast-isel intrinsic tests so we can observe a failure to select EVEX instructions.
The one I noticed is sqrtsss/sd, but there could be others.
I had to add a couple new tests that don't have insertelement in there to catch this on the fast-isel path. Otherwise we trigger an abort and use SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336938
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Matt Arsenault [Thu, 12 Jul 2018 19:40:16 +0000 (19:40 +0000)]
AMDGPU: Fix assert in truncate combine with vectors
The piece above probably has the same problem, but I need
to try to come up with a test for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336935
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Matthias Braun [Thu, 12 Jul 2018 19:27:01 +0000 (19:27 +0000)]
Revert "(HEAD -> master, origin/master, arcpatch-D37582) CodeGen: Remove pipeline dependencies on StackProtector; NFC"
This was triggering pass scheduling failures.
This reverts commit r336929.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336934
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Matthias Braun [Thu, 12 Jul 2018 18:33:32 +0000 (18:33 +0000)]
CodeGen: Remove pipeline dependencies on StackProtector; NFC
PrologEpilogInserter and StackColoring depend on the StackProtector analysis
being alive from the point it is run until PEI, which requires that they are all
scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass
between StackProtector and PEI results in these passes being in separate
FunctionPassManagers and the StackProtector is not available for PEI.
PEI and StackColoring don't use much information from the StackProtector pass,
so transfering the required information to MachineFrameInfo is cleaner than
keeping the StackProtector pass around. This commit moves the SSP layout
information to MFI instead of keeping it in the pass.
This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587)
is a first draft of the pagerando implementation described in
http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html.
Patch by Stephen Crane <sjc@immunant.com>
Differential Revision: https://reviews.llvm.org/D49256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336929
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Wolfgang Pieb [Thu, 12 Jul 2018 18:18:21 +0000 (18:18 +0000)]
[DWARF v5] Generate range list tables into the .debug_rnglists section. No support for split DWARF
and no use of DW_FORM_rnglistx with the DW_AT_ranges attribute.
Reviewer: aprantl
Differential Revision: https://reviews.llvm.org/D49214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336927
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Craig Topper [Thu, 12 Jul 2018 18:04:05 +0000 (18:04 +0000)]
[X86] Connect the flags user from PCMPISTR instructions to the correct node from the instruction.
We were accidentally connecting it to result 0 instead of result 1. This was caught by the machine verifier that noticed the flags were dead, but we were using them somehow. I'm still not clear what actually happened downstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336925
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Craig Topper [Thu, 12 Jul 2018 18:03:56 +0000 (18:03 +0000)]
[X86][FastISel] Choose EVEX instructions when possible when lowering x86_sse_cvttss2si and similar intrinsics.
This should fix a machine verifier error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336924
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Galina Kistanova [Thu, 12 Jul 2018 17:58:10 +0000 (17:58 +0000)]
Reverted r336805 as it broke llvm-clang-x86_64-expensive-checks-win build bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336923
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Stephen Hines [Thu, 12 Jul 2018 17:42:17 +0000 (17:42 +0000)]
Add --strip-all option back to llvm-strip.
Summary:
This option appears to have been dropped as part of the refactoring in
r331663. Unfortunately, if we want to use llvm-strip as a drop-in
replacement for strip, this option should still be available.
Reviewers: alexshap
Reviewed By: alexshap
Subscribers: meikeb, kongyi, chh, jakehehrlich, llvm-commits, pirama
Differential Revision: https://reviews.llvm.org/D49226
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336921
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Roman Lebedev [Thu, 12 Jul 2018 17:00:11 +0000 (17:00 +0000)]
[NFC][X86][AArch64] Add tests for the 'check for [no] signed truncation' pattern
Summary:
[[ https://bugs.llvm.org/show_bug.cgi?id=38149 | PR38149 ]]
As discussed in https://reviews.llvm.org/D49179#
1158957 and later,
the IR can be improved:
https://rise4fun.com/Alive/gBf
^ that pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958
https://bugs.llvm.org/show_bug.cgi?id=21530
in signed case, therefore it is probably a good idea to improve it.
But as it looks from these tests,
i think we want to revert at least some cases in DAGCombine.
Reviewers: spatel, craig.topper, RKSimon, javed.absar
Reviewed By: spatel
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D49247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336917
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Matt Davis [Thu, 12 Jul 2018 16:56:17 +0000 (16:56 +0000)]
[llvm-mca] Simplify eventing by adding an onEvent templated method.
Summary:
This patch eliminates some redundancy in iterating across Listeners for the
Instruction and Stall HWEvents, by introducing a template onEvent routine.
This change was suggested by @courbet in https://reviews.llvm.org/D48576. I
hope that this patch addresses that suggestion appropriately. I do like this
change better than what we had previously.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb, courbet
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits, courbet
Differential Revision: https://reviews.llvm.org/D48672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336916
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Sjoerd Meijer [Thu, 12 Jul 2018 14:59:02 +0000 (14:59 +0000)]
Follow up of r336913: forgot to add the new test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336914
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Sjoerd Meijer [Thu, 12 Jul 2018 14:57:59 +0000 (14:57 +0000)]
[AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions
These instructions are added to AArch64 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336913
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Roman Lebedev [Thu, 12 Jul 2018 14:56:17 +0000 (14:56 +0000)]
[InstCombine] icmp-logical.ll: restore the original intention of the test.
While that fold is clearly not happening [anymore],
we do now have separate test cases for these cases,
so we should be ok to slightly adjust these tests
to not potentially loose test coverage.
As suggested by Hiroshi Yamauchi in
https://reviews.llvm.org/D49179#
1159345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336912
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Roman Lebedev [Thu, 12 Jul 2018 14:56:12 +0000 (14:56 +0000)]
[InstCombine] Fold x & (-1 >> y) != x to x u> (-1 >> y)
Summary:
A complementary fold to D49179.
https://bugs.llvm.org/show_bug.cgi?id=38123
https://rise4fun.com/Alive/Rny
Caveat: one more thing in `test/Transforms/InstCombine/icmp-logical.ll` breaks.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336911
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Andrew Ng [Thu, 12 Jul 2018 14:40:21 +0000 (14:40 +0000)]
[ThinLTO] Escape module paths when printing
We have located a bug in AssemblyWriter::printModuleSummaryIndex(). This
function outputs path strings incorrectly. Backslashes in the strings
are not correctly escaped.
Consequently, if a path name contains a backslash followed by two
hexadecimal characters, the sequence is incorrectly interpreted when the
output is read by another component. This mangles the path and results
in error.
This patch fixes this issue by calling printEscapedString() to output
the module paths.
Patch by Chris Jackson.
Differential Revision: https://reviews.llvm.org/D49090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336908
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Francis Visoiu Mistrih [Thu, 12 Jul 2018 14:36:48 +0000 (14:36 +0000)]
[DebugInfo][X86] Add start-after flags to MIR tests
These tests would fail with -verify-machineinstrs because the MI
generated from the IR would be merged with the one already in the MIR
files, and we get the following error:
```
*** Bad machine code: Function has NoVRegs property but there are VReg operands ***
- function: f
```
Differential Revision: https://reviews.llvm.org/D49191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336907
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Francis Visoiu Mistrih [Thu, 12 Jul 2018 14:36:43 +0000 (14:36 +0000)]
[XRay] Fix machine verifier issues in X86
I'm not sure if this fix is the right thing to do, but it seemed to me
that PATCHABLE_RET and PATCHABLE_TAIL_CALL don't have any defs.
Running the following:
```
LLVM_ENABLE_MACHINE_VERIFIER=1 ./build/bin/llvm-lit -v -a test/CodeGen/X86/xray-*
```
results in the following tests to fail (along others):
```
LLVM :: CodeGen/X86/xray-attribute-instrumentation.ll
LLVM :: CodeGen/X86/xray-custom-log.ll
LLVM :: CodeGen/X86/xray-log-args.ll
LLVM :: CodeGen/X86/xray-loop-detection.ll
LLVM :: CodeGen/X86/xray-multiplerets-in-blocks.mir
LLVM :: CodeGen/X86/xray-section-group.ll
LLVM :: CodeGen/X86/xray-selective-instrumentation.ll
LLVM :: CodeGen/X86/xray-tail-call-sled.ll
LLVM :: CodeGen/X86/xray-typed-event-log.ll
```
The errors are:
```
*** Bad machine code: Explicit definition must be a register ***
- function: fn
- basic block: %bb.0 (0x7fa31a84d908)
- instruction: PATCHABLE_RET 2560, $eax
- operand 0: 2560
```
and
```
*** Bad machine code: Explicit definition must be a register ***
- function: caller
- basic block: %bb.0 (0x7fbff3044108)
- instruction: PATCHABLE_TAIL_CALL 3009, @callee, <regmask $bh $bl $bp $bph $bpl $bx $ebp $ebx $hbp $hbx $rbp $rbx $r12 $r13 $r14 $r15 $r12b $r13b $r14b $r15b $r12bh $r13bh $r14bh $r15bh $r12d $r13d $r14d $r15d $r12w $r13w $r14w $r15w $r12wh and 3 more...>, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $edi
- operand 0: 3009
```
Differential Revision: https://reviews.llvm.org/D49187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336906
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 12 Jul 2018 13:29:41 +0000 (13:29 +0000)]
[X86][SSE] Utilize ZeroableElements for canWidenShuffleElements
canWidenShuffleElements can do a better job if given a mask with ZeroableElements info. Apparently, ZeroableElements was being only used to identify AllZero candidates, but possibly we could plug it into more shuffle matchers.
Original Patch by Zvi Rackover @zvi
Differential Revision: https://reviews.llvm.org/D42044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336903
91177308-0d34-0410-b5e6-
96231b3b80d8
Chen Zheng [Thu, 12 Jul 2018 13:28:20 +0000 (13:28 +0000)]
[InstCombine]add testcases for folding more SPFofSPF pattern
Differential Revision: https://reviews.llvm.org/D49222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336902
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 12 Jul 2018 13:03:58 +0000 (13:03 +0000)]
[X86][AVX] Use Zeroable mask to improve shuffle mask widening
Noticed while updating D42044, lowerV2X128VectorShuffle can improve the shuffle mask with the zeroable data to create a target shuffle mask to recognise more 'zero upper 128' patterns.
NOTE: lowerV4X128VectorShuffle could benefit as well but the code needs refactoring first to discriminate between SM_SentinelUndef and SM_SentinelZero for negative shuffle indices.
Differential Revision: https://reviews.llvm.org/D49092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336900
91177308-0d34-0410-b5e6-
96231b3b80d8
David Green [Thu, 12 Jul 2018 10:44:47 +0000 (10:44 +0000)]
[UnJ] Use SmallPtrSets for block collections. NFC
We no longer care about the order of blocks in these collections,
so can change to SmallPtrSets, making contains checks quicker.
Differential revision: https://reviews.llvm.org/D49060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336897
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 12 Jul 2018 09:10:55 +0000 (09:10 +0000)]
Fix -Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336895
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 12 Jul 2018 09:04:28 +0000 (09:04 +0000)]
[X86] Add UDIV by uniform/non-uniform constant tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336894
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Thu, 12 Jul 2018 08:50:11 +0000 (08:50 +0000)]
[mips] Mark standard encoded instructions as not being in MIPS16e
Mark standard encoded instructions and pseudo "standard encoded"
as not being in MIPS16e by default.
Patch by Simon Dardis.
Differential revision: https://reviews.llvm.org/D48379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336893
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 07:30:01 +0000 (07:30 +0000)]
[X86] Remove i128 type from FR128 regclass.
i128 isn't a legal type in our x86 implementation today. So remove this and the few patterns that used it until it becomes necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336889
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam McCall [Thu, 12 Jul 2018 07:11:28 +0000 (07:11 +0000)]
[Support] Require llvm::Error passed to formatv() to be wrapped in fmt_consume()
Summary:
Someone must be responsible for handling an Error. When formatv takes
ownership of an Error, the formatv_object destructor must take care of this.
Passing an error by value to formatv() is not considered explicit enough to mark
the error as handled (see D49013), so we require callers to use a format adapter
to confirm this intent.
Reviewers: zturner
Subscribers: llvm-commits, lhames
Differential Revision: https://reviews.llvm.org/D49170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336888
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Granitz [Thu, 12 Jul 2018 06:41:41 +0000 (06:41 +0000)]
Fix few typos in comments (write access test commit)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336887
91177308-0d34-0410-b5e6-
96231b3b80d8
Chijun Sima [Thu, 12 Jul 2018 04:08:14 +0000 (04:08 +0000)]
[Dominators] Add isUpdateLazy() method to the DomTreeUpdater
Summary:
Previously, when people need to deal with DTU with different UpdateStrategy using different actions, they need to
```
if (DTU.getUpdateStrategy() == DomTreeUpdater::UpdateStrategy::Lazy) {
...
}
if (DTU.getUpdateStrategy() == DomTreeUpdater::UpdateStrategy::Eager) {
...
}
```
After the patch, they can avoid code patterns above
```
if (DTU.isUpdateLazy()){
...
}
if (!DTU.isUpdateLazy()){
...
}
```
Reviewers: kuhar, brzycki, dmgreen
Reviewed By: kuhar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336886
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 03:42:41 +0000 (03:42 +0000)]
[X86] Remove patterns and ISD nodes for the old scalar FMA intrinsic lowering.
We now use llvm.fma.f32/f64 or llvm.x86.fmadd.f32/f64 intrinsics that use scalar types rather than vector types. So we don't these special ISD nodes that operate on the lowest element of a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336883
91177308-0d34-0410-b5e6-
96231b3b80d8
Chen Zheng [Thu, 12 Jul 2018 03:06:04 +0000 (03:06 +0000)]
[InstSimplify] simplify add instruction if two operands are negative
Differential Revision: https://reviews.llvm.org/D49216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336881
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Thu, 12 Jul 2018 02:03:53 +0000 (02:03 +0000)]
[AsmParser] Fix inconsistent declaration parameter name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336879
91177308-0d34-0410-b5e6-
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Eric Christopher [Thu, 12 Jul 2018 01:53:21 +0000 (01:53 +0000)]
Temporarily revert "Recommit r328307: [IPSCCP] Use constant range information for comparisons of parameters." as it's causing miscompiles.
A testcase was provided in the original review thread.
This reverts commit r336098.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336877
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 12 Jul 2018 01:43:21 +0000 (01:43 +0000)]
[x86] Fix another trivial bug in x86 flags copy lowering that has been
there for a long time.
The boolean tracking whether we saw a kill of the flags was supposed to
be per-block we are scanning and instead was outside that loop and never
cleared. It requires a quite contrived test case to hit this as you have
to have multiple levels of successors and interleave them with kills.
I've included such a test case here.
This is another bug found testing SLH and extracted to its own focused
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336876
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 00:54:40 +0000 (00:54 +0000)]
[X86] Add patterns to use VMOVSS/SD zero masking for scalar f32/f64 select with zero.
These showed up in some of the upgraded FMA code. We really need to improve these test cases more, but this helps for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336875
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 12 Jul 2018 00:52:50 +0000 (00:52 +0000)]
[x86] Fix EFLAGS copy lowering to correctly handle walking past uses in
multiple successors where some of the uses end up killing the EFLAGS
register.
There was a bug where rather than skipping to the next basic block
queued up with uses once we saw a kill, we stopped processing the blocks
entirely. =/
Test case produces completely nonsensical code w/o this tiny fix.
This was found testing Speculative Load Hardening and split out of that
work.
Differential Revision: https://reviews.llvm.org/D49211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336874
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 00:29:56 +0000 (00:29 +0000)]
[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
This converts them to what clang is now using for codegen. Unfortunately, there seem to be a few kinks to work out still. I'll try to address with follow up patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336871
91177308-0d34-0410-b5e6-
96231b3b80d8
Eric Christopher [Thu, 12 Jul 2018 00:01:51 +0000 (00:01 +0000)]
Add -allow-deprecated-dag-overlap to one of the experimental webassembly target tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336870
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Wed, 11 Jul 2018 23:30:25 +0000 (23:30 +0000)]
IR: Skip -print-*-all after -print-*
This changes `-print-*` from transformation passes to analysis passes so
that `-print-after-all` and `-print-before-all` don't trigger. This
avoids some redundant output.
Patch by Son Tuan Vu!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336869
91177308-0d34-0410-b5e6-
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Eli Friedman [Wed, 11 Jul 2018 23:26:35 +0000 (23:26 +0000)]
[CodeGen] Emit more precise AssertZext/AssertSext nodes.
This is marginally helpful for removing redundant extensions, and the
code is easier to read, so it seems like an all-around win. In the new
test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an
AssertZext i2, which allows the extension of the return value to be
eliminated.
Differential Revision: https://reviews.llvm.org/D49004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336868
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 11 Jul 2018 22:35:28 +0000 (22:35 +0000)]
[LoopIdiomRecognize] Don't convert a do while loop to ctlz.
This commit suppresses turning loops like this into "(bitwidth - ctlz(input))".
unsigned foo(unsigned input) {
unsigned num = 0;
do {
++num;
input >>= 1;
} while (input != 0);
return num;
}
The loop version returns a value of 1 for both an input of 0 and an input of 1. Converting to a naive ctlz does not preserve that.
Theoretically we could do better if we checked isKnownNonZero or we could insert a select to handle the divergence. But until we have motivating cases for that, this is the easiest solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336864
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 11 Jul 2018 22:17:26 +0000 (22:17 +0000)]
[LoopIdiomRecognize] Add a test case showing a loop we turn into ctlz that we shouldn't.
This loop executes one iteration without checking the input value. This produces a count of 1 for an input of 0 and 1. We are turning this into 32 - ctlz(n), but that returns 0 if n is 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336862
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Wed, 11 Jul 2018 22:15:15 +0000 (22:15 +0000)]
AMDGPU/SI: Initialize InstrInfo before TargetLoweringInfo in GCNSubtarget
SITargetLowering queries SIInstrInfo in its constructor, so SIInstrInfo
must be initialized first. This fixes msan buildbot failures and was
introduced by r336851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336861
91177308-0d34-0410-b5e6-
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Alina Sbirlea [Wed, 11 Jul 2018 22:11:46 +0000 (22:11 +0000)]
[MemorySSA] Add APIs to move memory accesses between blocks, following CFG changes.
Summary:
The move APIs added in this patch will be used to update MemorySSA when CFG changes merge or split blocks, by moving memory accesses accordingly in MemorySSA's internal data structures.
[Split from D45299 for easier review]
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D48897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336860
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Wed, 11 Jul 2018 21:47:55 +0000 (21:47 +0000)]
Temporarily reverting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336858
91177308-0d34-0410-b5e6-
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Roman Lebedev [Wed, 11 Jul 2018 21:28:42 +0000 (21:28 +0000)]
[NFC][InstCombine] Tests for x & (-1 >> y) != x -> x u> (-1 >> y) fold
https://bugs.llvm.org/show_bug.cgi?id=38123
https://rise4fun.com/Alive/Rny
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336857
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Wed, 11 Jul 2018 21:12:03 +0000 (21:12 +0000)]
AMDGPU: Remove duplicate call to initializeSubtargetDependencies()
This was added in r336851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336853
91177308-0d34-0410-b5e6-
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Tom Stellard [Wed, 11 Jul 2018 20:59:01 +0000 (20:59 +0000)]
AMDGPU: Refactor Subtarget classes
Summary:
This is a follow-up to r335942.
- Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget
- Rename AMDGPUCommonSubtarget to AMDGPUSubtarget
- Merge R600Subtarget::Generation and GCNSubtarget::Generation into
AMDGPUSubtarget::Generation.
Reviewers: arsenm, jvesely
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D49037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336851
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel E. Denny [Wed, 11 Jul 2018 20:31:51 +0000 (20:31 +0000)]
finish: [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
Differential Revision: https://reviews.llvm.org/D47171
This contains the portions of that patch that could not be committed
using the git monorepo because of dos line ending problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336848
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel E. Denny [Wed, 11 Jul 2018 20:27:27 +0000 (20:27 +0000)]
[FileCheck] Don't permit overlapping CHECK-DAG
That is, make CHECK-DAG skip matches that overlap the matches of any
preceding consecutive CHECK-DAG directives. This change makes
CHECK-DAG more consistent with other directives, and there is evidence
it makes CHECK-DAG more intuitive and less error-prone. See the RFC
discussion starting at:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123010.html
Moreover, this behavior enables CHECK-DAG groups for unordered,
non-unique strings or patterns. For example, it is useful for
verifying output or logs from a parallel program, such as the OpenMP
runtime.
This patch also implements the command-line option
-allow-deprecated-dag-overlap, which reverts CHECK-DAG to the old
overlapping behavior. This option should not be used in new tests.
It is meant only for the existing tests that are broken by this change
and that need time to update.
See the following bugzilla issue for tracking of such tests:
https://bugs.llvm.org/show_bug.cgi?id=37532
Patches to add -allow-deprecated-dag-overlap to those tests will
follow immediately.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336847
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel E. Denny [Wed, 11 Jul 2018 20:25:49 +0000 (20:25 +0000)]
[FileCheck] Add -allow-deprecated-dag-overlap to failing llvm tests
See https://reviews.llvm.org/D47106 for details.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47171
This commit drops that patch's changes to:
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
llvm/test/CodeGen/NVPTX/param-load-store.ll
For some reason, the dos line endings there prevent me from commiting
via the monorepo. A follow-up commit (not via the monorepo) will
finish the patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336843
91177308-0d34-0410-b5e6-
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Teresa Johnson [Wed, 11 Jul 2018 20:08:32 +0000 (20:08 +0000)]
Revert "[docs] As of binutils 2.21.51.0.2, ld.bfd supports plugins too, represent this in docs"
This reverts commit r306102.
This change was made without any review, and has a couple of issues.
First, AFAIK we do not test the combination of the LLVM gold plugin with
ld.bfd. Second, the change removed documentation for how to build gold
and replaced it with instructions for building ld.bfd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336841
91177308-0d34-0410-b5e6-
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Bill Wendling [Wed, 11 Jul 2018 19:13:26 +0000 (19:13 +0000)]
gold: Add ability to toggle function/data sections
Some programs (e.g. Linux) aren't able to handle function/data sections when
LTO is used. Thus they need a way to disable it. That can be done with these
plugin options:
-plugin-opt=-function-sections=0
-plugin-opt=-data-sections=0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336838
91177308-0d34-0410-b5e6-
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Fangrui Song [Wed, 11 Jul 2018 19:09:37 +0000 (19:09 +0000)]
[DebugInfo] Fix getPreviousSibling after r336823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336837
91177308-0d34-0410-b5e6-
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Roman Lebedev [Wed, 11 Jul 2018 19:05:04 +0000 (19:05 +0000)]
[InstCombine] Fold x & (-1 >> y) == x to x u<= (-1 >> y)
Summary:
https://bugs.llvm.org/show_bug.cgi?id=38123
This pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958
https://bugs.llvm.org/show_bug.cgi?id=21530
in unsigned case, therefore it is probably a good idea to improve it.
https://rise4fun.com/Alive/Rny
^ there are more opportunities for folds, i will follow up with them afterwards.
Caveat: this somehow exposes a missing opportunities
in `test/Transforms/InstCombine/icmp-logical.ll`
It seems, the problem is in `foldLogOpOfMaskedICmps()` in `InstCombineAndOrXor.cpp`.
But i'm not quite sure what is wrong, because it calls `getMaskedTypeForICmpPair()`,
which calls `decomposeBitTestICmp()` which should already work for these cases...
As @spatel notes in https://reviews.llvm.org/D49179#
1158760,
that code is a rather complex mess, so we'll let it slide.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: yamauchi, majnemer, t.p.northover, llvm-commits
Differential Revision: https://reviews.llvm.org/D49179
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336834
91177308-0d34-0410-b5e6-
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Joel E. Denny [Wed, 11 Jul 2018 19:03:00 +0000 (19:03 +0000)]
Revert r336830: [FileCheck] Don't permit overlapping CHECK-DAG
Companion patches are failing to commit, and this patch alone breaks
many tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336833
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Wed, 11 Jul 2018 18:51:15 +0000 (18:51 +0000)]
Quick fix for some Windows bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336832
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel E. Denny [Wed, 11 Jul 2018 18:42:58 +0000 (18:42 +0000)]
[FileCheck] Don't permit overlapping CHECK-DAG
That is, make CHECK-DAG skip matches that overlap the matches of any
preceding consecutive CHECK-DAG directives. This change makes
CHECK-DAG more consistent with other directives, and there is evidence
it makes CHECK-DAG more intuitive and less error-prone. See the RFC
discussion starting at:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123010.html
Moreover, this behavior enables CHECK-DAG groups for unordered,
non-unique strings or patterns. For example, it is useful for
verifying output or logs from a parallel program, such as the OpenMP
runtime.
This patch also implements the command-line option
-allow-deprecated-dag-overlap, which reverts CHECK-DAG to the old
overlapping behavior. This option should not be used in new tests.
It is meant only for the existing tests that are broken by this change
and that need time to update.
See the following bugzilla issue for tracking of such tests:
https://bugs.llvm.org/show_bug.cgi?id=37532
Patches to add -allow-deprecated-dag-overlap to those tests will
follow immediately.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336830
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Semel [Wed, 11 Jul 2018 18:09:52 +0000 (18:09 +0000)]
Revert "[llvm-objdump] Add -demangle (-C) option"
This reverts commit
3a44ccd156e0edd2e89226f8ed63928e227900bb.
This reverts commit
d5cfc836bb5552e20507d3612d13ff66ff9e36a0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336829
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 11 Jul 2018 18:09:04 +0000 (18:09 +0000)]
[X86] Remove patterns for inserting a load into a zero vector.
We can instead block the load folding isProfitableToFold. Then isel will emit a register->register move for the zeroing part and a separate load. The PostProcessISelDAG should be able to remove the register->register move.
This saves us patterns and fixes the fact that we only had unaligned load patterns. The test changes show places where we should have been using an aligned load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336828
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 11 Jul 2018 17:51:27 +0000 (17:51 +0000)]
[TargetTransformInfo] Add pow2 analysis for scalar constants
Add ConstantInt analysis to getOperandInfo so we get more realistic div/rem expansion costs comparable to the vector costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336827
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Wed, 11 Jul 2018 17:27:17 +0000 (17:27 +0000)]
AMDGPU/NFC: Use already available explicit kernarg
size instead of calculating it again when filling
out the metadata.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336825
91177308-0d34-0410-b5e6-
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Jonas Devlieghere [Wed, 11 Jul 2018 17:11:11 +0000 (17:11 +0000)]
[DebugInfo] Make children iterator bidirectional
Make the DIE iterator bidirectional so we can move to the previous
sibling of a DIE.
Differential revision: https://reviews.llvm.org/D49173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336823
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Sanjay Patel [Wed, 11 Jul 2018 16:52:18 +0000 (16:52 +0000)]
[InstSimplify] add/move tests for add folds; NFC
isKnownNegation() is currently proposed as part of D48754,
but it could be used to make InstSimplify stronger independently
of any abs() improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336822
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Paul Semel [Wed, 11 Jul 2018 16:31:33 +0000 (16:31 +0000)]
Fix llvm-objdump demangle test (added triple option)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336821
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Andrea Di Biagio [Wed, 11 Jul 2018 15:27:50 +0000 (15:27 +0000)]
[X86] Fix MayLoad/HasSideEffect flag for (V)MOVLPSrm instructions.
Before revision 336728, the "mayLoad" flag for instruction (V)MOVLPSrm was
inferred directly from the "default" pattern associated with the instruction
definition.
r336728 removed special node X86Movlps, and all the patterns associated to it.
Now instruction (V)MOVLPSrm doesn't have a pattern associated to it, and the
'mayLoad/hasSideEffects' flags are left unset.
When the instruction info is emitted by tablegen, method
CodeGenDAGPatterns::InferInstructionFlags() sees that (V)MOVLPSrm doesn't have a
pattern, and flags are undefined. So, it conservatively sets the
"hasSideEffects" flag for it.
As a consequence, we were losing the 'mayLoad' flag, and we were gaining a
'hasSideEffect' flag in its place.
This patch fixes the issue (originally reported by Michael Holmen).
The mca tests show the differences in the instruction info flags. Instructions
that were affected by this problem were: MOVLPSrm/VMOVLPSrm/VMOVLPSZ128rm.
Differential Revision: https://reviews.llvm.org/D49182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336818
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Paul Semel [Wed, 11 Jul 2018 15:25:39 +0000 (15:25 +0000)]
[llvm-objdump] Add -demangle (-C) option
Differential Revision: https://reviews.llvm.org/D49043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336816
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Simon Pilgrim [Wed, 11 Jul 2018 15:05:10 +0000 (15:05 +0000)]
[SLPVectorizer] Add initial alternate opcode support for cast instructions. (REAPPLIED)
We currently only support binary instructions in the alternate opcode shuffles.
This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism:
1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly.
2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this.
3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc.
4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements.
Reapplied with fix to only accept 2 different casts if they come from the same source type.
Differential Revision: https://reviews.llvm.org/D49135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336812
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Simon Pilgrim [Wed, 11 Jul 2018 14:34:43 +0000 (14:34 +0000)]
[SLPVectorizer] Ensure alternate/passthrough doesn't vectorize sdiv with undef elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336809
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Simon Pilgrim [Wed, 11 Jul 2018 14:29:13 +0000 (14:29 +0000)]
[SLPVectorizer] Add some additional alternate cast tests
Initial attempt at D49135 failed as we weren't correctly handling casts with different source types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336808
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Simon Pilgrim [Wed, 11 Jul 2018 14:08:16 +0000 (14:08 +0000)]
Revert rL336804: [SLPVectorizer] Add initial alternate opcode support for cast instructions.
Reverting due to buildbot failures
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336806
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Florian Hahn [Wed, 11 Jul 2018 13:39:59 +0000 (13:39 +0000)]
Recommit r334887: [SmallSet] Add SmallSetIterator.
This version now uses the subset of is_trivially_XXX provided by
GCC 4.8 and llvm/Support/type_traits.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336805
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Simon Pilgrim [Wed, 11 Jul 2018 13:34:09 +0000 (13:34 +0000)]
[SLPVectorizer] Add initial alternate opcode support for cast instructions.
We currently only support binary instructions in the alternate opcode shuffles.
This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism:
1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly.
2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this.
3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc.
4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements.
Differential Revision: https://reviews.llvm.org/D49135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336804
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Krzysztof Parzyszek [Wed, 11 Jul 2018 13:30:27 +0000 (13:30 +0000)]
[CodeGen] Ignore debug uses in MachineCopyPropagation
Debug uses should not count as real uses, since the presence of debug
information could affect the generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336803
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Simon Atanasyan [Wed, 11 Jul 2018 13:21:10 +0000 (13:21 +0000)]
[mips] Update the P5600 scheduler model not to use instruction itineraries.
This mostly brings the P5600 scheduler model to a mostly complete
status. There are a number of instructions which trigger the
`error:'MipsP5600Model' lacks information for` error. These are certain
codegen only instructions relating to MIPS64 which can be addressed by
using the correct predicates for them. That will be done in a full-up
patch.
Patch by Simon Dardis.
Differential revision: https://reviews.llvm.org/D45245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336802
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Diogo N. Sampaio [Wed, 11 Jul 2018 12:59:42 +0000 (12:59 +0000)]
[NFC][InstCombine] Converts isLegalNarrowLoad into isLegalNarrowLdSt
Reuse this function as to test correctness and profitability of
reducing width of either load or store operations.
Reviewsers: samparker
Differential Revision: https://reviews.llvm.org/D48624
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336800
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Andrea Di Biagio [Wed, 11 Jul 2018 12:44:44 +0000 (12:44 +0000)]
[llvm-mca] Use a different character to flag instructions with side-effects in the Instruction Info View. NFC
This makes easier to identify changes in the instruction info flags. It also
helps spotting potential regressions similar to the one recently introduced at
r336728.
Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic
for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and
spaces. A change in position of the flag marker may not trigger a test failure.
This patch only changes the character used for flag `hasSideEffects`. The reason
why I didn't touch other flags is because I want to avoid spamming the mailing
because of the massive diff due to the numerous tests affected by this change.
In future, each instruction flag should be associated with a different character
in the Instruction Info View.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336797
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Roman Lebedev [Wed, 11 Jul 2018 12:37:12 +0000 (12:37 +0000)]
[NFC][InstCombine] Tests for x & (-1 >> y) == x -> x u<= (-1 >> y) fold
https://bugs.llvm.org/show_bug.cgi?id=38123
This pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958
https://bugs.llvm.org/show_bug.cgi?id=21530
in unsigned case, therefore it is probably a good idea to improve it.
https://rise4fun.com/Alive/Rny
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336796
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