OSDN Git Service
Craig Topper [Thu, 11 Jul 2019 01:01:39 +0000 (01:01 +0000)]
[X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.
We use the functions that convert to three address to do the
conversion, but changing an 8 or 16 bit will cause it to create
a virtual register. This can't be done after register allocation
where this pass runs.
I've switched the pass completely to a white list of instructions
that can be converted to LEA instead of a blacklist that was
incorrect. This will avoid surprises if we enhance the three
address conversion function to include additional instructions
in the future.
Fixes PR42565.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365720
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 11 Jul 2019 00:10:17 +0000 (00:10 +0000)]
[AMDGPU] gfx908 atomic fadd and atomic pk_fadd
Differential Revision: https://reviews.llvm.org/D64435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365717
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 11 Jul 2019 00:00:27 +0000 (00:00 +0000)]
[AMDGPU] gfx908 dot instruction support
Differential Revision: https://reviews.llvm.org/D64431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365715
91177308-0d34-0410-b5e6-
96231b3b80d8
Jordan Rupprecht [Wed, 10 Jul 2019 23:32:44 +0000 (23:32 +0000)]
Revert [llvm-objcopy] Allow strip symtab from executables and DSOs
This reverts r365193 (git commit
194f16b3548bcb23a7f0fd638778ed72edd18d37)
This patch doesn't work with binaries built w/ `--emit-relocs`, e.g.
```
$ echo 'int main() { return 0; }' | clang -Wl,--emit-relocs -x c - -o foo && llvm-objcopy --strip-unneeded foo
llvm-objcopy: error: 'foo': not stripping symbol '__gmon_start__' because it is named in a relocation
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365712
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 10 Jul 2019 23:23:54 +0000 (23:23 +0000)]
[SDAG] commute setcc operands to match a subtract
If we have:
R = sub X, Y
P = cmp Y, X
...then flipping the operands in the compare instruction can allow using a subtract that sets compare flags.
Motivated by diffs in D58875 - not sure if this changes anything there,
but this seems like a good thing independent of that.
There's a more involved version of this transform already in IR (in instcombine
although that seems misplaced to me) - see "swapMayExposeCSEOpportunities()".
Differential Revision: https://reviews.llvm.org/D63958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365711
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Wed, 10 Jul 2019 22:56:15 +0000 (22:56 +0000)]
Add IsBytewiseValue unit test
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365710
91177308-0d34-0410-b5e6-
96231b3b80d8
Vitaly Buka [Wed, 10 Jul 2019 22:53:52 +0000 (22:53 +0000)]
NFC: Pass DataLayout into isBytewiseValue
Summary:
We will need to handle IntToPtr which I will submit in a separate patch as it's
not going to be NFC.
Reviewers: eugenis, pcc
Reviewed By: eugenis
Subscribers: hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D63940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365709
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 10 Jul 2019 22:44:32 +0000 (22:44 +0000)]
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
Fixes similar issues to r352306.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365705
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 10 Jul 2019 22:44:24 +0000 (22:44 +0000)]
[X86] Add a few more TBM and BLSI test cases that show the same issue that r352306 fixed for BLSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365704
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 10 Jul 2019 22:14:39 +0000 (22:14 +0000)]
[X86] Add BLSR and BLSMSK to isUseDefConvertible.
Unfortunately subo formation in CGP prevents obvious ways of
testing this.
But we already have BLSI in here and the flag behavior is
well understood.
Might become more useful if we improve PR42571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365702
91177308-0d34-0410-b5e6-
96231b3b80d8
David Tenty [Wed, 10 Jul 2019 22:13:55 +0000 (22:13 +0000)]
[NFC]Fix IR/MC depency issue for function descriptor SDAG implementation
Summary: llvm/IR/GlobalValue.h can't be included in MC, that creates a circular dependency between MC and IR libraries. This circular dependency is causing an issue for build system that enforce layering.
Author: Xiangling_L
Reviewers: sfertile, jasonliu, hubert.reinterpretcast, gribozavr
Reviewed By: gribozavr
Subscribers: wuzish, nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365701
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 10 Jul 2019 21:01:34 +0000 (21:01 +0000)]
[X86] Remove unused variable. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365697
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 10 Jul 2019 19:58:13 +0000 (19:58 +0000)]
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365694
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 10 Jul 2019 19:31:25 +0000 (19:31 +0000)]
Add support for building with Python 3
LLDB supports Python 3 now.
Differential Revision: https://reviews.llvm.org/D64443
Patch from Christian Biesinger <cbiesinger@google.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365692
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Wed, 10 Jul 2019 19:21:43 +0000 (19:21 +0000)]
[AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and unknown values.
Since we have distinct types for pointers and scalars, G_INTTOPTRs can sometimes
obstruct attempts to find constant source values. These usually come about when
try to do some kind of null pointer check. Teaching getConstantVRegValWithLookThrough
about this operation allows the CBZ/CBNZ optimization to catch more cases.
This change also improves the case where we can't find a constant source at all.
Previously we would emit a cmp, cset and tbnz for that. Now we try to just emit
a cmp and conditional branch, saving an instruction.
The cumulative code size improvement of this change plus D64354 is 5.5% geomean
on arm64 CTMark -O0.
Differential Revision: https://reviews.llvm.org/D64377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365690
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 10 Jul 2019 19:20:17 +0000 (19:20 +0000)]
gn build: Merge r365687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365689
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikola Prica [Wed, 10 Jul 2019 18:58:05 +0000 (18:58 +0000)]
Revert "[ELF] Loose a condition for relocation with a symbol"
This reverts commit
8507eca1647118e73435b0ce1de8a1952a021d01.
Reveting due to some suspicious failurse in santizer-x86_64-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365685
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Wed, 10 Jul 2019 18:46:56 +0000 (18:46 +0000)]
[GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromReg
Some minor cleanup.
This function in Utils does the same thing as `findMIFromReg`. It also looks
through copies, which `findMIFromReg` didn't.
Delete `findMIFromReg` and use `getOpcodeDef` instead. This only happens in
`tryOptVectorDup` right now.
Update opt-shuffle-splat to show that we can look through the copies now, too.
Differential Revision: https://reviews.llvm.org/D64520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365684
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Wed, 10 Jul 2019 18:44:57 +0000 (18:44 +0000)]
[GlobalISel][AArch64][NFC] Use getDefIgnoringCopies from Utils where we can
There are a few places where we walk over copies throughout
AArch64InstructionSelector.cpp. In Utils, there's a function that does exactly
this which we can use instead.
Note that the utility function works with the case where we run into a COPY
from a physical register. We've run into bugs with this a couple times, so using
it should defend us from similar future bugs.
Also update opt-fold-compare.mir to show that we still handle physical registers
properly.
Differential Revision: https://reviews.llvm.org/D64513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365683
91177308-0d34-0410-b5e6-
96231b3b80d8
David Greene [Wed, 10 Jul 2019 18:25:58 +0000 (18:25 +0000)]
Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"
This broke some PPC prefetching tests.
This reverts commit
9fdfb045ae8bb643ab0d0455dcf9ecaea3b1eb3c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365680
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Berg [Wed, 10 Jul 2019 18:23:26 +0000 (18:23 +0000)]
Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang. I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it. Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context.
Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm
Reviewed By: arsenm
Subscribers: michele.scandale, wdng, javed.absar
Differential Revision: https://reviews.llvm.org/D64450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365679
91177308-0d34-0410-b5e6-
96231b3b80d8
David Greene [Wed, 10 Jul 2019 18:07:01 +0000 (18:07 +0000)]
[System Model] [TTI] Update cache and prefetch TTI interfaces
Rework the TTI cache and software prefetching APIs to prepare for the
introduction of a general system model. Changes include:
- Marking existing interfaces const and/or override as appropriate
- Adding comments
- Adding BasicTTIImpl interfaces that delegate to a subtarget
implementation
- Adding a default "no information" subtarget implementation
Only a handful of targets use these interfaces currently: AArch64,
Hexagon, PPC and SystemZ. AArch64 already has a custom subtarget
implementation, so its custom TTI implementation is migrated to use
the new facilities in BasicTTIImpl to invoke its custom subtarget
implementation. The custom TTI implementations continue to exist for
the other targets with this change. They are not moved over to
subtarget-based implementations.
The end goal is to have the default subtarget implementation defer to
the system model defined by the target. With this change, the default
subtarget implementation essentially returns "no information" for
these interfaces. None of the existing users of TTI will hit that
implementation because they define their own custom TTI
implementations and won't use the BasicTTIImpl implementations.
Once system models are in place for the targets that use these
interfaces, their custom TTI implementations can be removed.
Differential Revision: https://reviews.llvm.org/D63614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365676
91177308-0d34-0410-b5e6-
96231b3b80d8
Don Hinton [Wed, 10 Jul 2019 17:57:05 +0000 (17:57 +0000)]
Recommit "[CommandLine] Remove OptionCategory and SubCommand caches from the Option class."
Previously reverted in 364141 due to buildbot breakage, and fixed here
by making GeneralCategory global a ManagedStatic.
Summary:
This change processes `OptionCategory`s and `SubCommand`s as they
are seen instead of caching them in the Option class and processing
them later. Doing so simplifies the work needed to be done by the Global
parser and significantly reduces the size of the Option class to a mere 64
bytes.
Removing the `OptionCategory` cache saved 24 bytes, and removing
the `SubCommand` cache saved an additional 48 bytes, for a total of a
72 byte reduction.
Reviewed By: serge-sans-paille
Tags: #llvm, #clang
Differential Revision: https://reviews.llvm.org/D62105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365675
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 17:49:27 +0000 (17:49 +0000)]
[X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.
Determine the element/load size calculations earlier and assert that they are whole bytes in size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365674
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Wed, 10 Jul 2019 17:36:56 +0000 (17:36 +0000)]
[LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.
Summary:
The map kept in loop rotate is used for instruction remapping, in order
to simplify the clones of instructions. Thus, if an instruction can be
simplified, its simplified value is placed in the map, even when the
clone is added to the IR. MemorySSA in contrast needs to know about that
clone, so it can add an access for it.
To resolve this: keep a different map for MemorySSA.
Reviewers: george.burgess.iv
Subscribers: jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365672
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 10 Jul 2019 17:24:24 +0000 (17:24 +0000)]
[ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.
LLJITBuilder now has a setCompileFunctionCreator method which can be used to
construct a CompileFunction for the LLJIT instance being created. The motivating
use-case for this is supporting ObjectCaches, which can now be set up at
compile-function construction time. To demonstrate this an example project,
LLJITWithObjectCache, is included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365671
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 17:22:31 +0000 (17:22 +0000)]
[X86] Regenerate tests. NFCI.
Hasn't been regenerated since the update script could merge 32/64-bit checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365670
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 10 Jul 2019 17:11:18 +0000 (17:11 +0000)]
[X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365667
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Desaulniers [Wed, 10 Jul 2019 17:08:25 +0000 (17:08 +0000)]
[TargetLowering] support BlockAddress as "i" inline asm constraint
Summary:
This allows passing address of labels to inline assembly "i" input
constraints.
Fixes pr/42502.
Reviewers: ostannard
Reviewed By: ostannard
Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365664
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 10 Jul 2019 16:54:13 +0000 (16:54 +0000)]
[NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365663
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Wed, 10 Jul 2019 16:36:46 +0000 (16:36 +0000)]
MC: AArch64: Add support for pg_hi21_nc relocation specifier.
Differential Revision: https://reviews.llvm.org/D64455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365661
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Wed, 10 Jul 2019 16:32:20 +0000 (16:32 +0000)]
[CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)
An alloca which can be sunk into the extraction region may have more
than one bitcast use. Move these uses along with the alloca to prevent
use-before-def.
Testing: check-llvm, stage2 build of clang
Fixes llvm.org/PR42451.
Differential Revision: https://reviews.llvm.org/D64463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365660
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Wed, 10 Jul 2019 16:32:16 +0000 (16:32 +0000)]
[CodeExtractor] Simplify findAllocas, NFC
Split getLifetimeMarkers out into its own method and have it return a
struct.
Differential Revision: https://reviews.llvm.org/D64467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365659
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 10 Jul 2019 16:31:19 +0000 (16:31 +0000)]
GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365658
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 10 Jul 2019 16:31:15 +0000 (16:31 +0000)]
GlobalISel: Define the full family of FP min/max instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365657
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 16:22:31 +0000 (16:22 +0000)]
[X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.
We've already checked that each element is the correct contributory size for VT when we inspect the elements for Undef/Zero/Load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365656
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 16:14:26 +0000 (16:14 +0000)]
[X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same size. NFCI.
This renames the type so it doesn't sound like its based off the load size - as we're moving towards supporting combining loads of different sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365655
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 10 Jul 2019 16:09:26 +0000 (16:09 +0000)]
AMDGPU: Serialize mode from MachineFunctionInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365653
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 10 Jul 2019 16:07:35 +0000 (16:07 +0000)]
[PatternMatch] Generalize m_SpecificInt_ULT() to take ICmpInst::Predicate
As discussed in the original review, this may be useful,
so let's just do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365652
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 10 Jul 2019 15:46:36 +0000 (15:46 +0000)]
[Remarks] Add cl::Hidden to -remarks-yaml-string-table
It was showing up in a lot of unrelated tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365647
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Wed, 10 Jul 2019 15:39:37 +0000 (15:39 +0000)]
docs/GithubMove.rst: Remove obsolete information
Summary:
Remove references to the multirepo and update the document to
reflect the current state of the github repository.
Reviewers: mehdi_amini, jyknight
Subscribers: jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365645
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Preud'homme [Wed, 10 Jul 2019 15:31:19 +0000 (15:31 +0000)]
[FileCheck] Use bool operator to test Expected
Use bool() consistently to get boolean value of Error, Optional and
Expected types in EXPECT calls. While static_cast is used in all cases
but one, bool provides more clarity and makes more sense as a new
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365644
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Wed, 10 Jul 2019 15:08:06 +0000 (15:08 +0000)]
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365641
91177308-0d34-0410-b5e6-
96231b3b80d8
Jay Foad [Wed, 10 Jul 2019 14:53:47 +0000 (14:53 +0000)]
[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
Summary:
D59191 added support for these modifiers in the assembler and
disassembler. This patch just teaches instruction selection that it can
use them.
Reviewers: arsenm, tstellar
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365640
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Wed, 10 Jul 2019 14:43:27 +0000 (14:43 +0000)]
[InstCombine] pow(C,x) -> exp2(log2(C)*x)
Summary:
Transform
pow(C,x)
To
exp2(log2(C)*x)
if C > 0, C != inf, C != NaN (and C is not power of 2, since we have some fold for such case already).
log(C) is folded by the compiler and exp2 is much faster to compute than pow.
Reviewers: spatel, efriedma, evandro
Reviewed By: evandro
Subscribers: lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365637
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 10 Jul 2019 14:41:47 +0000 (14:41 +0000)]
[InferFunctionAttrs] add/adjust tests for dereferenceable; NFC
Based on review comments for D64258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365636
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 10 Jul 2019 14:05:13 +0000 (14:05 +0000)]
gn build: Merge r365585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365633
91177308-0d34-0410-b5e6-
96231b3b80d8
James Henderson [Wed, 10 Jul 2019 13:40:45 +0000 (13:40 +0000)]
[docs][llvm-symbolizer] Fix grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365630
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 13:28:13 +0000 (13:28 +0000)]
[X86] EltsFromConsecutiveLoads - cleanup Zero/Undef/Load element collection. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365628
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Wed, 10 Jul 2019 13:18:13 +0000 (13:18 +0000)]
[MIPS GlobalISel] Select float and double phi
Select float and double phi for MIPS32.
Differential Revision: https://reviews.llvm.org/D64420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365627
91177308-0d34-0410-b5e6-
96231b3b80d8
Petar Avramovic [Wed, 10 Jul 2019 12:55:21 +0000 (12:55 +0000)]
[MIPS GlobalISel] Select float and double load and store
Select float and double load and store for MIPS32.
Differential Revision: https://reviews.llvm.org/D64419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365626
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Preud'homme [Wed, 10 Jul 2019 12:49:28 +0000 (12:49 +0000)]
[FileCheck] Simplify numeric variable interface
Summary:
This patch simplifies 2 aspects in the FileCheckNumericVariable code.
First, setValue() method is turned into a void function since being
called only on undefined variable is an invariant and is now asserted
rather than returned. This remove the assert from the callers.
Second, clearValue() method is also turned into a void function since
the only caller does not check its return value since it may be trying
to clear the value of variable that is already cleared without this
being noteworthy.
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64231
llvm-svn: 365249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365625
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Preud'homme [Wed, 10 Jul 2019 12:49:17 +0000 (12:49 +0000)]
[FileCheck] Fix @LINE value after match failure
Summary:
The value of the FileCheckNumericVariable class instance representing
the @LINE numeric variable is set and cleared respectively before and
after substitutions are made, if any. However, when a substitution
fails, the value is not cleared. This causes the next substitution of
@LINE later on to give the wrong value since setValue is a nop if the
value is already set. This is what caused failures after commit r365249.
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365624
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Wed, 10 Jul 2019 12:29:43 +0000 (12:29 +0000)]
[NFC][ARM] Convert lambdas to static helpers
Break up and convert some of the lambdas in ARMLowOverheadLoops into
static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365623
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 12:22:59 +0000 (12:22 +0000)]
[X86] EltsFromConsecutiveLoads - LDBase is non-null. NFCI.
Don't bother checking for LDBase != null - it should be (and we assert that it is).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365622
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 12:21:35 +0000 (12:21 +0000)]
[DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.
Keep the uint64_t type from getZExtValue() to stop truncation/extension overflow warnings in MSVC in subvector index math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365621
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 11:26:57 +0000 (11:26 +0000)]
[X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.
Cache the LoadSDNode nodes so we can easily map to/from the element index instead of packing them together - this will be useful for future patches for PR16739 etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365620
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikola Prica [Wed, 10 Jul 2019 11:17:48 +0000 (11:17 +0000)]
[ELF] Loose a condition for relocation with a symbol
Deleted code was introduced as a work around for a bug in the gold linker
(http://sourceware.org/PR16794). Test case that was given as a reason for
this part of code, the one on previous link, now works for the gold.
This condition is too strict and when a code is compiled with debug info
it forces generation of numerous relocations with symbol for architectures
that do not have relocation addend.
Reviewers: arsenm, espindola
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D64327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365618
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 10:46:36 +0000 (10:46 +0000)]
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support
This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it.
Another step towards partial vector loads......
Differential Revision: https://reviews.llvm.org/D64205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365614
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 10:45:09 +0000 (10:45 +0000)]
Fix const/non-const lambda return type warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365613
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 10 Jul 2019 10:34:44 +0000 (10:34 +0000)]
Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365612
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 10 Jul 2019 10:25:22 +0000 (10:25 +0000)]
[SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with one unique successor
Only instructions with two or more unique successors should be considered for unswitching.
Patch Author: Daniil Suchkov.
Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365611
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikhail Maltsev [Wed, 10 Jul 2019 08:59:17 +0000 (08:59 +0000)]
[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.
Patch by Momchil Velikov.
Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen
Reviewed By: dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365604
91177308-0d34-0410-b5e6-
96231b3b80d8
James Henderson [Wed, 10 Jul 2019 08:56:13 +0000 (08:56 +0000)]
[docs][llvm-dwarfdump] Normalise some wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365603
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Wed, 10 Jul 2019 08:40:11 +0000 (08:40 +0000)]
[test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries.
This converts 5 precompiled binaries to YAMLs,
removes 4 from inputs and performs a cleanup.
Differential revision: https://reviews.llvm.org/D64246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365601
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 10 Jul 2019 08:25:48 +0000 (08:25 +0000)]
[SimpleLoopUnswitch] Add a test case exposing a bug
This test exposes a bug in SimpleLoopUnswitch that leads to a crash on
assert(SuccessorsCount > 1 && "Cannot unswitch a condition without multiple distinct successors!");
when SimpleLoopUnswitch considers unswitching of a loop by a switch with one successor.
Fix will be submitted soon.
Patch Author: Daniil Suchkov.
Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365600
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Wed, 10 Jul 2019 06:18:03 +0000 (06:18 +0000)]
Silence gcc warning by adding parentheses to condition [NFC]
Without this gcc 7.4.0 complains with
../include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:457:54: error: suggest parentheses around '&&' within '||' [-Werror=parentheses]
isArtifactCast(TmpDef->getOpcode()) &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
"Expecting copy or artifact cast here");
~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365597
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristina Brooks [Wed, 10 Jul 2019 03:52:31 +0000 (03:52 +0000)]
Fix modular build issues caused by BitCodes.h
Consolidate llvm::BWH_* statics into an enum to fix
module build issues. This fixes the LLVM_Bitcode module,
getting rid of -Wmodules-ambiguous-internal-linkage.
Differential Revision: https://reviews.llvm.org/D64469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365594
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 10 Jul 2019 00:40:01 +0000 (00:40 +0000)]
[X86] Limit getTargetConstantFromNode to only work on NormalLoads not extending loads.
This seems to fix a failure reported by Jordan Rupprecht, but we
don't have a reduced test case yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365589
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 10 Jul 2019 00:34:13 +0000 (00:34 +0000)]
[Support] Move llvm::MemoryBuffer to sys::fs::file_t
Summary:
On Windows, Posix integer file descriptors are a compatibility layer
over native file handles provided by the C runtime. There is a hard
limit on the maximum number of file descriptors that a process can open,
and the limit is 8192. LLD typically doesn't run into this limit because
it opens input files, maps them into memory, and then immediately closes
the file descriptor. This prevents it from running out of FDs.
For various reasons, I'd like to open handles to every input file and
keep them open during linking. That requires migrating MemoryBuffer over
to taking open native file handles instead of integer FDs.
Reviewers: aganea, Bigcheese
Reviewed By: aganea
Subscribers: smeenai, silvas, mehdi_amini, hiraditya, steven_wu, dexonsmith, dang, llvm-commits, zturner
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365588
91177308-0d34-0410-b5e6-
96231b3b80d8
Tom Stellard [Wed, 10 Jul 2019 00:22:41 +0000 (00:22 +0000)]
AMDGPU/GlobalISel: Add support for wide loads >= 256-bits
Summary:
This adds support for the most commonly used wide load types:
<8xi32>, <16xi32>, <4xi64>, and <8xi64>
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57399
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365586
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 9 Jul 2019 23:34:29 +0000 (23:34 +0000)]
GlobalISel: Implement lower for G_FCOPYSIGN
In SelectionDAG AMDGPU treated these as legal, but this was mostly
because the bitcasts required for FP types were painful. Theoretically
the bitpattern should eventually match to bfi, so don't bother trying
to get the patterns to import.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365583
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:20:01 +0000 (23:20 +0000)]
[Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.h
This fixes a modules issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365580
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:16:59 +0000 (23:16 +0000)]
[docs][Remarks] Add documentation for remarks in LLVM
This adds documentation that describes remarks in LLVM.
It aims at explaining what remarks are, how to enable them, and what
users can do with the different modes.
It lists all the available flags in LLVM (excluding clang), and
describes the expected YAML structure as well as the tools that support
the YAML format today.
Differential Revision: https://reviews.llvm.org/D64355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365578
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 9 Jul 2019 23:05:54 +0000 (23:05 +0000)]
[X86] Don't form extloads in combineExtInVec unless the load extension is legal.
This should prevent doing this on pre-sse4.1 targets or for 256
bit vectors without avx2.
I don't know of a failure from this. Op legalization will probably
take care of, but seemed better to be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365577
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 9 Jul 2019 22:48:04 +0000 (22:48 +0000)]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365575
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Tue, 9 Jul 2019 22:42:24 +0000 (22:42 +0000)]
[AMDGPU] gfx908 v_pk_fmac_f16 support
Differential Revision: https://reviews.llvm.org/D64433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365573
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Tue, 9 Jul 2019 22:37:51 +0000 (22:37 +0000)]
gn build: Merge r365536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365572
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Tue, 9 Jul 2019 22:37:41 +0000 (22:37 +0000)]
gn build: Merge r365532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365571
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Tue, 9 Jul 2019 22:37:25 +0000 (22:37 +0000)]
gn build: Merge r365541.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365570
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Tue, 9 Jul 2019 22:37:09 +0000 (22:37 +0000)]
gn build: Merge r365531.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365569
91177308-0d34-0410-b5e6-
96231b3b80d8
Pavel Labath [Tue, 9 Jul 2019 22:36:43 +0000 (22:36 +0000)]
Add lldb type unit support to the release notes
Reviewers: JDevlieghere, teemperor
Subscribers: llvm-commits, lldb-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365568
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 9 Jul 2019 22:19:13 +0000 (22:19 +0000)]
GlobalISel: Combine unmerge of merge with intermediate cast
This eliminates some illegal intermediate vectors when operations are
scalarized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365566
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Tue, 9 Jul 2019 22:01:04 +0000 (22:01 +0000)]
[Profile] Support raw/indexed profiles larger than 4GB
rdar://
45955976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365565
91177308-0d34-0410-b5e6-
96231b3b80d8
Yuanfang Chen [Tue, 9 Jul 2019 21:53:33 +0000 (21:53 +0000)]
[llvm-objdump] Keep warning for --disassemble-functions in correct order.
relative to normal output when dumping archive files.
prepare for PR35351.
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Reviewed by: MaskRay, jhenderson
Differential Revision: https://reviews.llvm.org/D64165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365564
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Tue, 9 Jul 2019 21:43:09 +0000 (21:43 +0000)]
[AMDGPU] gfx908 mAI instructions, MC part
Differential Revision: https://reviews.llvm.org/D64446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365563
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikita Popov [Tue, 9 Jul 2019 20:24:44 +0000 (20:24 +0000)]
[SLP] Optimize getSpillCost(); NFCI
For a given set of live values, the spill cost will always be the
same for each call. Compute the cost once and multiply it by the
number of calls.
(I'm not sure this spill cost modeling makes sense if there are
multiple calls, as the spill cost will likely be shared across
calls in that case. But that's how it currently works.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365552
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Tue, 9 Jul 2019 20:22:36 +0000 (20:22 +0000)]
hwasan: Improve precision of checks using short granule tags.
A short granule is a granule of size between 1 and `TG-1` bytes. The size
of a short granule is stored at the location in shadow memory where the
granule's tag is normally stored, while the granule's actual tag is stored
in the last byte of the granule. This means that in order to verify that a
pointer tag matches a memory tag, HWASAN must check for two possibilities:
* the pointer tag is equal to the memory tag in shadow memory, or
* the shadow memory tag is actually a short granule size, the value being loaded
is in bounds of the granule and the pointer tag is equal to the last byte of
the granule.
Pointer tags between 1 to `TG-1` are possible and are as likely as any other
tag. This means that these tags in memory have two interpretations: the full
tag interpretation (where the pointer tag is between 1 and `TG-1` and the
last byte of the granule is ordinary data) and the short tag interpretation
(where the pointer tag is stored in the granule).
When HWASAN detects an error near a memory tag between 1 and `TG-1`, it
will show both the memory tag and the last byte of the granule. Currently,
it is up to the user to disambiguate the two possibilities.
Because this functionality obsoletes the right aligned heap feature of
the HWASAN memory allocator (and because we can no longer easily test
it), the feature is removed.
Also update the documentation to cover both short granule tags and
outlined checks.
Differential Revision: https://reviews.llvm.org/D63908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365551
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 9 Jul 2019 19:59:39 +0000 (19:59 +0000)]
[PoisonChecking] Flesh out complete todo list for full coverage
Note: I don't actually plan to implement all of the cases at the moment, I'm just documenting them for completeness. There's a couple of cases left which are practically useful for me in debugging loop transforms, and I'll probably stop there for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365550
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 9 Jul 2019 19:55:28 +0000 (19:55 +0000)]
[X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.
This patch merges the allowsMemoryAccess call into isLoadBitCastBeneficial to allow X86 to skip it.
Differential Revision: https://reviews.llvm.org/D64295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365549
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Tue, 9 Jul 2019 19:51:58 +0000 (19:51 +0000)]
Fix build error for VC STL, use llvm::make_unique
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365548
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Tue, 9 Jul 2019 19:41:51 +0000 (19:41 +0000)]
[AMDGPU] gfx908 register file changes
Differential Revision: https://reviews.llvm.org/D64438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365546
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 9 Jul 2019 19:26:12 +0000 (19:26 +0000)]
[PoisonCheker] Support for out of bounds operands on shifts + insert/extractelement
These are sources of poison which don't come from flags, but are clearly documented in the LangRef. Left off support for scalable vectors for the moment, but should be easy to add if anyone is interested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365543
91177308-0d34-0410-b5e6-
96231b3b80d8
Sean Fertile [Tue, 9 Jul 2019 19:21:01 +0000 (19:21 +0000)]
Boilerplate for producing XCOFF object files from the PowerPC backend.
Stubs out a number of the classes needed to produce a new object file format
(XCOFF) for the powerpc-aix target. For testing input is an empty module which
produces an object file with just a file header.
Differential Revision: https://reviews.llvm.org/D61694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365541
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 9 Jul 2019 19:19:17 +0000 (19:19 +0000)]
[X86] LowerToHorizontalOp - use count_if to count non-UNDEF ops. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365540
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 9 Jul 2019 18:56:41 +0000 (18:56 +0000)]
[PoisonChecking] Add validation rules for "exact" on sdiv/udiv
As directly stated in the LangRef, no ambiguity here...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365538
91177308-0d34-0410-b5e6-
96231b3b80d8
Bob Haarman [Tue, 9 Jul 2019 18:50:55 +0000 (18:50 +0000)]
[ThinLTO] only emit used or referenced CFI records to index
Summary: We emit CFI_FUNCTION_DEFS and CFI_FUNCTION_DECLS to
distributed ThinLTO indices to implement indirect function call
checking. This change causes us to only emit entries for functions
that are either defined or used by the module we're writing the index
for (instead of all functions in the combined index), which can make
the indices substantially smaller.
Fixes PR42378.
Reviewers: pcc, vitalybuka, eugenis
Subscribers: mehdi_amini, hiraditya, dexonsmith, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365537
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 9 Jul 2019 18:49:29 +0000 (18:49 +0000)]
Add a transform pass to make the executable semantics of poison explicit in the IR
Implements a transform pass which instruments IR such that poison semantics are made explicit. That is, it provides a (possibly partial) executable semantics for every instruction w.r.t. poison as specified in the LLVM LangRef. There are obvious parallels to the sanitizer tools, but this pass is focused purely on the semantics of LLVM IR, not any particular source language.
The target audience for this tool is developers working on or targetting LLVM from a frontend. The idea is to be able to take arbitrary IR (with the assumption of known inputs), and evaluate it concretely after having made poison semantics explicit to detect cases where either a) the original code executes UB, or b) a transform pass introduces UB which didn't exist in the original program.
At the moment, this is mostly the framework and still needs to be fleshed out. By reusing existing code we have decent coverage, but there's a lot of cases not yet handled. What's here is good enough to handle interesting cases though; for instance, one of the recent LFTR bugs involved UB being triggered by integer induction variables with nsw/nuw flags would be reported by the current code.
(See comment in PoisonChecking.cpp for full explanation and context)
Differential Revision: https://reviews.llvm.org/D64215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365536
91177308-0d34-0410-b5e6-
96231b3b80d8
Sean Fertile [Tue, 9 Jul 2019 18:44:28 +0000 (18:44 +0000)]
Try to appease the Windows build bots.
Several of the conditonal operators commited in llvm-svn: 365524 fail to compile
on the windows buildbots. Converting to an if and early return to try to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365535
91177308-0d34-0410-b5e6-
96231b3b80d8
Yonghong Song [Tue, 9 Jul 2019 18:35:46 +0000 (18:35 +0000)]
[BPF] Fix a typo in the file name
Fixed the file name from BPFAbstrctMemberAccess.cpp to
BPFAbstractMemberAccess.cpp.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365532
91177308-0d34-0410-b5e6-
96231b3b80d8