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Topi Pohjolainen [Thu, 25 Jun 2015 11:00:41 +0000 (14:00 +0300)]
i965: Stop aux data compare preventing program binary re-use
Items in the program cache consist of three things: key, the data
representing the instructions and auxiliary data representing
uniform storage. The data consisting of instructions is stored into
a drm buffer object while the key and the auxiliary data reside in
malloced section. Now the cache uploading is equipped with a check
that iterates over existing items and seeks to find a another item
using identical instruction data than the one being just uploaded.
If such is found there is no need to add another section into the
drm buffer object holding identical copy of the existing one. The
item just being uploaded should instead simply point to the same
offset in the underlying drm buffer object.
Unfortunately the check for the matching instruction data is
coupled with a check for matching auxiliary data also. This
effectively prevents the cache from ever containing two items
that could share a section in the drm buffer object.
The constraint for the instruction data and auxiliary data to
match is, fortunately, unnecessary strong. When items are stored
into the cache they will anyway contain their own copy of the
auxiliary data (even if they matched - which they in real world
never will). The only thing the items would be sharing is the
instruction data and hence we should only check for that to match
and nothing else.
No piglit regression in jenkins.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 25 Jun 2015 11:35:26 +0000 (14:35 +0300)]
i965: Only write program to cache when it doesn't exist yet
Current logic re-writes the same data when existing data is found.
Not that this actually matters at the moment in practice, the
contraint for finding matching data is too severe to ever allow
data to be shared between two items in the cache.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Topi Pohjolainen [Thu, 25 Jun 2015 11:31:03 +0000 (14:31 +0300)]
i965: Rename brw_upload_item_data to brw_alloc_item_data
and simplify the interface to take directly the size and to return
the offset. The routine does nothing more than allocate, it doesn't
upload anything.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Tapani Pälli [Wed, 12 Aug 2015 08:13:40 +0000 (11:13 +0300)]
mesa: update MaxShaderStorageBlockSize to 2^27
Extension spec originally required 2^24 but 2^27 is the minimum value
required by OpenGL 4.5 and OpenGL ES 3.1 specifications.
Fixes:
ES31-CTS.shader_storage_buffer_object.basic-max
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Tapani Pälli [Mon, 3 Aug 2015 07:46:33 +0000 (10:46 +0300)]
mesa: fix name returned for XFB varyings
_mesa_get_program_resource_name has logic to append '[0]' in name
if variable is an array, this should be skipped for XFB varyings
that have array index already appended.
v2: fix comment, change also GL_NAME_LENGTH query to match
the behaviour
Fixes:
ES31-CTS.program_interface_query.transform-feedback-types
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Edward O'Callaghan [Wed, 29 Jul 2015 11:49:45 +0000 (21:49 +1000)]
mesa: Fix printf format specifier warn of the ptrdiff_t
See §7.19.6.1, paragraph 7 of the ISO C specification.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Tue, 11 Aug 2015 19:37:59 +0000 (21:37 +0200)]
r600g: allow setting geometry shader sampler states
We were ignoring them. This is both hilarious and sad.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Tue, 11 Aug 2015 20:36:51 +0000 (22:36 +0200)]
r600g: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
(untested, ported from radeonsi)
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Marek Olšák [Tue, 11 Aug 2015 20:36:51 +0000 (22:36 +0200)]
radeonsi: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Fixes piglit: gl-1.4-polygon-offset (formerly a glean test)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Marek Olšák [Mon, 10 Aug 2015 00:28:01 +0000 (02:28 +0200)]
radeonsi: enable VS_OUT_MISC_SIDE_BUS_ENA
This is recommended for better performance.
Diag tests always enable this.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 9 Aug 2015 23:50:11 +0000 (01:50 +0200)]
radeonsi: add support for gl_PrimitiveID in the fragment shader
It must be obtained from the VS.
The GS scenario A must be enabled for PrimID to be generated for the VS.
+ 4 piglits
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 9 Aug 2015 22:52:21 +0000 (00:52 +0200)]
radeonsi: move VGT_GS_MODE to the VS state
The VS will want to select GS scenario A here (VS with PrimitiveID).
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Rob Clark [Wed, 12 Aug 2015 15:39:24 +0000 (11:39 -0400)]
freedreno/a4xx: format updates
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 20:47:16 +0000 (16:47 -0400)]
freedreno/a3xx+a4xx: add texture buffer object support
Basic texture buffer support. Should be straightforward to add first/
last_element support. And with a bit of work in ir3 emulate larger
texture buffer sizes. But this seems to be enough for stk gl31 render
paths.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 20:33:14 +0000 (16:33 -0400)]
ttn: add buffer texture type
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 20:11:04 +0000 (16:11 -0400)]
freedreno/ir3: 'keeps' need neighbors found too
This shows up with a glamor shader, which does a TXF and uses the result
for conditional kill. Before we wouldn't group the fanin (collect)
neighbors which need to be allocated adjacently at RA, resulting in
badness.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 20:09:48 +0000 (16:09 -0400)]
freedreno/ir3/print: print left/right neighbors too
When debugging compiler, this is useful to see.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 15:47:46 +0000 (11:47 -0400)]
freedreno/ir3: use nir pass to lower const to scalar
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 12:48:34 +0000 (08:48 -0400)]
freedreno/a4xx: point-size and spritelist fixes
a4xx needs similar treatment as
995f55a6
Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp()
hack previously needed for mem2gmem.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 11 Aug 2015 00:41:45 +0000 (20:41 -0400)]
freedreno: cap cleanups
Move a few things around to group stuff that is common to a3xx/a4xx
together. Also, introduce is_ir3() for things that are more specific to
the compiler / shader-ISA than to the gpu generation.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 10 Aug 2015 10:58:37 +0000 (06:58 -0400)]
mesa: add NV_read_{depth,stencil,depth_stencil} extensions
These extensions allow reading depth/stencil for GLES contexts, which is
useful for tools like apitrace.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Thu, 6 Aug 2015 21:26:47 +0000 (14:26 -0700)]
i965/shader: Don't use OptimizeForAOS for NIR vec4 vertex shaders
Shader-db results for vec4 programs using NIR on HSW:
total instructions in shared programs:
1838157 ->
1828469 (-0.53%)
instructions in affected programs: 275978 -> 266290 (-3.51%)
helped: 2827
HURT: 244
GAINED: 0
LOST: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Nanley Chery [Fri, 7 Aug 2015 23:37:47 +0000 (16:37 -0700)]
mesa/teximage: report the correct function which triggered the error
This function would always report that a dimension or size error occurred
in glTexImage even when it was called from glCompressedTexImage. Replace
the static string with the dynamically determined caller name.
Reviewed-by: Tapani Palli <tapani.palli@intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Oded Gabbay [Wed, 12 Aug 2015 15:22:53 +0000 (18:22 +0300)]
mesa/formats: don't byteswap when building array formats
Because we build here an array format, we don't need to swap the
bytes for big endian.
If it isn't an array format, the bytes will be swapped in
_mesa_format_convert.
v2: remove temp variable
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 10 Aug 2015 08:32:23 +0000 (01:32 -0700)]
mesa/formats: Don't flip channels of null array formats
Before, if we encountered an array format of 0 on a BE system, we would
flip all the channels even though it's an invalid format. This would
result in a mostly invalid format with a swizzle of yyyy or wwww. Instead,
we should just return 0 if the array format stashed in the format info is
invalid.
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 10 Aug 2015 06:45:44 +0000 (23:45 -0700)]
mesa/formats: Fix swizzle flipping for big-endian targets
The swizzle defines where in the format you should look for any given
channel. When we flip the format around for BE targets, we need to change
the destinations of the swizzles, not the sources. For example, say the
format is an RGBX format with a swizzle of xyz1 on LE. Then it should be
wzy1 on BE; however, the code as it was before, would have made it 1zyx on
BE which is clearly wrong.
Reviewed-by: Iago Toral <itoral@igalia.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Sat, 8 Aug 2015 16:00:21 +0000 (09:00 -0700)]
mesa/formats: Only do byteswapping for packed formats
Reviewed-by: Iago Toral <itoral@igalia.com>
Cc: "10.6 10.5" <mesa-stable@lists.freedesktop.org>
Matt Turner [Tue, 11 Aug 2015 22:21:03 +0000 (15:21 -0700)]
configure.ac: Always define __STDC_LIMIT_MACROS.
... which ensures that we get defines like LONG_MAX in C++.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Tue, 11 Aug 2015 01:50:48 +0000 (18:50 -0700)]
i965: Optimize brw_inst_set_bits() and brw_compact_inst_set_bits().
Cuts about 2k of .text.
text data bss dec hex filename
5017141 197160 27672
5241973 4ffc75 i965_dri.so before
5014981 197160 27672
5239813 4ff405 i965_dri.so after
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 10 Aug 2015 23:57:58 +0000 (16:57 -0700)]
i965: Optimize brw_inst_bits() and brw_compact_inst_bits().
Cuts about 1k of .text.
text data bss dec hex filename
5018165 197160 27672
5242997 500075 i965_dri.so before
5017141 197160 27672
5241973 4ffc75 i965_dri.so after
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Emil Velikov [Tue, 11 Aug 2015 18:00:03 +0000 (19:00 +0100)]
docs: add news item and link release notes for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Tue, 11 Aug 2015 17:54:18 +0000 (18:54 +0100)]
docs: add sha256 checksums for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
99793e2541510fe208d29e69fedf97a6fff006f8)
Emil Velikov [Tue, 11 Aug 2015 15:39:10 +0000 (16:39 +0100)]
docs: add release notes for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
6b2fcee64edadbd4db2293f5f4fc1a70e80c7251)
Marek Olšák [Sat, 8 Aug 2015 12:03:54 +0000 (14:03 +0200)]
gallium/radeon: fix r600g build if LLVM is disabled
MESA_LLVM_VERSION_PATCH is undefined.
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Tested-by: Benjamin Bellec <b.bellec@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Grazvydas Ignotas [Sun, 9 Aug 2015 21:42:35 +0000 (00:42 +0300)]
r600g: use a bitfield to track dirty atoms
r600 currently has 73 atoms and looping through their dirty flags has
become costly because checking each flag requires a pointer
dereference before the read. To avoid having to do that add additional
bitfield which can be checked really quickly thanks to tzcnt instruction.
id field was added to struct r600_atom but that doesn't affect memory
usage for both 32 and 64 bit CPUs because it was stuffed into padding.
The performance improvement is ~2% for benchmarks that can have FPS in
the thousands but is hardly measurable in "real" programs.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Sun, 9 Aug 2015 21:42:34 +0000 (00:42 +0300)]
r600g: don't mark unused atom dirty
On evergreen config_state is not used, so don't mark it dirty.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Sun, 9 Aug 2015 21:42:33 +0000 (00:42 +0300)]
r600g: use a helper to add an initialized atom
Instead of writing to rctx->atoms directly use a helper to take
advantage of assert checks.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Sun, 9 Aug 2015 21:42:32 +0000 (00:42 +0300)]
gallium/radeon: use helper functions to mark atoms dirty
This is analogous to r300_mark_atom_dirty() used by r300, and will
be used by later patches. For common radeon code, appropriate helper
is called through a function pointer.
No functional changes.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Francisco Jerez [Fri, 1 May 2015 14:00:02 +0000 (17:00 +0300)]
docs: Mark ARB_shader_image_load_store as done on i965.
Francisco Jerez [Thu, 7 May 2015 15:56:01 +0000 (18:56 +0300)]
i965: Expose ARB_shader_image_load_store.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Mon, 27 Jul 2015 11:33:06 +0000 (14:33 +0300)]
i965/fs: Clamp image array indices to the array bounds on IVB.
This fixes the spec@arb_shader_image_load_store@invalid index bounds
piglit tests on IVB, which were causing a GPU hang and then a crash
due to the invalid binding table index result of the array index
calculation. Other generations seem to behave sensibly when an
invalid surface is provided so it doesn't look like we need to care.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Francisco Jerez [Mon, 27 Jul 2015 13:26:52 +0000 (16:26 +0300)]
i965/fs: Translate image load, store and atomic NIR intrinsics.
v2: Move array coordinate workaround into the surface builder.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Sun, 28 Jun 2015 18:16:31 +0000 (21:16 +0300)]
i965/fs: Handle image uniforms in NIR programs.
v2: Move the image_params array back to brw_stage_prog_data.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Tue, 5 May 2015 18:07:15 +0000 (21:07 +0300)]
i965: Implement logic to set up and upload an image uniform.
v2: Move the image_params array back to brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Francisco Jerez [Tue, 5 May 2015 18:05:45 +0000 (21:05 +0300)]
i965: Teach type_size() about the size of an image uniform.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Francisco Jerez [Thu, 30 Jul 2015 12:46:40 +0000 (15:46 +0300)]
i965/fs: Implement image load, store and atomic.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Move array coordinate workaround into the surface builder.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Thu, 30 Jul 2015 12:51:58 +0000 (15:51 +0300)]
i965/fs: Import image format conversion primitives.
Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determining the bitfield position of each
component. Most of the remaining functions perform integer, fixed
point normalized, and floating point type conversions, mapping between
a target type with per-component bit widths given by a parameter and a
matching native representation of the same type.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Fix clamping of negative floats in the unsigned case of
emit_convert_to_scaled().
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Wed, 22 Apr 2015 13:45:28 +0000 (16:45 +0300)]
i965/fs: Import image format metadata queries.
Define some utility functions to query the bitfield layout of a given
image format and whether it satisfies a number of more or less
hardware-specific properties.
v2: Drop VEC4 suport.
v3: Add SKL support.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Thu, 23 Jul 2015 16:32:08 +0000 (19:32 +0300)]
i965/fs: Import code to transform image coordinates into surface coordinates.
Accounting for the padding required for 1D arrays in certain cases.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Wed, 22 Apr 2015 13:44:18 +0000 (16:44 +0300)]
i965/fs: Import image memory offset calculation code.
Define a function to calculate the memory address of the image
location given by a vector of coordinates. This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and swizzling. They are still useful
because typed surface reads don't support any 64 or 128-bit formats on
IVB, and they don't support any 128-bit formats on HSW and BDW.
The tiling algorithm is implemented based on a number of parameters
which are passed in as uniforms and determine whether the surface
layout is X-tiled, Y-tiled or untiled. This allows binding surfaces
of different tiling layouts to the pipeline without recompiling the
program.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Add plenty of comments (Jason).
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Wed, 22 Apr 2015 13:43:51 +0000 (16:43 +0300)]
i965/fs: Import image access validity checks.
These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results. Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB and untyped messages elsewhere) we need to
implement it in software to work around lacking hardware support.
v2: Drop VEC4 suport.
v3: Rebase.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Sat, 23 Nov 2013 00:00:33 +0000 (16:00 -0800)]
i965: Define implementation constants for ARB_shader_image_load_store.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
v2: Drop VS support pre-Gen8, drop GS support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 9 Feb 2015 19:04:53 +0000 (21:04 +0200)]
i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.
v2: Store early fragment test mode in brw_wm_prog_data instead of
getting it from core mesa data structures (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 13 Jul 2015 11:21:07 +0000 (14:21 +0300)]
i965/gen7-8: Poke the 3DSTATE UAV access enable bits.
v2: Set the PS UAV-only bit on HSW (Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Tue, 3 Feb 2015 15:14:10 +0000 (17:14 +0200)]
i965/gen7: Enable fragment shader dispatch if the program has image uniforms.
Shaders with image uniforms may have side effects. Make sure that
fragment shader threads are dispatched if the shader has any image
uniforms.
v2: Use brw_stage_prog_data::nr_image_params to find out if the shader
has image uniforms instead of checking core mesa data structures
(Ken).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 20 Jul 2015 14:13:17 +0000 (17:13 +0300)]
i965: Hook up image state upload.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Mon, 13 Jul 2015 14:19:29 +0000 (17:19 +0300)]
i965: Reserve enough parameter entries for all image uniforms used in the program.
v2: Add CS support.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Wed, 21 Jan 2015 15:34:49 +0000 (17:34 +0200)]
i965: Define and initialize image parameter structure.
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too. surface_idx
is always used.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
v3: Improve documentation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Sat, 2 May 2015 13:58:24 +0000 (16:58 +0300)]
i965: Implement surface state set-up for shader images.
v2: Add SKL support.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Francisco Jerez [Tue, 12 May 2015 12:56:54 +0000 (15:56 +0300)]
i965: Fix brw_memory_barrier() for SKL.
This works as-is on SKL, only the assertion needs to be relaxed.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Tue, 12 May 2015 13:10:07 +0000 (16:10 +0300)]
i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Timothy Arceri [Sun, 9 Aug 2015 04:44:30 +0000 (14:44 +1000)]
glsl: Add missing spec quote about atomic counter in structs
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Alex Deucher [Mon, 10 Aug 2015 19:35:21 +0000 (15:35 -0400)]
radeonsi: add new OLAND pci id
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Mon, 10 Aug 2015 21:41:36 +0000 (17:41 -0400)]
nouveau: no need to do tnl wakeup, state updates are always hooked up
A TNL state update now requires a DrawBuffer to be set, which it isn't
early on in context creation. Since we init swtnl from context init,
this caused crashes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 10 Aug 2015 18:52:50 +0000 (11:52 -0700)]
i965/fs: Make resolve_source_modifiers consistent with the vec4 version
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 10 Aug 2015 18:48:14 +0000 (11:48 -0700)]
i965/vec4_visitor: Make some function arguments const references
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 31 Jul 2015 15:36:35 +0000 (08:36 -0700)]
i965/fs: Don't do redundant RA setup on IVB+
Acked-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 31 Jul 2015 15:35:57 +0000 (08:35 -0700)]
i965/fs: Use dispatch_width instead of reg_width in alloc_reg_sets
reg_width is kind of an outdated concept.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 31 Jul 2015 03:53:04 +0000 (20:53 -0700)]
ra: Delete the conflict lists in ra_set_finalize
They are never used after the set is finalized so there's no reason to keep
them around.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 31 Jul 2015 03:49:22 +0000 (20:49 -0700)]
ra: Refactor ra_set_finalize
All this commit does is change an early return to an if with an else
clause.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 3 Aug 2015 22:21:59 +0000 (15:21 -0700)]
i965/vec4_nir: Properly handle integer multiplies on BDW+
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 3 Aug 2015 21:37:41 +0000 (14:37 -0700)]
i965/vec4_nir: Do boolean source modifier resolves on BDW+
On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
a boolean negate and not an integer negate. However, NIR's soruce
modifiers are the integer version. We have to resolve it with a MOV prior
to emitting the actual instruction. This is basically the same thing we do
in the FS backend.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 3 Aug 2015 17:00:38 +0000 (10:00 -0700)]
i965/vec4-nir: Handle boolean resolvese on ILK-
The analysis code was already there and running, we just weren't doing
anything with the result of it yet.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 3 Aug 2015 23:25:18 +0000 (16:25 -0700)]
i965/nir: Don't mark bany or ball instructions for resolve
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 3 Aug 2015 21:12:35 +0000 (14:12 -0700)]
i965/nir: Use nir_op_info.output_type for determining when to resolve
Previously, we were explicitly listing every instruction that needs a
resolve. However, those instructions were precicely the ones that returned
booleans so there's no reason why we shouldn't just have that check. Also,
all of the reduction opcodes such as bany and ball were missing so it
didn't properly flag stuff on vec4. If an opcode gets added in the future
that returns a bool but doesn't need a resolve, we can special-case that.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Mon, 10 Aug 2015 05:03:00 +0000 (22:03 -0700)]
mesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unorm
This better ensures that the src_bits == dst_bits case gets optimized away.
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sun, 2 Aug 2015 14:22:43 +0000 (16:22 +0200)]
gallium/radeon: add a debug flag not to use write combining (v2)
v2: just clear the flag before the allocation
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Rob Clark [Wed, 5 Aug 2015 22:14:49 +0000 (18:14 -0400)]
freedreno/a4xx: add s8/z32/z32_s8x24 support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 5 Aug 2015 18:21:06 +0000 (14:21 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 9 Aug 2015 13:03:25 +0000 (09:03 -0400)]
freedreno/a4xx: fix vpsrepl for blit shaders
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 10 Aug 2015 11:11:56 +0000 (07:11 -0400)]
freedreno/a4xx: clear cached fp when switching blit prog
For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore. But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 9 Aug 2015 12:38:25 +0000 (08:38 -0400)]
freedreno/a3xx: clear cached fp when switching blit prog
For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore. But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Marta Lofstedt [Mon, 10 Aug 2015 10:48:11 +0000 (13:48 +0300)]
mesa/es3.1: Allow Multisampled FrameBufferTextures
GLES 3.1 must be allowed to use multisampled framebuffer textures.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Marta Lofstedt [Mon, 15 Jun 2015 11:50:21 +0000 (13:50 +0200)]
mesa/es3.1: Pass sample count check for multisampled textures
v3 : Removed space in comment.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Oded Gabbay [Tue, 4 Aug 2015 18:39:32 +0000 (21:39 +0300)]
mesa: clear existing swizzle info before bitwise-OR
This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.
v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Jose Fonseca [Sun, 9 Aug 2015 21:36:37 +0000 (22:36 +0100)]
util: Use LONG_MAX instead of LONG_BIT.
More portable. Based on Roland Scheidegger's idea.
Tested with roundevent_test on Linux, MinGW, and MSVC.
https://bugs.freedesktop.org/show_bug.cgi?id=91591
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jose Fonseca [Sun, 9 Aug 2015 10:55:28 +0000 (11:55 +0100)]
scons: Build roundevent_test.
Reviewed-by: Roland Scheidegger <sroland@vmware.co>
Jose Fonseca [Sun, 9 Aug 2015 10:25:41 +0000 (11:25 +0100)]
util: Cope with LONG_BIT not being defined on Windows.
Neither MSVC nor MinGW defines LONG_BIT. For MSVC this was not a problem as
it doesn't define __x86_64__ macro (it's GCC specific.)
However on Windows long type is guaranteed to be 32bits.
Also add an #error, as GCC will just warn, not throw any error, when no
value is returned.
Trivial.
Jose Fonseca [Sun, 9 Aug 2015 10:21:03 +0000 (11:21 +0100)]
gallium: GCC 4.9 allows to include tmmintrin.h without -msse3.
Fixes build with MinGW x86_64 build with GCC 4.9, due to conflicting
definition _mm_shuffle_epi8 of u_sse.h and system headers.
Trivial.
Jose Fonseca [Fri, 7 Aug 2015 12:07:40 +0000 (13:07 +0100)]
util: Rename PURE to ATTRIBUTE_PURE.
To avoid collission with windows.h's PURE macro.
We could consider eventually renaming to __pure, but that would require
further care, so it's left to the future.
Reviewed-by: Brian Paul <brianp@vmware.com>
Boyan Ding [Sat, 8 Aug 2015 09:23:28 +0000 (17:23 +0800)]
egl/x11: Fix driver_name acquisition
We don't need to free driverName string from dri2 reply, on the other
hand, the driver name acquired from loader doesn't need duplication.
Fixes:
45e110bad9d (egl/x11: trust our loader over the xserver for the
drivername)
Reported-by: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: use brackets for both branches of conditional]
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Ben Widawsky [Fri, 7 Aug 2015 20:46:30 +0000 (13:46 -0700)]
i965/skl: (trivial) Remove invalid comment about thread counts
This should have been a part of:
commit
7eaacc1678195738fab3bb98870828611cae066d
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date: Wed Jul 29 12:35:24 2015 -0700
i965/skl: Add production thread counts and URB size
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Chris Wilson [Wed, 5 Aug 2015 12:58:46 +0000 (13:58 +0100)]
i965: Fix HW binding tables editing
Since the introduction of new gl_shader_stages in
commit
a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler <fabianbieler@fastmail.fm>
Date: Fri Mar 7 10:19:09 2014 +0100
mesa: add tessellation shader enums
the translation table for the stage into the HW binding table edit
command was broken, and so we used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Alexander von Gluck IV [Fri, 7 Aug 2015 17:55:40 +0000 (12:55 -0500)]
egl/dri2: Fix include path of u_atomic.h introduced
e7e29189
This was causing a failure to build on SCons due to a missing
-Isrc/egl. Instead of adding in that path, lets just -Isrc/
and include "utils/u_atomic.h".
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Fri, 7 Aug 2015 18:20:48 +0000 (19:20 +0100)]
egl/x11: don't crash if dri2_dpy->conn is NULL
Identical to commit
60e9c35b3a0(egl/x11: bail out if we cannot fetch
the xcb connection) but for the swrast codepath.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Wed, 29 Jul 2015 16:19:07 +0000 (17:19 +0100)]
egl/x11: auth with xserver before attempting to open the dri module
No real change, apart from keeping the calls to the underlying winsys
(x11) next to each other. Just like platform_wayland.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Emil Velikov [Wed, 29 Jul 2015 16:19:06 +0000 (17:19 +0100)]
egl/x11: trust our loader over the xserver for the drivername
This is a port of commit
7bd95ec437a(dri2: Trust our own driver name
lookup over the server's.) from glx/dri2.
v2: Add newline between code and multiline comment. (Matt)
Cc: Julien Isorce <julien.isorce@gmail.com>
Reported-by: Julien Isorce <julien.isorce@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Emil Velikov [Wed, 29 Jul 2015 16:19:05 +0000 (17:19 +0100)]
egl/x11: open the device from within dri2_x11_connect()
Allows us, with the next commit, to use alternative driver_name rather
than the one from xserver.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Emil Velikov [Wed, 29 Jul 2015 16:19:04 +0000 (17:19 +0100)]
egl/x11: fetch the device_name prior to driver_name
With the follow up commits we're about to further reshuffle things. Thus
we'll honour our our driver_name lookup (src/loader), and use the one
provided by xserver as a fall-back.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Emil Velikov [Wed, 29 Jul 2015 16:19:03 +0000 (17:19 +0100)]
egl/x11: remove dri2_dpy->conn checks
If the connection is NULL we won't be able to get here.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>