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David L. Jones [Mon, 13 May 2019 04:07:54 +0000 (04:07 +0000)]
gn build: support host build on ppc64 (a.k.a. powerpc64le)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360553
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Craig Topper [Mon, 13 May 2019 04:03:35 +0000 (04:03 +0000)]
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"
I've included a new fix in X86RegisterInfo to prevent PR41619 without
reintroducing r359392. We might be able to improve that in the base class
implementation of shouldRewriteCopySrc somehow. But this hopefully enables
forward progress on SimplifyDemandedBits improvements for now.
Original commit message:
This patch adds support for BigBitWidth -> SmallBitWidth bitcasts, splitting the DemandedBits/Elts accordingly.
The AMDGPU backend needed an extra (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1) combine to encourage BFE creation, I investigated putting this in DAGComb
but it caused a lot of noise on other targets - some improvements, some regressions.
The X86 changes are all definite wins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360552
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David L. Jones [Mon, 13 May 2019 03:43:25 +0000 (03:43 +0000)]
gn build: merge r360550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360551
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David L. Jones [Mon, 13 May 2019 03:32:41 +0000 (03:32 +0000)]
[WebAssembly] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360550
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Nico Weber [Sun, 12 May 2019 23:47:03 +0000 (23:47 +0000)]
gn build: Merge r360540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360549
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Lang Hames [Sun, 12 May 2019 22:26:33 +0000 (22:26 +0000)]
[JITLink] Add a test for zero-filled content.
Also updates RuntimeDyldChecker and llvm-rtdyld to support zero-fill tests by
returning a content address of zero (but no error) for zero-fill atoms, and
treating loads from zero as returning zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360547
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Lang Hames [Sun, 12 May 2019 22:26:32 +0000 (22:26 +0000)]
[ORC] Fix some typos.
Patch by Praveen Velliengiri. Thanks Praveen!
https://reviews.llvm.org/D61793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360546
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Simon Pilgrim [Sun, 12 May 2019 15:16:29 +0000 (15:16 +0000)]
[X86][AVX] Split VZEXT_MOVL ymm/zmm if the upper elements are not demanded.
Removes unnecessary vzeroupper noted in D61806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360543
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Sanjay Patel [Sun, 12 May 2019 14:53:59 +0000 (14:53 +0000)]
[LoopVectorizer] add tests for FP minmax; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360542
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Sanjay Patel [Sun, 12 May 2019 14:43:20 +0000 (14:43 +0000)]
[DAGCombiner] try to move bitcast after extract_subvector
I noticed that we were failing to narrow an x86 ymm math op in a case similar
to the 'madd' test diff. That is because a bitcast is sitting between the math
and the extract subvector and thwarting our pattern matching for narrowing:
t56: v8i32 = add t59, t58
t68: v4i64 = bitcast t56
t73: v2i64 = extract_subvector t68, Constant:i64<2>
t96: v4i32 = bitcast t73
There are a few wins and neutral diffs in the other tests.
Differential Revision: https://reviews.llvm.org/D61806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360541
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Fangrui Song [Sun, 12 May 2019 04:55:09 +0000 (04:55 +0000)]
[utils] update_test_checks.py: allow opt-8, opt-9
Allow using Debian's opt-8, opt-9 with update_test_checks.py
Patch by Shawn Landden!
Differential Revision: https://reviews.llvm.org/D61148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360536
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Simon Pilgrim [Sat, 11 May 2019 21:35:50 +0000 (21:35 +0000)]
[X86][SSE] SimplifyDemandedBits - call PEXTRB/PEXTRW SimplifyDemandedVectorElts as well.
See if we can simplify the demanded vector elts from the extraction before trying to simplify the demanded bits.
This helps us with target shuffles and hops in particular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360535
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Simon Pilgrim [Sat, 11 May 2019 20:56:05 +0000 (20:56 +0000)]
[DAG] Add SimplifyDemandedBits support for BITREVERSE
Pulled out of D58017 while I continue to investigate the BSWAP regression on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360534
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Simon Pilgrim [Sat, 11 May 2019 20:28:20 +0000 (20:28 +0000)]
[X86] Updated shift-mask test targets for D61830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360533
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Don Hinton [Sat, 11 May 2019 20:27:01 +0000 (20:27 +0000)]
[CommandLine] Add long option flag for cl::ParseCommandLineOptions . Part 5 of 5
Summary:
If passed, the long option flag makes the CommandLine parser
mimic the behavior or GNU getopt_long. Short options are a single
character prefixed by a single dash, and long options are multiple
characters prefixed by a double dash.
This patch was motivated by the discussion in the following thread:
http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html
Reviewed By: MaskRay
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360532
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Simon Pilgrim [Sat, 11 May 2019 19:16:46 +0000 (19:16 +0000)]
[X86] Add scalar shl+lshr -> shift+mask tests (PR40758)
As discussed on D61068, many x86 targets can perform 2 immediate shifts quicker than a shift + mask
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360530
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Simon Pilgrim [Sat, 11 May 2019 19:14:19 +0000 (19:14 +0000)]
[X86] Add avx512f tests for boolean reduction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360529
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Simon Pilgrim [Sat, 11 May 2019 17:12:52 +0000 (17:12 +0000)]
[CostModel][X86] Add min/max reduction costs for all SSE targets
The original costs stopped at SSE42, I've added conservative estimates for everything down to SSE1/SSE2 and moved some of the SSE42 costs to SSE41 (really only the addition of PCMPGT makes any difference).
I've also added missing vXi8 costs (we use PHMINPOSUW for i8/i16 for scarily quick results) and 256-bit vector costs for AVX1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360528
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Puyan Lotfi [Sat, 11 May 2019 17:03:36 +0000 (17:03 +0000)]
[NFC] yaml2obj/yam2elf.cpp whitespace changes: dos2unix removed CRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360527
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Simon Pilgrim [Sat, 11 May 2019 16:07:12 +0000 (16:07 +0000)]
[X86][SSE] Add SimplifyDemandedVectorElts HADD/HSUB handling.
Still missing PHADDW/PHSUBW tests because PEXTRW doesn't call SimplifyDemandedVectorElts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360526
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Simon Pilgrim [Sat, 11 May 2019 16:02:34 +0000 (16:02 +0000)]
FixupLEAPass::fixupIncDec - non-LEA opcodes should not happen here. NFCI.
Matches what we do in other functions and fixes scan-build warning about uninitialized NewOpcode variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360525
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Craig Topper [Sat, 11 May 2019 16:00:28 +0000 (16:00 +0000)]
[X86] Add CMOV_FR32X/CMOV_FR64X pseudo instructions. Use them in fast isel to fix a machine verifier error after adding test cases.
Fast isel picks the FR32X/FR64X register classes when lowering pseudo select, but it didn't have the right opcode to go with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360524
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Craig Topper [Sat, 11 May 2019 16:00:19 +0000 (16:00 +0000)]
[X86] Sink some fast isel code into the only if that uses it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360523
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Craig Topper [Sat, 11 May 2019 16:00:13 +0000 (16:00 +0000)]
[X86] Use TLI.getRegClassFor to simplify some more fast isel code. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360522
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Simon Pilgrim [Sat, 11 May 2019 15:51:14 +0000 (15:51 +0000)]
[MC][X86] Add test cases from PR14056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360521
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Simon Pilgrim [Sat, 11 May 2019 15:24:34 +0000 (15:24 +0000)]
HexagonConstEvaluator::evaluateHexExt - check incoming opcodes. NFCI.
Only certain extension opcodes are supported - fixes scan build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360520
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Simon Pilgrim [Sat, 11 May 2019 14:47:54 +0000 (14:47 +0000)]
[X86][SSE] Tweaked HADD/HSUB SimplifyDemandedVectorElts
Try to ensure we LHS and RHS test coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360519
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Simon Pilgrim [Sat, 11 May 2019 14:08:34 +0000 (14:08 +0000)]
[X86][SSE] Add integer HADD/HSUB SimplifyDemandedVectorElts tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360518
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Simon Pilgrim [Sat, 11 May 2019 12:46:38 +0000 (12:46 +0000)]
[X86][SSE] Add HADD/HSUB SimplifyDemandedVectorElts tests
Shows missed opportunities to simplify args.
Will add integer HADD/HSUB tests in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360517
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Simon Pilgrim [Sat, 11 May 2019 11:08:24 +0000 (11:08 +0000)]
Fix uninitialized variable analyzer warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360516
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Simon Pilgrim [Sat, 11 May 2019 11:00:37 +0000 (11:00 +0000)]
SelectionDAGISel::CodeGenAndEmitDAG - remove unused variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360514
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Craig Topper [Sat, 11 May 2019 05:18:58 +0000 (05:18 +0000)]
[X86] Use getRegClassFor to simplify some code in fast isel. NFCI
No need to select the register class based on type and features. It should
already be setup by X86ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360513
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Craig Topper [Sat, 11 May 2019 04:19:33 +0000 (04:19 +0000)]
[X86] Don't emit MOVNTDQA loads from fast-isel without SSE4.1.
We were checking for SSE4.1 for FP types, but not integer 128-bit types.
Fixes PR41837.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360512
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Craig Topper [Sat, 11 May 2019 04:00:27 +0000 (04:00 +0000)]
[X86] Add a test case for idempotent atomic operations with speculative load hardening. Fix an additional issue found by the test.
This test covers the fix from r360475 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360511
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Richard Trieu [Sat, 11 May 2019 03:36:16 +0000 (03:36 +0000)]
[SystemZ] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360510
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David L. Jones [Sat, 11 May 2019 03:23:37 +0000 (03:23 +0000)]
gn build: sort tablegen rules for X86 and AArch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360508
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David L. Jones [Sat, 11 May 2019 03:20:09 +0000 (03:20 +0000)]
gn build: merge r360494 and r360502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360507
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Richard Trieu [Sat, 11 May 2019 02:59:02 +0000 (02:59 +0000)]
[Sparc] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360506
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Richard Trieu [Sat, 11 May 2019 02:43:58 +0000 (02:43 +0000)]
[RISCV] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360505
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Richard Trieu [Sat, 11 May 2019 02:33:18 +0000 (02:33 +0000)]
[PowerPC] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360502
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Richard Trieu [Sat, 11 May 2019 02:09:13 +0000 (02:09 +0000)]
[NVPTX] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360500
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Richard Trieu [Sat, 11 May 2019 01:58:52 +0000 (01:58 +0000)]
[MSP430] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360498
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Richard Trieu [Sat, 11 May 2019 01:38:56 +0000 (01:38 +0000)]
[Mips] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360497
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Richard Trieu [Sat, 11 May 2019 01:25:58 +0000 (01:25 +0000)]
[Lanai] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360496
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Richard Trieu [Sat, 11 May 2019 01:13:21 +0000 (01:13 +0000)]
[BPF] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360494
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Richard Trieu [Sat, 11 May 2019 01:03:03 +0000 (01:03 +0000)]
[AVR] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360493
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David L. Jones [Sat, 11 May 2019 00:44:30 +0000 (00:44 +0000)]
gn build: merge r360490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360492
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David L. Jones [Sat, 11 May 2019 00:35:53 +0000 (00:35 +0000)]
gn build: merge r360484 and r360486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360491
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Richard Trieu [Sat, 11 May 2019 00:34:07 +0000 (00:34 +0000)]
[ARM] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360490
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David L. Jones [Sat, 11 May 2019 00:20:18 +0000 (00:20 +0000)]
gn build: merge r360345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360489
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Richard Trieu [Sat, 11 May 2019 00:13:01 +0000 (00:13 +0000)]
[ARC] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360488
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Richard Trieu [Sat, 11 May 2019 00:03:35 +0000 (00:03 +0000)]
[AMDGPU] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360487
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Richard Trieu [Fri, 10 May 2019 23:50:01 +0000 (23:50 +0000)]
[AArch64] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360486
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Richard Trieu [Fri, 10 May 2019 23:36:49 +0000 (23:36 +0000)]
[XCore] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360485
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Richard Trieu [Fri, 10 May 2019 23:24:38 +0000 (23:24 +0000)]
[X86] Move InstPrinter files to MCTargetDesc. NFC
For some targets, there is a circular dependency between InstPrinter and
MCTargetDesc. Merging them together will fix this. For the other targets,
the merging is to maintain consistency so all targets will have the same
structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360484
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Jordan Rupprecht [Fri, 10 May 2019 23:20:02 +0000 (23:20 +0000)]
Revert [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor
This reverts r360171 (git commit
a9d6c32eafc645c55b07eb50698c428e14c0bffd). A repro showing the asan/msan failures is forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360481
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Philip Reames [Fri, 10 May 2019 22:55:42 +0000 (22:55 +0000)]
Factor out redzone ABI checks [NFCI]
As requested in D58632, cleanup our red zone detection logic in the X86 backend. The existing X86MachineFunctionInfo flag is used to track whether we *use* the redzone (via a particularly optimization?), but there's no common way to check whether the function *has* a red zone.
I'd appreciate careful review of the uses being updated. I think they are NFC, but a careful eye from someone else would be appreciated.
Differential Revision: https://reviews.llvm.org/D61799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360479
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Lang Hames [Fri, 10 May 2019 22:51:03 +0000 (22:51 +0000)]
[ORC] Make a narrowing-cast explicit to silence a compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360478
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Lang Hames [Fri, 10 May 2019 22:24:37 +0000 (22:24 +0000)]
[JITLink][MachO] Mark atoms in sections 'no-dead-strip' set live by default.
If a MachO section has the no-dead-strip attribute set then its atoms should
be preserved, regardless of whether they're public or referenced elsewhere in
the object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360477
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Craig Topper [Fri, 10 May 2019 22:03:33 +0000 (22:03 +0000)]
[X86] Disable speculative load hardening for operations with an explicit RSP base.
After D58632, we can create idempotent atomic operations to the top of stack.
This confused speculative load hardening because it thinks accesses should have
virtual register base except for the cases it already excluded.
This commit adds a new exclusion for this case. I'll try to reduce a test case
for this, but this fix was verified to work by the reporter. This should avoid
needing to revert D58632.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360475
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Reid Kleckner [Fri, 10 May 2019 21:53:44 +0000 (21:53 +0000)]
[COFF] Fix .bss section size bug in obj2yaml / yaml2obj
We need to serialize SizeOfRawData through even when there is no data,
as in a .bss section.
Fixes PR41836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360473
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Craig Topper [Fri, 10 May 2019 21:42:27 +0000 (21:42 +0000)]
[LegalizeVectorOps] Remove calls to LegalizeOp on the return value from ExpandLoad/ExpandStore.
We already updated the LegalizedNodes map at the end of the Expand call. This
would have marked the new node as being mapped to itself. So the LegalizeOp
call will find that an immediately return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360472
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Mircea Trofin [Fri, 10 May 2019 21:27:55 +0000 (21:27 +0000)]
Skip over prefetches
Summary: Skip over prefetches when assigning debug info to instructions with memory operands. This way, the debug info is stable after instrumenting a binary with prefetches, allowing for iterative profiling and instrumentation.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: aprantl, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360471
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Nikita Popov [Fri, 10 May 2019 20:42:48 +0000 (20:42 +0000)]
[SDAG] Recursively legalize both vector mulo results
Split out from D61692 per RKSimon's suggestion. Vector op
legalization will automatically recursively legalize the returned
SDValue, but we need to take care of the other results ourselves.
Otherwise it will end up getting legalized only during op
legalization, by which point it might be too late (though I'm not
aware of any specific cases right now).
There are codegen differences because expansion occurs earlier now
and we don't get a DAGCombiner run in between.
Differential Revision: https://reviews.llvm.org/D61744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360470
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Teresa Johnson [Fri, 10 May 2019 20:08:24 +0000 (20:08 +0000)]
[ThinLTO] Auto-hide prevailing linkonce_odr only when all copies eligible
Summary:
We hit undefined references building with ThinLTO when one source file
contained explicit instantiations of a template method (weak_odr) but
there were also implicit instantiations in another file (linkonce_odr),
and the latter was the prevailing copy. In this case the symbol was
marked hidden when the prevailing linkonce_odr copy was promoted to
weak_odr. It led to unsats when the resulting shared library was linked
with other code that contained a reference (expecting to be resolved due
to the explicit instantiation).
Add a CanAutoHide flag to the GV summary to allow the thin link to
identify when all copies are eligible for auto-hiding (because they were
all originally linkonce_odr global unnamed addr), and only do the
auto-hide in that case.
Most of the changes here are due to plumbing the new flag through the
bitcode and llvm assembly, and resulting test changes. I augmented the
existing auto-hide test to check for this situation.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, eraman, dexonsmith, arphaman, dang, llvm-commits, steven_wu, wmi
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360466
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Sanjay Patel [Fri, 10 May 2019 20:02:30 +0000 (20:02 +0000)]
[DAGCombiner] reduce code duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360462
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Cameron McInally [Fri, 10 May 2019 20:01:04 +0000 (20:01 +0000)]
Add InstCombine::visitFNeg(...)
Differential Revision: https://reviews.llvm.org/D61784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360461
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Nikita Popov [Fri, 10 May 2019 19:36:38 +0000 (19:36 +0000)]
[CVP] Add tests for urem, sdiv, srem ranges; NFC
We currently don't calcuate result ranges for these binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360460
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David Blaikie [Fri, 10 May 2019 19:15:29 +0000 (19:15 +0000)]
DebugInfo: Only move types out of type units if they're named or type united
Follow up to r359122, after a bug was reported in it - the original
change too aggressively tried to move related types out of type units,
which included unnamed types (like array types) which can't reasonably
be declared-but-not-defined.
A step beyond that is that some types in type units can be anonymous, if
they are types with a name for linkage purposes (eg: "typedef struct { }
x;"). So ensure those don't get turned into plain declarations (without
signatures) because, lacking names, they can't be resolved to the
definition.
[Also include a fix for llvm-dwarfdump/libDebugInfoDWARF to pretty print
types in type units]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360458
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Simon Pilgrim [Fri, 10 May 2019 18:55:17 +0000 (18:55 +0000)]
[SLP] Refactor VectorizableTree to use unique_ptr.
This patch fixes the TreeEntry dangling pointer issue caused by reallocations of VectorizableTree.
Committed on behalf of @vporpo (Vasileios Porpodas)
Differential Revision: https://reviews.llvm.org/D61706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360456
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Paul Robinson [Fri, 10 May 2019 18:47:39 +0000 (18:47 +0000)]
Replace 'REQUIRES: nozlib' with '!zlib' because we don't need two ways
to say the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360455
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Paul Robinson [Fri, 10 May 2019 18:08:02 +0000 (18:08 +0000)]
Replace 'REQUIRES: not_?san' with 'UNSUPPORTED: ?san' as that better
expresses the intent of the exclusion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360449
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Nikita Popov [Fri, 10 May 2019 17:39:50 +0000 (17:39 +0000)]
[CVP] Add tests for abs and nabs spf; NFC
One half of the bound is already computed correctly for these
tests, the other isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360445
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Amara Emerson [Fri, 10 May 2019 17:29:35 +0000 (17:29 +0000)]
[LSR] Tweak setup cost depth threshold to 10.
The original change introduced a depth limit of 7 which caused a 22% regression
in the Swift MapReduceLazyCollection & Ackermann benchmarks. This new threshold
still ensures that the original test case doesn't hang.
rdar://
50359639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360444
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Fangrui Song [Fri, 10 May 2019 17:09:25 +0000 (17:09 +0000)]
[MC][ELF] Copy top 3 bits of st_other to .symver aliases
On PowerPC64 ELFv2 ABI, the top 3 bits of st_other encode the local
entry offset. A versioned symbol alias created by .symver should copy
the bits from the source symbol.
This partly fixes PR41048. A full fix needs tracking of .set assignments
and updating st_other fields when finish() is called, see D56586.
Patch by Alfredo Dal'Ava JĂșnior
Differential Revision: https://reviews.llvm.org/D59436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360442
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Momchil Velikov [Fri, 10 May 2019 16:54:32 +0000 (16:54 +0000)]
Adjust MachineScheduler to use ProcResource counts
This fix allows the scheduler to take into account the number of instances of
each ProcResource specified. Previously a declaration in a scheduler of
ProcResource<1> would be treated identically to a declaration of
ProcResource<2>. Now the hazard recognizer would report a hazard only after all
of the resource instances are busy.
Patch by Jackson Woodruff and Momchil Velikov.
Differential Revision: https://reviews.llvm.org/D51160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360441
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Fangrui Song [Fri, 10 May 2019 16:24:57 +0000 (16:24 +0000)]
[llvm-objdump] Print st_other
Add support for ".hidden" ".internal" ".protected" and " 0x%02x" for
other st_other bits used by some architectures.
Reviewed By: sfertile
Differential Revision: https://reviews.llvm.org/D61718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360439
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Nemanja Ivanovic [Fri, 10 May 2019 16:03:22 +0000 (16:03 +0000)]
Pull r360426 as it is breaking the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360437
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Robert Lougher [Fri, 10 May 2019 15:55:06 +0000 (15:55 +0000)]
[X86] Avoid SFB - Fix inconsistent codegen with/without debug info
Fixes https://bugs.llvm.org/show_bug.cgi?id=40969
The functions findPotentiallyBlockedCopies and buildCopy are currently not
accounting for the presence of debug instructions. In the former this results
in the optimization not being trigerred, and in the latter results in
inconsistent codegen.
This patch enables the optimization to be performed in a debug build and
ensures the codegen is consistent with non-debug builds.
Patch by Chris Dawson.
Differential Revision: https://reviews.llvm.org/D61680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360436
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Simon Pilgrim [Fri, 10 May 2019 15:46:04 +0000 (15:46 +0000)]
[X86][SSE] Add getHopForBuildVector vector splitting
If we only use the lower xmm of a ymm hop, then extract the xmm's (for free), perform the xmm hop and then insert back into a ymm (for free).
Fixes some of the regressions noted in D61782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360435
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Nemanja Ivanovic [Fri, 10 May 2019 15:44:56 +0000 (15:44 +0000)]
Another attempt to fix the build bot breaks after r360426
The test case checks were produced by the update_test_checks.py
scripts and I assumed that is sufficient. However, the behaviour
is different with different default target triples. Specify the
triple explicitly in the test case.
If this doesn't clean up the build bot breaks, I'll remove the test
case until I can get to the bottom of why the behaviour on build bots
is different from my machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360434
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Nemanja Ivanovic [Fri, 10 May 2019 15:11:40 +0000 (15:11 +0000)]
Fix build break after r360426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360433
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Michael Liao [Fri, 10 May 2019 14:57:42 +0000 (14:57 +0000)]
[InferAddressSpaces] Enhance the handling of cosntexpr.
Summary:
- Constant expressions may not be added in strict postorder as the
forward instruction scan order. Thus, for a constant express (CE0), if
its operand (CE1) is used in an previous instruction, they are not in
postorder. However, different from
`cloneInstructionWithNewAddressSpace`,
`cloneConstantExprWithNewAddressSpace` doesn't bookkeep uninferred
instructions for later resolving. That results in failure of inferring
constant address.
- This patch adds the support to infer constant expression operand
recursively, since there won't be loop, if that operand is another
constant expression.
Reviewers: arsenm
Subscribers: jholewinski, jvesely, wdng, nhaehnle, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360431
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Lei Huang [Fri, 10 May 2019 14:04:06 +0000 (14:04 +0000)]
[PowerPC] custom lower `v2f64 fpext v2f32`
Reduces scalarization overhead via custom lowering of v2f64 fpext v2f32.
eg. For the following IR
%0 = load <2 x float>, <2 x float>* %Ptr, align 8
%1 = fpext <2 x float> %0 to <2 x double>
ret <2 x double> %1
Pre custom lowering:
ld r3, 0(r3)
mtvsrd f0, r3
xxswapd vs34, vs0
xscvspdpn f0, vs0
xxsldwi vs1, vs34, vs34, 3
xscvspdpn f1, vs1
xxmrghd vs34, vs0, vs1
After custom lowering:
lfd f0, 0(r3)
xxmrghw vs0, vs0, vs0
xvcvspdp vs34, vs0
Differential Revision: https://reviews.llvm.org/D57857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360429
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Nemanja Ivanovic [Fri, 10 May 2019 13:47:00 +0000 (13:47 +0000)]
[Pass Pipeline][NFC] Add a test prior to committing D61726
This patch just adds a test case to show the differences in code emitted
by opt before and after https://reviews.llvm.org/D61726.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360426
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Cameron McInally [Fri, 10 May 2019 13:18:57 +0000 (13:18 +0000)]
Pre-commit InstCombine::visitFNeg(...) test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360424
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James Henderson [Fri, 10 May 2019 12:58:52 +0000 (12:58 +0000)]
[llvm-objcopy] Add additional testing for various cases
This patch adds a number of tests to test various cases not covered by
existing tests. All of them work correctly, with no need to change
llvm-objcopy itself, although some do indicate possible areas for
improvement.
Reviewed by: MaskRay
Differential Revision: https://reviews.llvm.org/D61727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360422
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Tim Northover [Fri, 10 May 2019 11:23:04 +0000 (11:23 +0000)]
SelectionDAG: accommodate atomic floating stores.
We were applying a pointer truncation to floating types, which crashed LLVM.
That is Not A Good Thing(TM).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360421
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Fangrui Song [Fri, 10 May 2019 10:47:30 +0000 (10:47 +0000)]
[Object] Fix macho-invalid.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360420
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Simon Pilgrim [Fri, 10 May 2019 10:22:13 +0000 (10:22 +0000)]
[cmake] Remove MSVC C4800 override
Remove C4800 : ''type' : forcing value to bool 'true' or 'false' (performance warning)' from the list of forced disabled warnings.
I'm not seeing any regressions in VS2017/VS2019 llvm/clang builds from removing this.
Differential Revision: https://reviews.llvm.org/D61730
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360417
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Fangrui Song [Fri, 10 May 2019 10:19:08 +0000 (10:19 +0000)]
[Object] Move ELF specific ObjectFile::getBuildAttributes to ELFObjectFileBase
Change the return type from std::error_code to Error and make the
function protected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360416
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Jeremy Morse [Fri, 10 May 2019 10:03:41 +0000 (10:03 +0000)]
[DebugInfo] Use zero linenos for debug intrinsics when promoting dbg.declare
In certain circumstances, optimizations pick line numbers from debug
intrinsic instructions as the new location for altered instructions. This
is problematic because the line number of a debugging intrinsic is
meaningless (it doesn't produce any machine instruction), only the scope
information is valid. The result can be the line number of a variable
declaration "leaking" into real code from debugging intrinsics, making the
line table un-necessarily jumpy, and potentially different with / without
variable locations.
Fix this by using zero line numbers when promoting dbg.declare intrinsics
into dbg.values: this is safe for debug intrinsics as their line numbers
are meaningless, and reduces the scope for damage / misleading stepping
when optimizations pick locations from the wrong place.
Differential Revision: https://reviews.llvm.org/D59272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360415
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Fangrui Song [Fri, 10 May 2019 09:59:04 +0000 (09:59 +0000)]
[Object] Change SymbolicFile::printSymbolName to use Error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360414
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Simon Pilgrim [Fri, 10 May 2019 09:54:42 +0000 (09:54 +0000)]
[cmake] Remove MSVC C4355 override
Remove C4355 : ''this' : used in base member initializer list' from the list of forced disabled warnings.
I'm not seeing any regressions in VS2017/VS2019 llvm/clang builds from removing this.
Differential Revision: https://reviews.llvm.org/D61757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360413
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Eric Christopher [Fri, 10 May 2019 07:58:47 +0000 (07:58 +0000)]
Remove an unnecessary header from SROA.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360410
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Sam Clegg [Fri, 10 May 2019 01:52:08 +0000 (01:52 +0000)]
[WebAssembly] Don't assume that strongly defined symbols are DSO-local
The current PIC model for WebAssembly is more like ELF in that it
allows symbol interposition.
This means that more functions end up being addressed via the GOT
and fewer directly added to the wasm table.
One effect is a reduction in the number of wasm table entries similar
to the previous attempt in https://reviews.llvm.org/D61539 which was
reverted.
Differential Revision: https://reviews.llvm.org/D61772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360402
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Sam Clegg [Fri, 10 May 2019 01:45:34 +0000 (01:45 +0000)]
[WebAssembly] Remove friend18.C from list of known gcc torture test failures. NFC.
Differential Revision: https://reviews.llvm.org/D61775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360401
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Mircea Trofin [Fri, 10 May 2019 00:12:51 +0000 (00:12 +0000)]
[llvm] X86DiscriminateMemOps: insert debug info when missing
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: aprantl, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61735
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360396
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Stanislav Mekhanoshin [Fri, 10 May 2019 00:09:01 +0000 (00:09 +0000)]
[AMDGPU] Pattern for v_xor3_b32
This also allows three op patterns to use increased constant bus
limit of GFX10.
Differential Revision: https://reviews.llvm.org/D61763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360395
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Philip Reames [Thu, 9 May 2019 23:23:42 +0000 (23:23 +0000)]
[X86] Improve lowering of idemptotent RMW operations
The current lowering uses an mfence. mfences are substaintially higher latency than the locked operations originally requested, but we do want to avoid contention on the original cache line. As such, use a locked instruction on a cache line assumed to be thread local.
Differential Revision: https://reviews.llvm.org/D58632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360393
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