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Ilia Mirkin [Mon, 7 Dec 2015 22:40:36 +0000 (17:40 -0500)]
gk110/ir: fix imad sat/hi flag emission for immediate args
According to nvdisasm both the immediate and non-imm cases use the same
bits. Both of these flags are quite rarely set though.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Mon, 30 Nov 2015 23:26:50 +0000 (15:26 -0800)]
i965: Add brw_device_info::min_ds_entries field.
From the 3DSTATE_URB_DS documentation:
"Project: IVB, HSW
If Domain Shader Thread Dispatch is Enabled then the minimum number of
handles that must be allocated is 10 URB entries."
"Project: BDW+
If Domain Shader Thread Dispatch is Enabled then the minimum number of
handles that must be allocated is 34 URB entries."
When the HS is run in SINGLE_PATCH mode (the only mode we support
today), there is no minimum for HS - it's just zero.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Chris Forbes [Tue, 9 Sep 2014 09:27:05 +0000 (21:27 +1200)]
i965: Add state bits for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Chris Forbes [Tue, 9 Sep 2014 09:25:00 +0000 (21:25 +1200)]
i965: Add backend structures for tess stages
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Chris Forbes [Tue, 9 Sep 2014 09:22:25 +0000 (21:22 +1200)]
i965: Set core tessellation-related limits
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sat, 25 Jul 2015 03:32:43 +0000 (20:32 -0700)]
i965: Request lowering of gl_TessLevel* from float[] to vec4s.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 30 Sep 2015 21:54:55 +0000 (14:54 -0700)]
i965: Create new files for HS/DS/TE state upload code.
For now, this just splits the existing code to disable these stages into
separate atoms/files. We can then replace it with real code.
v2: Bump the render atoms in this patch so it compiles (in my branch,
I'd bumped it in an earlier patch). 61 seems to be the minimum
that works, which doesn't match the old value + the number of atoms
I added in this patch, so apparently we had some slop before.
v3: Actually disable the DS unit on Gen8+.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ilia Mirkin [Mon, 7 Dec 2015 21:14:53 +0000 (16:14 -0500)]
gk104/ir: sampler doesn't matter for txf
We actually leave the sampler unset for OP_TXF, which caused the GK104+
logic to treat some texel fetches as indirect. While this works, it's
incredibly wasteful. This only happened when the texture was > 0 (since
sampler remained == 0).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Marek Olšák [Fri, 4 Dec 2015 19:35:08 +0000 (20:35 +0100)]
radeonsi: disable DCC on Stoney
Cc: 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Sonny Jiang [Tue, 10 Nov 2015 21:07:43 +0000 (16:07 -0500)]
winsys/amdgpu: addrlib - port a Fiji bug fix
Fiji: Fixed tiled resource failures
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
v2: fix a compile failure (typo) - Marek
Sonny Jiang [Thu, 12 Nov 2015 17:34:37 +0000 (12:34 -0500)]
winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatible
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Sonny Jiang [Thu, 12 Nov 2015 17:08:31 +0000 (12:08 -0500)]
winsys/amdgpu: addrlib - port fix error for workaround for 1D tiling
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Christian König [Mon, 23 Nov 2015 14:21:19 +0000 (15:21 +0100)]
st/va: disable MPEG4 by default v2
The workarounds are too hacky to enable them by default
and otherwise MPEG4 doesn't work reliably.
v2: add docs/envvars.html, CC stable and fix typos
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (v1)
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> (v1)
Cc: "11.1.0" <mesa-stable@lists.freedesktop.org>
Christian König [Mon, 23 Nov 2015 14:00:46 +0000 (15:00 +0100)]
st/va: move HEVC functions into separate file v2
v2: actually copy all of it
Signed-off-by: Christian König <christian.koenig@amd.com>
Alejandro Piñeiro [Sat, 5 Dec 2015 19:47:33 +0000 (20:47 +0100)]
mesa: remove _mesa_tex_target_is_array
_mesa_is_array_texture provides the same functionality and:
1. it returns bool instead of GLboolean
2. it's not related to the texture format (texformat.c)
3. the name's a little shorter
v2: remove _mesa_tex_target_is_array instead (Brian Paul)
Reviewed-by: Brian Paul <brianp@vmware.com>
Alejandro Piñeiro [Sat, 5 Dec 2015 19:46:30 +0000 (20:46 +0100)]
i965: use _mesa_is_array_texture instead of _mesa_tex_target_is_array
Both methods provide the same functionality, so one would be
removed.
v2: use _mesa_is_array_texture and not the other way (Brian Paul)
Reviewed-by: Brian Paul <brianp@vmware.com>
Ilia Mirkin [Mon, 7 Dec 2015 18:26:51 +0000 (13:26 -0500)]
gk110/ir: fix imul hi emission with limm arg
The elemental demo hits this case.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Brian Paul [Fri, 4 Dec 2015 19:26:35 +0000 (12:26 -0700)]
svga: use the debug callback to report issues to the state tracker
Use the new debug callback hook to report conformance, performance
and fallbacks to the state tracker. The state tracker, in turn can
report this issues to the user via the GL_ARB_debug_output extension.
More issues can be reported in the future; this is just a start.
v2: remove conditionals around pipe_debug_message() calls since the
check is now done in the macro itself.
v3: remove unneeded dummy %s substitutions
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>,
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Sat, 5 Dec 2015 00:44:29 +0000 (17:44 -0700)]
gallium/util: check callback pointers for non-null in pipe_debug_message()
So the callers don't have to do it.
v2: also check cb!=NULL in the macro
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Abdiel Janulgue [Tue, 11 Nov 2014 14:02:14 +0000 (16:02 +0200)]
i965: Add defines for gather push constants
v2 (Francisco Jerez):
- Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
- Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANT_*.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Timothy Arceri [Sun, 6 Dec 2015 05:02:32 +0000 (16:02 +1100)]
mesa: move GLES checks for SSO input/output validation
This function is unfinished there is a bunch more validation rules
that need to be applied here. We will still want to call it for desktop
GL we just don't want to validate precision so move the ES check to
reflect this.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Sun, 6 Dec 2015 04:30:34 +0000 (15:30 +1100)]
mesa: move GL_INVALID_OPERATION error to rendering call
The validation api doesn't trigger this error so just move it to the
code called during rendering.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 6 Dec 2015 04:17:15 +0000 (15:17 +1100)]
mesa: move pipeline input/output validation inside _mesa_validate_program_pipeline()
This allows validation to be done on rendering calls also.
Fixes 3 dEQP-GLES31.functional.separate tests.
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 6 Dec 2015 03:30:44 +0000 (14:30 +1100)]
glsl: re-validate program pipeline after sampler change
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
https://bugs.freedesktop.org/show_bug.cgi?id=93180
Dave Airlie [Mon, 7 Dec 2015 07:59:34 +0000 (17:59 +1000)]
r600: apply SIMD workaround to cayman also.
At last on ARUBA this is required to stop tessellation hanging
in heaven.
This removes one of the SIMDs from use by the HS/LS.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 7 Dec 2015 05:44:02 +0000 (05:44 +0000)]
r600: fix regression introduced with ring emit changes.
This was adding one after a CUT which broke end primitive
Dave Airlie [Mon, 7 Dec 2015 01:04:48 +0000 (11:04 +1000)]
r600: remove stale tessellation comment
pointed out by Marek.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 7 Dec 2015 00:06:44 +0000 (10:06 +1000)]
docs: consolidate r600 entry in GL3.txt
Though fp64 emulation still needs to be done for a lot of the evergreen hw.
Dave Airlie [Fri, 4 Dec 2015 04:05:54 +0000 (04:05 +0000)]
docs: update with r600 tessellation status.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:01:31 +0000 (16:01 +1000)]
r600: enable tessellation for evergreen/cayman (v2)
This enables tessellation for evergreen/cayman,
This will need changes before committing depending
on what hw works etc.
working are CAYMAN/REDWOOD/BARTS/TURKS/SUMO/CAICOS
v2: only enable on evergreen and above.
Dave Airlie [Fri, 4 Dec 2015 02:08:12 +0000 (02:08 +0000)]
r600g: reduce number of ps thread on caicos
this allows tess apps to start
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 4 Dec 2015 01:44:12 +0000 (01:44 +0000)]
r600g: adjust ls/hs thread counts for sumo
these stop tess hangs here.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:06:20 +0000 (16:06 +1000)]
r600/asm: enable nstack check for tess ctrl/eval shaders.
This just makes sure they register at least one stack
usage frame like vertex shaders.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:05:14 +0000 (16:05 +1000)]
r600/asm: handle lds read operations.
Reads from the queue shouldn't be merged for now read operations.
Reads from the queue shouldn't be merged for now, or put in
T slots.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:03:33 +0000 (16:03 +1000)]
r600/asm: add LDS ops and barrier to the once per group restriction.
LDS ops must be scheduled in X slot, and barrier should be on its
own in a group.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:02:38 +0000 (16:02 +1000)]
r600: move VGT_VTX_CNT_EN into shader stages atom.
This should be enabled for tessellation shaders as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:01:43 +0000 (16:01 +1000)]
r600: enable tcs/tes dumping for R600_DUMP_SHADERS.
Trivial patch just to enable dumping more.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 06:00:02 +0000 (16:00 +1000)]
r600: handle SIMD allocation issue with HS/LS
At least one SIMD must be kept away from the HS/LS
stages in order to avoid a hw issue on evergreen/cayman.
This patch implements this workaround.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:59:28 +0000 (15:59 +1000)]
r600/shader: increase number of inputs/outputs to 64.
Tessellation exceeds these sometimes, so increase them for now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Mon, 30 Nov 2015 05:58:18 +0000 (15:58 +1000)]
r600: handle barrier opcode.
This handles the barrier opcode for EG/CM.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:56:33 +0000 (15:56 +1000)]
r600/shader: handle tess related system-values.
This adds handling for TESSINNER/TESSOUTER in the TES
where they need to be fetched from LDS,
and TESSCOORD which comes in via r0.
It also handle primitive ID and invocation ID.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:51:54 +0000 (15:51 +1000)]
r600/shader: allow multi-dimension arrays for tcs/tes inputs/outputs.
This just allows multi-dim arrays to be processed.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:51:01 +0000 (15:51 +1000)]
r600/shader: handle TES exports and streamout
when tessellation is enabled the TES shader is responsible
for handling streamout and exports.
This adds the streamout and export workarounds to TES,
and also makes sure TES sets up spi_sid.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:48:22 +0000 (15:48 +1000)]
r600/shader: emit tessellation factors to GDS at end of TCS.
When we are finished the shader, we read back all the tess factors
from LDS and write them to special global memory storage using
GDS instructions.
This also handles adding NOP when GDS or ENDLOOP end the TCS.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:46:58 +0000 (15:46 +1000)]
r600/shader: handle TCS output writing.
TCS outputs whenever they are written in the shader,
need to be written to LDS not temporaries, this handles
this case. It also fixes up the case where the output
is a relative addressed output, so we don't try to apply
the relative address at the wrong time.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:45:46 +0000 (15:45 +1000)]
r600/shader: handle VS shader writing to the LDS outputs. (v1.1)
This writes the VS shaders outputs to the LDS memory in
the correct places.
v1.1: use 24-bit
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:41:35 +0000 (15:41 +1000)]
r600/shader: handle fetching tcs/tes inputs and tcs outputs
This handles the logic for doing fetches from LDS for
TCS and TES. For TCS we need to fetch both inputs and outputs,
for TES only inputs need to be fetched.
v2: use 24-bit ops.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:39:58 +0000 (15:39 +1000)]
r600/shader: add get_lds_offset0 helper
This retrievs the offset into the LDS for a patch or
non-patch variable, it takes the RelPatch channel
and a temporary register.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:32:18 +0000 (15:32 +1000)]
r600/shader: add function to get tess constants info
This function retrieves the tess input/output info
from the tess constant buffer that is bound to the shader.
This uses a vfetch to get the values into the shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:34:14 +0000 (15:34 +1000)]
r600/shader: add utility functions to do single slot arithmatic
These utilities are to be used to do things like integer adds and
multiplies to be used in calculating the LDS offsets etc.
It handles CAYMAN MULLO differences as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:22:06 +0000 (15:22 +1000)]
r600/eg: workaround bug with tess shader and dynamic GPRs.
When using tessellation on eg/ni chipsets, we must disable
dynamic GPRs to workaround a hw bug where the GPU hangs
when too many things get queued.
This implements something like the r600 code to emit
the transition between static and dynamic GPRs, and to
statically allocate GPRs when tessellation is enabled.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:10:51 +0000 (15:10 +1000)]
r600/shader: move get_temp and last_instruction helpers up
These are required for tess to be used earlier.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:07:34 +0000 (15:07 +1000)]
r600: bind geometry shader ring to the correct place
When tess/gs are enabled, the geom shader ring needs
to bind to the tess eval not the vertex shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:06:23 +0000 (15:06 +1000)]
r600: create fixed function tess control shader fallback.
If we have no tess control shader, then we have to use a fallback
one that just writes the tessellation factors.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:56:10 +0000 (14:56 +1000)]
r600: create LDS info constants buffer and write LDS registers. (v2)
This creates a constant buffer with the information about
the layout of the LDS memory that is given to the vertex, tess
control and tess evaluation shaders.
This also programs the LDS size and the LS_HS_CONFIG registers,
on evergreen only.
v2: calculate lds hs num waves properly (Marek)
Emit the state only when something has changed (airlied).
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:49:02 +0000 (14:49 +1000)]
r600/eg: update shader stage emission/tf param for tess.
This update the setting of the shader stages register
when tess is enabled and add the setting of the VGT_TF_PARAM
register from the tess shader properties.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:47:07 +0000 (14:47 +1000)]
r600: hook TES/TCS shaders to the selection logic.
This hooks the TES/TCS bindings to the HW stages up.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:44:30 +0000 (14:44 +1000)]
r600: workout bitmask for the used tcs inputs/outputs.
This is used later to setup the constants to be given
to the tessellation shaders.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:43:07 +0000 (14:43 +1000)]
r600: port over the get_lds_unique_index from radeonsi
On r600 this needs to subtract 9 due to texcoord interactions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:38:18 +0000 (14:38 +1000)]
r600: add set_tess_state callback.
This just stores the values in the context to be used later
when emitting the constant buffers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:33:05 +0000 (14:33 +1000)]
r600/eg: init tess registers to defaults (v1.1)
This initialises the tess min/max using fglrx values,
and also initialises a number of other registers related
to tessellation.
v1.1: caicos doesn't have some registers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:55:43 +0000 (10:55 +1000)]
r600: hook up constants/samplers/sampler view for tessellation
This hooks the resources to the correct hw shaders when tess
is enabled.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:53:58 +0000 (10:53 +1000)]
r600: add create/bind/delete shader hooks for tessellation
This hooks up the gallium API for the tessellation shaders.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:52:23 +0000 (10:52 +1000)]
r600/sb: add LS/HS hw shader types.
This just adds printing for the hw shader types, and hooks it up.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:51:21 +0000 (10:51 +1000)]
r600/blit: add tcs/tes shader saves.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:49:11 +0000 (10:49 +1000)]
r600: disable SB for now on tess related shaders.
Note we have to disable on vertex shaders when we are
operating in tes mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:48:14 +0000 (10:48 +1000)]
r600: update correct hw shaders depending on configuration.
This updates the tess hw shaders from the sw ones routing
things correctly.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:45:19 +0000 (10:45 +1000)]
r600: add shader key entries for tcs and tes.
with tessellation vs can now run on ls, and tes can
run on vs or es, tcs runs on hs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:40:30 +0000 (10:40 +1000)]
r600: add PATCHES to the pipe conversion.
This just converts the value to the hw value.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:29:12 +0000 (10:29 +1000)]
r600: add functions to update ls/hs state.
This just adds the two functions, these will get hooked up
later in the shader code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Glenn Kennard [Mon, 30 Nov 2015 00:10:23 +0000 (10:10 +1000)]
r600g/sb: Support LDS ops in SB bytecode I/O
This just adds the LDS ops to the SB bytecode reader/writers.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:07:44 +0000 (10:07 +1000)]
r600: add support for LDS instruction encoding.
These are used in tessellation shaders to read/write values
between VS/TCS/TES.
This splits the eg alu assembler out to handle these
instructions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:04:32 +0000 (10:04 +1000)]
r600/sb: add support for GDS to the sb decoder/dump. (v1.1)
This just adds support to the decoder, not actual SB support.
v1.1: fixup GDS relative mode. (Glenn).
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:01:41 +0000 (10:01 +1000)]
r600: add support for GDS clause to the assembler.
This just adds enough for the tessellation shaders,
which require TF_WRITE to work.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:46:14 +0000 (11:46 +1000)]
r600: use macros for updating the various stages.
These macros will make things easier to see when tess
is added to the mix.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:20:05 +0000 (11:20 +1000)]
r600: add SET_NULL_SHADER macro.
This is used to set a hw shader to NULL.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:17:08 +0000 (11:17 +1000)]
r600: move clip misc and streamout stream updates to a single place
This will be updated in a macro later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:14:26 +0000 (11:14 +1000)]
r600: move selecting shaders into earlier code.
select the ps/gs/vs in that order then process the results.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:12:07 +0000 (11:12 +1000)]
r600: use a macro to remove common shader selection code.
This function is going to get a lot messier with tessellation
so I'm going to use some macros to try and clean some bits
of common code up.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 03:27:22 +0000 (13:27 +1000)]
r600: move to using hw stages array for hw stage atoms
This moves to using an array of hw stages for the atoms.
Note this drops the 23 from the vertex shader, this value
is calculated internally when shaders are bound, so not
required here.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 03:15:57 +0000 (13:15 +1000)]
r600: make adjust_gprs use hw stages.
This changes the r600 specific GPR adjustment code
to use the stage defines, and arrays.
This is prep work for the tess changes later.
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 03:12:45 +0000 (13:12 +1000)]
r600: introduce HW shader stage defines
Add a list of defines for the HW stages.
We will use this for GPR calculations amongst other things.
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:41:27 +0000 (14:41 +1000)]
r600: fix masks for two of the unused evergreen regs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Fri, 4 Dec 2015 09:08:09 +0000 (20:08 +1100)]
gallium: Remove redundant NULL ptr checks
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 11:08:22 +0000 (22:08 +1100)]
gallium/drivers: Sanitize NULL checks into canonical form
Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 10:26:50 +0000 (21:26 +1100)]
gallium/auxiliary: Sanitize NULL checks into canonical form
Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 06:12:30 +0000 (17:12 +1100)]
gallium/auxiliary: Trivial code style cleanup
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 05:47:56 +0000 (16:47 +1100)]
gallium/drivers: Trivial code-style cleanup
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 05:36:02 +0000 (16:36 +1100)]
gallium/auxiliary: Fix zero integer literal to pointer comparison
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:34:33 +0000 (15:34 +1100)]
winsys/amdgpu: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:31:40 +0000 (15:31 +1100)]
svga: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:28:11 +0000 (15:28 +1100)]
llvmpipe: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:27:18 +0000 (15:27 +1100)]
gallium/drivers/nouveau: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Sun, 6 Dec 2015 07:37:49 +0000 (18:37 +1100)]
gallium/radeon*: Remove useless casts
These are unnecessary and are likely just left overs from prior
work.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Fri, 4 Dec 2015 22:26:32 +0000 (17:26 -0500)]
nv50/ir: fold shl + mul with immediates
On SM20 this gives:
total instructions in shared programs :
6299222 ->
6294240 (-0.08%)
total gprs used in shared programs : 944139 -> 944068 (-0.01%)
total local used in shared programs : 54116 -> 54116 (0.00%)
local gpr inst bytes
helped 0 126 2781 2781
hurt 0 55 11 11
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 20:21:11 +0000 (15:21 -0500)]
nv50/ir: propagate indirect loads into instructions
This way $r1 = $r0 + 4; c1[$r1] becomes c1[$r0+4].
On SM35:
total instructions in shared programs :
6206257 ->
6185058 (-0.34%)
total gprs used in shared programs : 911045 -> 910722 (-0.04%)
total local used in shared programs : 39072 -> 39072 (0.00%)
local gpr inst bytes
helped 0 417 4195 4195
hurt 0 280 0 0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 21:05:56 +0000 (16:05 -0500)]
nv50/ir: flip shl(add, imm) into add(shl, imm)
This works when the add also has an immediate. This often happens in
address calculations. These addresses can then be inlined as well.
On code targeted to SM35:
total instructions in shared programs :
6223346 ->
6206257 (-0.27%)
total gprs used in shared programs : 911075 -> 911045 (-0.00%)
total local used in shared programs : 39072 -> 39072 (0.00%)
local gpr inst bytes
helped 0 119 3664 3664
hurt 0 74 15 15
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Anholt [Fri, 4 Dec 2015 21:41:50 +0000 (13:41 -0800)]
vc4: Fix accidental scissoring when scissor is disabled.
Even if the rasterizer has scissor disabled, we'll have whatever
vc4->scissor bounds were last set when someone set up a scissor, so we
shouldn't clip to them in that case.
Fixes piglit fbo-blit-rect, and a lot of MSAA tests once they're enabled.
Eric Anholt [Fri, 4 Dec 2015 21:15:01 +0000 (13:15 -0800)]
vc4: Disable RCL blitting when scissors are enabled.
We could potentially handle scissored blits when they're tile aligned, but
it doesn't seem worth it. If you're doing a scissored blit, you're
probably a testcase.
Fixes piglit's fbo-scissor-blit fbo
Eric Anholt [Sat, 5 Dec 2015 20:25:25 +0000 (12:25 -0800)]
vc4: Bring over cleanups from submitting to the kernel.