OSDN Git Service
Benjamin Kramer [Sat, 28 Apr 2012 16:22:26 +0000 (16:22 +0000)]
Use the most basic superclass of SmallVector in ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155760
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Jakob Stoklund Olesen [Sat, 28 Apr 2012 06:21:38 +0000 (06:21 +0000)]
Fix a problem with blocks that need to be split twice.
The code could search past the end of the basic block when there was
already a constant pool entry after the block.
Test case with giant basic block in SingleSource/UnitTests/Vector/constpool.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155753
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Andrew Trick [Sat, 28 Apr 2012 01:03:23 +0000 (01:03 +0000)]
Reapply 155668: Fix the SD scheduler to avoid gluing the same node twice.
This time, also fix the caller of AddGlue to properly handle
incomplete chains. AddGlue had failure modes, but shamefully hid them
from its caller. It's luck ran out.
Fixes rdar://
11314175: BuildSchedUnits assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155749
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Jim Grosbach [Fri, 27 Apr 2012 23:51:36 +0000 (23:51 +0000)]
ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.
rdar://
11219154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748
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Jim Grosbach [Fri, 27 Apr 2012 23:51:33 +0000 (23:51 +0000)]
ARM: Tweak tADDrSP definition for consistent operand order.
Make the operand order of the instruction match that of the asm syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155747
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Derek Schuff [Fri, 27 Apr 2012 23:37:41 +0000 (23:37 +0000)]
Revert r155745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155746
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Derek Schuff [Fri, 27 Apr 2012 23:27:17 +0000 (23:27 +0000)]
Fix fastcc structure return with fast-isel on x86-32
On x86-32, structure return via sret lets the callee pop the hidden
pointer argument off the stack, which the caller then re-pushes.
However if the calling convention is fastcc, then a register is used
instead, and the caller should not adjust the stack. This is
implemented with a check of IsTailCallConvention
X86TargetLowering::LowerCall but is now checked properly in
X86FastISel::DoSelectCall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155745
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Jakob Stoklund Olesen [Fri, 27 Apr 2012 22:58:38 +0000 (22:58 +0000)]
Track worst case alignment padding more accurately.
Previously, ARMConstantIslandPass would conservatively compute the
address of an aligned basic block as:
RoundUpToAlignment(Offset + UnknownPadding)
This worked fine for the layout algorithm itself, but it could fool the
verify() function because it accounts for alignment padding twice: Once
when adding the worst case UnknownPadding, and again by rounding up the
fictional block offset. This meant that when optimizeThumb2Instructions
would shrink an instruction, the conservative distance estimate could
grow. That shouldn't be possible since the woorst case alignment padding
wss already included.
This patch drops the use of RoundUpToAlignment, and depends only on
worst case padding to compute conservative block offsets. This has the
weird effect that the computed offset for an aligned block may not be
aligned.
The important difference is that shrinking an instruction can never
cause the estimated distance between two instructions to grow. The
estimated distance is always larger than the real distance that only the
assembler knows.
<rdar://problem/
11339352>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155744
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Andrew Trick [Fri, 27 Apr 2012 22:55:59 +0000 (22:55 +0000)]
Temporarily revert r155668: Fix the SD scheduler to avoid gluing.
This definitely caused regression with ARM -mno-thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155743
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Craig Topper [Fri, 27 Apr 2012 22:54:43 +0000 (22:54 +0000)]
Use 'unsigned' instead of 'int' in several places when retrieving number of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155742
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Chad Rosier [Fri, 27 Apr 2012 22:33:25 +0000 (22:33 +0000)]
Add x86-specific DAG combine to simplify:
x == -y --> x+y == 0
x != -y --> x+y != 0
On x86, the generated code goes from
negl %esi
cmpl %esi, %edi
je .LBB0_2
to
addl %esi, %edi
je .L4
This case is correctly handled for ARM with "cmn".
Patch by Manman Ren.
rdar://
11245199
PR12545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155739
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Michael J. Spencer [Fri, 27 Apr 2012 21:12:20 +0000 (21:12 +0000)]
[Support/YAMLParser] Fix ASan found bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155735
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Craig Topper [Fri, 27 Apr 2012 21:05:09 +0000 (21:05 +0000)]
Tidy up spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155733
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Evan Cheng [Fri, 27 Apr 2012 20:48:18 +0000 (20:48 +0000)]
Make test less fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155732
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Hal Finkel [Fri, 27 Apr 2012 19:34:00 +0000 (19:34 +0000)]
Don't vectorize target-specific types (ppc_fp128, x86_fp80, etc.).
Target specific types should not be vectorized. As a practical matter,
these types are already register matched (at least in the x86 case),
and codegen does not always work correctly (at least in the ppc case,
and this is not worth fixing because ppc_fp128 is currently broken and
will probably go away soon).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155729
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David Blaikie [Fri, 27 Apr 2012 19:30:32 +0000 (19:30 +0000)]
Change recurse depth limit to uint32 to fix warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155727
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David Blaikie [Fri, 27 Apr 2012 19:30:29 +0000 (19:30 +0000)]
Switch to c-style comments in a C file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155726
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Dan Gohman [Fri, 27 Apr 2012 18:56:31 +0000 (18:56 +0000)]
Miscellaneous accumulated cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155725
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Lang Hames [Fri, 27 Apr 2012 18:51:24 +0000 (18:51 +0000)]
Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,
<rdar://problem/
11325085>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724
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Mon P Wang [Fri, 27 Apr 2012 18:09:28 +0000 (18:09 +0000)]
Add an early bailout to IsValueFullyAvailableInBlock from deeply nested blocks.
The limit is set to an arbitrary 1000 recursion depth to avoid stack overflow
issues. <rdar://problem/
11286839>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155722
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Dan Gohman [Fri, 27 Apr 2012 17:50:22 +0000 (17:50 +0000)]
Reapply r155682, making constant folding more consistent, with a fix to work
properly with how the code handles all-undef PHI nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155721
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Richard Barton [Fri, 27 Apr 2012 17:34:01 +0000 (17:34 +0000)]
Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720
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Jim Grosbach [Fri, 27 Apr 2012 16:29:22 +0000 (16:29 +0000)]
Remove a docs reference to the CBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155716
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Benjamin Kramer [Fri, 27 Apr 2012 12:21:46 +0000 (12:21 +0000)]
Missed some register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155706
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Benjamin Kramer [Fri, 27 Apr 2012 12:14:03 +0000 (12:14 +0000)]
Update edis test for r155704.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155705
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Benjamin Kramer [Fri, 27 Apr 2012 12:07:43 +0000 (12:07 +0000)]
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704
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Evgeniy Stepanov [Fri, 27 Apr 2012 10:27:32 +0000 (10:27 +0000)]
Update config.sub in the sample project.
This change replaces projects/sample/autoconf/config.sub with a copy of
autoconf/config.sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155703
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Kostya Serebryany [Fri, 27 Apr 2012 10:04:53 +0000 (10:04 +0000)]
[asan] small optimization: do not emit "x+0" instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155701
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Richard Barton [Fri, 27 Apr 2012 08:42:59 +0000 (08:42 +0000)]
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700
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NAKAMURA Takumi [Fri, 27 Apr 2012 07:59:20 +0000 (07:59 +0000)]
Revert r155682, "Use ConstantExpr::getExtractElement when constant-folding vectors"
It broke stage2 build. stage1/clang sometimes crashed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155699
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Kostya Serebryany [Fri, 27 Apr 2012 07:31:53 +0000 (07:31 +0000)]
[tsan] Atomic support for ThreadSanitizer, patch by Dmitry Vyukov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155698
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Craig Topper [Fri, 27 Apr 2012 07:11:58 +0000 (07:11 +0000)]
Add mcpu to tests to prevent them from using AVX instructions on Sandy Bridge after r155618.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155696
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Evan Cheng [Fri, 27 Apr 2012 02:11:10 +0000 (02:11 +0000)]
Implement a bastardized ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686
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Evan Cheng [Fri, 27 Apr 2012 01:27:19 +0000 (01:27 +0000)]
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://
11331541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685
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Dan Gohman [Fri, 27 Apr 2012 00:54:36 +0000 (00:54 +0000)]
Use ConstantExpr::getExtractElement when constant-folding vectors
instead of getAggregateElement. This has the advantage of being
more consistent and allowing higher-level constant folding to
procede even if an inner extract element cannot be folded.
Make ConstantFoldInstruction call ConstantFoldConstantExpression
on the instruction's operands, making it more consistent with
ConstantFoldConstantExpression itself. This makes sure that
ConstantExprs get TargetData-aware folding before being handed
off as operands for further folding.
This causes more expressions to be folded, but due to a known
shortcoming in constant folding, this currently has the side effect
of stripping a few more nuw and inbounds flags in the non-targetdata
side of constant-fold-gep.ll. This is mostly harmless.
This fixes rdar://
11324230.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155682
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Jakob Stoklund Olesen [Thu, 26 Apr 2012 23:33:11 +0000 (23:33 +0000)]
Break up getProfitableChainIncrement().
The required checks are moved to ChainInstruction() itself and the
policy decisions are moved to IVChain::isProfitableInc().
Also cache the ExprBase in IVChain to avoid frequent recomputations.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155676
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Jakob Stoklund Olesen [Thu, 26 Apr 2012 23:33:09 +0000 (23:33 +0000)]
Turn IVChain into a struct.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155675
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Chad Rosier [Thu, 26 Apr 2012 23:29:14 +0000 (23:29 +0000)]
Add instcombine patterns for the following transformations:
(x & y) | (x ^ y) -> x | y
(x & y) + (x ^ y) -> x | y
Patch by Manman Ren.
rdar://
10770603
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155674
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Evan Cheng [Thu, 26 Apr 2012 22:07:28 +0000 (22:07 +0000)]
DumpSegment64Command() wasn't returning correct result. Caught by static analyzer. rdar://
11329354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155669
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Andrew Trick [Thu, 26 Apr 2012 21:48:25 +0000 (21:48 +0000)]
Fix the SD scheduler to avoid gluing the same node twice.
DAGCombine strangeness may result in multiple loads from the same
offset. They both may try to glue themselves to another load. We could
insist that the redundant loads glue themselves to each other, but the
beter fix is to bail out from bad gluing at the time we detect it.
Fixes rdar://
11314175: BuildSchedUnits assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155668
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Ted Kremenek [Thu, 26 Apr 2012 20:54:27 +0000 (20:54 +0000)]
Defensively guard against calling malloc() with a size of zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155661
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Jim Grosbach [Thu, 26 Apr 2012 20:48:12 +0000 (20:48 +0000)]
ARM: Thumb ldr(literal) base address alignment is 32-bits.
The base address for the PC-relative load is Align(PC,4), so it's the
address of the word containing the 16-bit instruction, not the address
of the instruction itself. Ugh.
rdar://
11314619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659
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Joerg Sonnenberger [Thu, 26 Apr 2012 20:10:07 +0000 (20:10 +0000)]
Add note about returns_twice magic removal from LLVM itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155657
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Preston Gurd [Thu, 26 Apr 2012 19:52:27 +0000 (19:52 +0000)]
Trivial change to set UseLeaForSP flag in addition to toggling
the FeatureLeaForSP feature bit when llvm auto detects Intel Atom.
Patch by Andy Zhang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155655
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Michael J. Spencer [Thu, 26 Apr 2012 19:43:35 +0000 (19:43 +0000)]
[CMake] Restructure how Clang, Polly and other external projects get included.
While making lld build under the tools directory I decided to refactor how this
works.
There is now a macro, add_llvm_external_project, which takes the name of the
expected subdirectory. This sets up two CMake options.
* LLVM_EXTERNAL_${NAME}_SOURCE_DIR
This is the path to the source. It defaults to
${CMAKE_CURRENT_SOURCE_DIR}/${name}.
* LLVM_EXTERNAL_${NAME}_BUILD
Enable and disable building the tool as part of LLVM.
I chose LLVM_EXTERNAL_${NAME} as a prefix so they all show up together in the
GUI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155654
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Michael J. Spencer [Thu, 26 Apr 2012 19:27:11 +0000 (19:27 +0000)]
[Support/YAML] Properly fix unitialized variable warning by inserting a
'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155653
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Stepan Dyatkovskiy [Thu, 26 Apr 2012 18:45:24 +0000 (18:45 +0000)]
Fixed SmallMap test. The order of items is undefined in DenseMap. So being checking the increment for big mode, we can only check that all items are in map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155651
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Tim Northover [Thu, 26 Apr 2012 08:46:29 +0000 (08:46 +0000)]
Use VLD1 in NEON extenting-load patterns instead of VLDR.
On some cores it's a bad idea for performance to mix VFP and NEON instructions
and since these patterns are NEON anyway, the NEON load should be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155630
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Tim Northover [Thu, 26 Apr 2012 08:24:07 +0000 (08:24 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155626
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Craig Topper [Thu, 26 Apr 2012 06:40:15 +0000 (06:40 +0000)]
Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618
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Chandler Carruth [Thu, 26 Apr 2012 05:30:30 +0000 (05:30 +0000)]
Teach the reassociate pass to fold chains of multiplies with repeated
elements to minimize the number of multiplies required to compute the
final result. This uses a heuristic to attempt to form near-optimal
binary exponentiation-style multiply chains. While there are some cases
it misses, it seems to at least a decent job on a very diverse range of
inputs.
Initial benchmarks show no interesting regressions, and an 8%
improvement on SPASS. Let me know if any other interesting results (in
either direction) crop up!
Credit to Richard Smith for the core algorithm, and helping code the
patch itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155616
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Evan Cheng [Thu, 26 Apr 2012 01:38:10 +0000 (01:38 +0000)]
Specify cpu to unbreak tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604
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Evan Cheng [Thu, 26 Apr 2012 01:13:36 +0000 (01:13 +0000)]
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.
rdar://
11318438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601
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Bill Wendling [Thu, 26 Apr 2012 00:38:42 +0000 (00:38 +0000)]
Don't forget to reset 'first operand' flag when we're setting the MDNodeOperand value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155599
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 21:22:33 +0000 (21:22 +0000)]
Try to fix llvm-arm-linux builder with -mcpu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155589
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Preston Gurd [Wed, 25 Apr 2012 21:04:54 +0000 (21:04 +0000)]
Trivial change to make the test use -mcpu=generic so as to avoid
a failure if run on an Intel Atom with post RA instruction scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155587
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Benjamin Kramer [Wed, 25 Apr 2012 18:01:58 +0000 (18:01 +0000)]
Reapply the SmallMap patch with a fix.
Comparing ~0UL with an unsigned will always return false when long is 64 bits long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155568
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 18:01:32 +0000 (18:01 +0000)]
Print IV chain numbers while collecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155567
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 18:01:30 +0000 (18:01 +0000)]
Remove more dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155566
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Richard Barton [Wed, 25 Apr 2012 18:00:18 +0000 (18:00 +0000)]
Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565
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Eric Christopher [Wed, 25 Apr 2012 17:51:00 +0000 (17:51 +0000)]
Revert "First implementation of:"
This reverts commit
76271a3366731d4c372fdebcd8d3437e6e09a61b.
as it's breaking the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155562
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Stepan Dyatkovskiy [Wed, 25 Apr 2012 17:09:38 +0000 (17:09 +0000)]
First implementation of:
- FlatArrayMap. Very simple map container that uses flat array inside.
- MultiImplMap. Map container interface, that has two modes, one for small amount of elements and one for big amount.
- SmallMap. SmallMap is DenseMap compatible MultiImplMap. It uses FlatArrayMap for small mode, and DenseMap for big mode.
Also added unittests for new classes and update for ProgrammersManual.
For more details about new classes see ProgrammersManual and comments in sourcecode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155557
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 16:32:23 +0000 (16:32 +0000)]
Simplify LiveIntervals::getApproximateInstructionCount().
This function is only used for a heuristic during -join-physregs. It
doesn't need floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155554
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 16:32:20 +0000 (16:32 +0000)]
Remove a dead function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155553
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 16:17:50 +0000 (16:17 +0000)]
Remove the -disable-cross-class-join option.
Cross-class joins have been normal and fully supported for a while now.
With TableGen generating the getMatchingSuperRegClass() hook, they are
unlikely to cause problems again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155552
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Jakob Stoklund Olesen [Wed, 25 Apr 2012 16:17:47 +0000 (16:17 +0000)]
Cross-class joining is winning.
Remove the heuristic for disabling cross-class joins. The greedy
register allocator can handle the narrow register classes, and when it
splits a live range, it can pick a larger register class.
Benchmarks were unaffected by this change.
<rdar://problem/
11302212>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155551
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Craig Topper [Wed, 25 Apr 2012 06:56:34 +0000 (06:56 +0000)]
Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155538
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Craig Topper [Wed, 25 Apr 2012 06:39:39 +0000 (06:39 +0000)]
Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155537
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Chris Lattner [Wed, 25 Apr 2012 06:37:20 +0000 (06:37 +0000)]
openbsd doesn't support soname, patch by Brad Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155536
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Chandler Carruth [Wed, 25 Apr 2012 02:30:00 +0000 (02:30 +0000)]
Actually delete now-empty file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155532
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Lang Hames [Wed, 25 Apr 2012 02:16:54 +0000 (02:16 +0000)]
Reverting r155468. Chris and Chandler have convinced me that it's dangerous and
in poor taste.
Talking through some alternate solutions with Chandler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155530
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Akira Hatanaka [Wed, 25 Apr 2012 01:24:52 +0000 (01:24 +0000)]
Do not use $gp as a dedicated global register if the target ABI is not O32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155522
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Andrew Trick [Wed, 25 Apr 2012 01:11:22 +0000 (01:11 +0000)]
typo in declaration from earlier today
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155519
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Dan Gohman [Wed, 25 Apr 2012 00:50:46 +0000 (00:50 +0000)]
Simplify the known retain count tracking; use a boolean state instead
of a precise count. Also, move RRInfo's Partial field into PtrState,
now that it won't increase the size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155513
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Dan Gohman [Tue, 24 Apr 2012 22:53:18 +0000 (22:53 +0000)]
Build custom predecessor and successor lists for each basic block.
These lists exclude invoke unwind edges and loop backedges which
are being ignored. This makes it easier to ignore them
consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155500
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Jim Grosbach [Tue, 24 Apr 2012 22:40:08 +0000 (22:40 +0000)]
ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://
11257547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499
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Andrew Trick [Tue, 24 Apr 2012 20:36:19 +0000 (20:36 +0000)]
Fix a naughty header include that breaks "installed" builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486
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Nadav Rotem [Tue, 24 Apr 2012 20:18:49 +0000 (20:18 +0000)]
ConstantFoldSelectInstruction swapped the operands of the select.
Fix 12592. Patch by Matt Pharr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155480
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Nadav Rotem [Tue, 24 Apr 2012 19:57:38 +0000 (19:57 +0000)]
Fix the testcase. We do expect two vblendw on XMMs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155477
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Nadav Rotem [Tue, 24 Apr 2012 19:45:28 +0000 (19:45 +0000)]
Add a testcase for 155440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155475
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Evan Cheng [Tue, 24 Apr 2012 19:06:55 +0000 (19:06 +0000)]
MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://
11300144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155470
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Lang Hames [Tue, 24 Apr 2012 18:58:36 +0000 (18:58 +0000)]
Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixes
<rdar://problem/
11291436>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155468
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Chandler Carruth [Tue, 24 Apr 2012 18:42:47 +0000 (18:42 +0000)]
Fix a crash on valid (if UB) bitcode that is produced for some global
constants in C++11 mode. I have no idea why it required such particular
circumstances to get here, the code seems clearly to rely upon unchecked
assumptions.
Specifically, when we decide to form an index into a struct type, we may
have gone through (at least one) zero-length array indexing round, which
would have left the offset un-adjusted, and thus not necessarily valid
for use when indexing the struct type.
This is just an canonicalization step, so the correct thing is to refuse
to canonicalize nonsensical GEPs of this form. Implemented, and test
case added.
Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit
him with most of the debugging, and preventing me from writing the wrong
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155466
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Jim Grosbach [Tue, 24 Apr 2012 18:39:47 +0000 (18:39 +0000)]
ARM: Nuke remnant bogus code.
r154362 was supposed to delete this bit, but obviously didn't.
rdar://
11305594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155465
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Stepan Dyatkovskiy [Tue, 24 Apr 2012 18:31:10 +0000 (18:31 +0000)]
Related to PR1255. Let's begin. I'll commit classes that corresponds to our latest PR1255 discussion posts in llvm-commits.
Strategy.
0. Implement new classes. Classes doesn't affect anything. They still work with ConstantInt base values at this stage.
1. Fictitious replacement of current ConstantInt case values with ConstantRangesSet. Case ranges set will still hold single value, and ConstantInt *getCaseValue() will return it. But additionally implement new method in SwitchInst that allows to work with case ranges. Currenly I think it should be some wrapper that returns either single value or ConstantRangesSet object.
2. Step-by-step replacement of old "ConstantInt* getCaseValue()" with new alternative. Modify algorithms for all passes that works with SwitchInst. But don't modify LLParser and BitcodeReader/Writer. Still hold single value in each ConstantRangesSet object. On this stage some parts of LLVM will use old-style methods, and some ones new-style.
3. After all getCaseValue() usages will removed and whole LLVM and its clients will work in new style - modify LLParser, Reader and Writer. Remove getCaseValue().
4. Replace ConstantInt*-based case ranges set items with APInt ones.
Currently we are on Zero Stage: New classes.
ConstantRangesSet.
I selected ConstantArrays as case ranges set "holder" object (it is a temporary decision, I'll explain why below). The array items are may be ConstantVectors with single item, and ConstantVectors with two items (that means single number and range respectively).
The ConstantInt will used as basic value representation. It will replaced with APInt then. Of course ConstantArray and ConstantVector will go away after ConstantInt => APInt replacement.
New class mandatory features:
- bool isSatisfies(ConstantInt *V) method (need better name?). Returns true if the given value satisfies this case.
- Case's ranges and values enumeration. In some passes we need to analize each case (SwitchLowering for example).
Factory + unified clusterify.
I also propose to implement the factory that allows to build case object with user friendly way. I called it CRSBuilder by now.
Currenly I implemented the factory that allows add,remove pairs of range+successor. It also allows add existing ConstantRangesSet decompiling it to separated ranges. Factory can emit either clusters set (single case range + successor) or the set of "ConstantRangesSet + Successor" pairs.
So you can use it either as builder for new cases set for SwitchInst, or for clusterification of existing cases set.
Just call Factory.optimize() and it emits optimized and sorted clusters collection for you!
I tested clusterification on SelectionDAGBuilder - it works fine. Don't worry it was not included in this patch. Just new classes.
Factory is a template. There are two params: SuccessorClass and IsReadonly. So you can specify what successor you need (BB or MBB). And you can also restrict your factory to use values in read-only mode (SelectionDAGBuilder need IsReadonly=true). Read-only factory couldn't build the cases ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155464
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Nadav Rotem [Tue, 24 Apr 2012 18:09:59 +0000 (18:09 +0000)]
AVX: Add additional vbroadcast replacement sequences for integers.
Remove the v2f64 patterns because it does not match any vbroadcast
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155461
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Andrew Trick [Tue, 24 Apr 2012 18:06:49 +0000 (18:06 +0000)]
cmake: new file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155460
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Andrew Trick [Tue, 24 Apr 2012 18:04:41 +0000 (18:04 +0000)]
misched: DAG builder must special case earlyclobber
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155459
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Andrew Trick [Tue, 24 Apr 2012 18:04:37 +0000 (18:04 +0000)]
misched: try (not too hard) to place debug values where they belong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155458
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Andrew Trick [Tue, 24 Apr 2012 18:04:34 +0000 (18:04 +0000)]
misched: ignore debug values during scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155457
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Andrew Trick [Tue, 24 Apr 2012 17:56:43 +0000 (17:56 +0000)]
misched: DAG builder support for tracking register pressure within the current scheduling region.
The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456
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Andrew Trick [Tue, 24 Apr 2012 17:53:35 +0000 (17:53 +0000)]
RegisterPressure: A utility for computing register pressure within a
MachineInstr sequence.
This uses the new target interface for tracking register pressure
using pressure sets to model overlapping register classes and
subregisters.
RegisterPressure results can be tracked incrementally or stored at
region boundaries. Global register pressure can be deduced from local
RegisterPressure results if desired.
This is an early, somewhat untested implementation. I'm working on
testing it within the context of a register pressure reducing
MachineScheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155454
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Kevin Enderby [Tue, 24 Apr 2012 17:45:56 +0000 (17:45 +0000)]
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453
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Kevin Enderby [Tue, 24 Apr 2012 15:55:00 +0000 (15:55 +0000)]
Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444
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Nadav Rotem [Tue, 24 Apr 2012 11:27:53 +0000 (11:27 +0000)]
AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440
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Richard Barton [Tue, 24 Apr 2012 11:13:20 +0000 (11:13 +0000)]
Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155439
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Nadav Rotem [Tue, 24 Apr 2012 11:07:03 +0000 (11:07 +0000)]
AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions
using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155437
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Bill Wendling [Tue, 24 Apr 2012 11:03:50 +0000 (11:03 +0000)]
Look for the 'Is Simulated' module flag. This indicates that the program is compiled to run on a simulator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155435
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Bill Wendling [Tue, 24 Apr 2012 10:45:44 +0000 (10:45 +0000)]
FileCheck-ize tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155434
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Bill Wendling [Tue, 24 Apr 2012 10:36:42 +0000 (10:36 +0000)]
FileCheck-ize these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155433
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