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Craig Topper [Sun, 5 Mar 2017 01:08:16 +0000 (01:08 +0000)]
[DAGCombine] Use APInt::operator|(uint64_t) instead of creating a temporary APInt and calling APInt::Or. NFC
This is more efficient by itself. But this is prep for a future patch that may remove APInt::Or while making operator| support rvalue references similar to add/sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296981
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Sanjay Patel [Sat, 4 Mar 2017 20:35:19 +0000 (20:35 +0000)]
[x86] don't require a zext when forming ADC/SBB
The larger goal is to move the ADC/SBB transforms currently in
combineX86SetCC() to combineAddOrSubToADCOrSBB() because we're
creating ADC/SBB in lots of places where we shouldn't.
This was intended to be an NFC change, but avx-512 has something
strange going on. It doesn't seem like any of the affected tests
should really be using SET+TEST or ADC; a simple ADD could replace
several instructions. But that's another bug...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296978
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Sanjay Patel [Sat, 4 Mar 2017 19:18:09 +0000 (19:18 +0000)]
[DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)
select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook.
This is part of the ongoing process to obsolete D24480. The motivation is to
canonicalize to select IR in InstCombine whenever possible, so we need to have a way to
undo that easily in codegen.
PowerPC is an obvious winner for this kind of transform because it has fast and complete
bit-twiddling abilities but generally lousy conditional execution perf (although this might
have changed in recent implementations).
x86 also sees some wins, but the effect is limited because these transforms already mostly
exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86
changes just shows that that code is a mess of special-case holes. We may be able to remove
some of that logic now.
My guess is that other targets will want to enable this hook for most cases. The likely
follow-ups would be to add value type and/or the constants themselves as parameters for the
hook. As the tests in select_const.ll show, we can transform any select-of-constants to
math/logic, but the general transform for any 2 constants needs one more instruction
(multiply or 'and').
ARM is one target that I think may not want this for most cases. I see infinite loops there
because it wants to use selects to enable conditionally executed instructions.
Differential Revision: https://reviews.llvm.org/D30537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296977
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Zachary Turner [Sat, 4 Mar 2017 18:53:09 +0000 (18:53 +0000)]
Try to fix thread name truncation on non-Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296976
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Kamil Rytarowski [Sat, 4 Mar 2017 17:42:46 +0000 (17:42 +0000)]
Improve the Threading code on NetBSD
Do not include <sys/user.h> on NetBSD. It's dead file and will be removed.
No need to include <sys/sysctl.h> in this code context on NetBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296973
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Zachary Turner [Sat, 4 Mar 2017 16:42:25 +0000 (16:42 +0000)]
Truncate thread names if they're too long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296972
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Daniel Berlin [Sat, 4 Mar 2017 14:08:47 +0000 (14:08 +0000)]
DebugCounter: Initialize skip to 0, not -1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296971
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Sylvestre Ledru [Sat, 4 Mar 2017 14:01:38 +0000 (14:01 +0000)]
Fix a typo. Patch by fcrick on github https://github.com/llvm-mirror/llvm/pull/23
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296969
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Sylvestre Ledru [Sat, 4 Mar 2017 14:00:44 +0000 (14:00 +0000)]
Remove redundant code block and update comment.
By patch zoren here: https://github.com/llvm-mirror/llvm/pull/20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296968
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Sylvestre Ledru [Sat, 4 Mar 2017 13:56:11 +0000 (13:56 +0000)]
Fix a typo. Thanks to huangml. Reported here: https://github.com/llvm-mirror/llvm/pull/6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296967
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Simon Pilgrim [Sat, 4 Mar 2017 12:50:47 +0000 (12:50 +0000)]
[X86][SSE] Enable post-legalize vXi64 shuffle combining on 32-bit targets
Long ago (2010 according to svn blame), combineShuffle probably needed to prevent the accidental creation of illegal i64 types but there doesn't appear to be any combines that can cause this any more as they all have their own legality checks.
Differential Revision: https://reviews.llvm.org/D30213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296966
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Florian Hahn [Sat, 4 Mar 2017 12:00:35 +0000 (12:00 +0000)]
[legalize-types] Remove stale entries from SoftenedFloats.
Summary:
When replacing a SDValue, we should remove the replaced value from
SoftenedFloats (and possibly the other maps as well?).
When we revisit a Node because it needs analyzing again, we have to
remove all result values from SoftenedFloats (and possibly other maps?).
This fixes the fp128 test failures with expensive checks for X86.
I think we probably should also remove the values from the other maps
(PromotedIntegers and so on), let me know what you think.
Reviewers: baldrick, bogner, davidxl, ab, arsenm, pirama, chh, RKSimon
Reviewed By: chh
Subscribers: danalbert, wdng, srhines, hfinkel, sepavloff, llvm-commits
Differential Revision: https://reviews.llvm.org/D29265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296964
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Evgeny Stupachenko [Sat, 4 Mar 2017 05:20:02 +0000 (05:20 +0000)]
Add test missed in r296770.
Differential Revision: http://reviews.llvm.org/D27004
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296962
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Daniel Berlin [Sat, 4 Mar 2017 03:23:41 +0000 (03:23 +0000)]
Fix bug in bisect-skip-count not using passed-in arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296961
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Evgeny Stupachenko [Sat, 4 Mar 2017 03:14:05 +0000 (03:14 +0000)]
Set option enabling LSR alternative way to resolve complex solution to false.
Differential Revision: http://reviews.llvm.org/D29862
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296959
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Matthias Braun [Sat, 4 Mar 2017 01:40:40 +0000 (01:40 +0000)]
X86ISelLowering: Only perform copy elision on legal types.
This fixes cases where i1 types were not properly legalized yet and lead
to the creating of 0-sized stack slots.
This fixes http://llvm.org/PR32136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296950
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Peter Collingbourne [Sat, 4 Mar 2017 01:38:05 +0000 (01:38 +0000)]
Fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296949
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Peter Collingbourne [Sat, 4 Mar 2017 01:34:53 +0000 (01:34 +0000)]
WholeProgramDevirt: Implement exporting for uniform ret val opt.
Differential Revision: https://reviews.llvm.org/D29846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296948
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Peter Collingbourne [Sat, 4 Mar 2017 01:31:01 +0000 (01:31 +0000)]
WholeProgramDevirt: Implement exporting for single-impl devirtualization.
Differential Revision: https://reviews.llvm.org/D29811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296945
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Peter Collingbourne [Sat, 4 Mar 2017 01:23:30 +0000 (01:23 +0000)]
WholeProgramDevirt: Add any unsuccessful llvm.type.checked.load devirtualizations to the list of llvm.type.test users.
Any unsuccessful llvm.type.checked.load devirtualizations will be translated
into uses of llvm.type.test, so we need to add the resulting llvm.type.test
intrinsics to the function summaries so that the LowerTypeTests pass will
export them.
Differential Revision: https://reviews.llvm.org/D29808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296939
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Daniel Berlin [Sat, 4 Mar 2017 00:44:43 +0000 (00:44 +0000)]
NewGVN: Be consistent in what order we compare operands for swapping.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296935
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Eli Friedman [Sat, 4 Mar 2017 00:42:55 +0000 (00:42 +0000)]
[MISched] Remove unused arguments. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296934
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Sanjay Patel [Sat, 4 Mar 2017 00:18:31 +0000 (00:18 +0000)]
[x86] check for commuted add pattern to find ADC/SBB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296933
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Sanjay Patel [Sat, 4 Mar 2017 00:06:37 +0000 (00:06 +0000)]
[x86] add test to show failed recognition of commuted pattern; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296931
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Matthias Braun [Fri, 3 Mar 2017 23:27:20 +0000 (23:27 +0000)]
RegAllocGreedy: Follow-up to r296722
We can now end up in situations where we initiate LiveIntervalUnion
queries with different SubRanges against the same register unit, so the
assert() no longer holds in all cases. Just recalculate now when we know
the cache is out of date.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296928
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Hans Wennborg [Fri, 3 Mar 2017 23:19:31 +0000 (23:19 +0000)]
Revert r296865 "[ARM] fpscr read/write intrinsics not aware of each other"
It caused PR32134: "Cannot select: intrinsic %llvm.arm.get.fpscr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296926
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Tim Northover [Fri, 3 Mar 2017 23:05:47 +0000 (23:05 +0000)]
GlobalISel: constrain G_INSERT to inserting just one value per instruction.
It's much easier to reason about single-value inserts and no-one was actually
using the variadic variants before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296923
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Tim Northover [Fri, 3 Mar 2017 22:46:09 +0000 (22:46 +0000)]
GlobalISel: add merge/unmerge nodes for legalization.
These are simplified variants of the current G_SEQUENCE and G_EXTRACT, which
assume the individual parts will be contiguous, homogeneous, and occupy the
entirity of the larger register. This makes reasoning about them much easer
since you only have to look at the first register being merged and the result
to know what the instruction is doing.
I intend to gradually replace all uses of the more complicated sequence/extract
with these (or single-element insert/extracts), and then remove the older
variants. For now we start with legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296921
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Sanjay Patel [Fri, 3 Mar 2017 22:35:11 +0000 (22:35 +0000)]
[x86] refactor combineAddOrSubToADCOrSBB(); NFCI
The comments were wrong, and this is not an obvious transform.
This hopefully makes it clearer that we're missing the commuted
patterns for adds. It's less clear that this is actually a good
transform for all micro-arch.
This is prep work for trying to clean up the current adc/sbb
codegen because it's definitely not happening optimally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296918
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Krzysztof Parzyszek [Fri, 3 Mar 2017 22:21:02 +0000 (22:21 +0000)]
Silence a warning, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296917
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Rong Xu [Fri, 3 Mar 2017 21:56:34 +0000 (21:56 +0000)]
[PGO] Text format profile reader needs to clear the value profile
Summary:
Reset the ValueData for each function to avoid using the ones in
the previous function.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits, xur
Differential Revision: https://reviews.llvm.org/D30479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296916
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Krzysztof Parzyszek [Fri, 3 Mar 2017 21:53:12 +0000 (21:53 +0000)]
Detect the existence of pthread_{s,g}etname_np in libpthread on Linux
Older Linux distributions may not have those functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296915
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Zachary Turner [Fri, 3 Mar 2017 21:49:38 +0000 (21:49 +0000)]
Fix Threading path when LLVM_ENABLE_THREADS=0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296914
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Mehdi Amini [Fri, 3 Mar 2017 21:28:05 +0000 (21:28 +0000)]
un-Xfail Fuzzer test that decided to pass on Green Dragon
It may be flacky, I'll turn it into unsupported if it fails again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296913
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Peter Collingbourne [Fri, 3 Mar 2017 21:22:06 +0000 (21:22 +0000)]
MC: De-duplicate the object streamer implementations of EmitFileDirective into MCObjectStreamer. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296912
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Chris Bieneman [Fri, 3 Mar 2017 21:11:55 +0000 (21:11 +0000)]
[ObjectYAML] [DWARF] Abstract DWARF Initial Length values
In the DWARF 4 Spec section 7.2.2, data in many DWARF sections, and some DWARF structures start with "Initial Length Values", which are a 32-bit length, and an optional 64-bit length if the 32 bit value == UINT32_MAX.
This patch abstracts the Initial Length type in YAML, and extends its use to all the DWARF structures that are supported in the DWARFYAML code that have Initial Length values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296911
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Sanjay Patel [Fri, 3 Mar 2017 20:48:54 +0000 (20:48 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296908
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Peter Collingbourne [Fri, 3 Mar 2017 20:25:30 +0000 (20:25 +0000)]
LTO: Hash the set of imported symbols for each module.
This set may affect code generation and is sensitive to link order (and
possibly in the future to the linker's choice of prevailing symbol), so we
need to include it.
Differential Revision: https://reviews.llvm.org/D30586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296907
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Zachary Turner [Fri, 3 Mar 2017 20:21:59 +0000 (20:21 +0000)]
[Windows] Remove the #include <eh.h> hack.
Prior to MSVC 2015 we had to manually include this header any
time we were going to include <thread> or <future> due to a
bug in MSVC's STL implementation. This has been fixed in MSVC
for some time now, and we require VS 2015 minimum, so we can
remove this across all subprojects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296906
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Matthias Braun [Fri, 3 Mar 2017 19:05:34 +0000 (19:05 +0000)]
RegisterCoalescer: Simplify subrange splitting code; NFC
- Use slightly better variable names / compute in a more direct way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296905
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Zachary Turner [Fri, 3 Mar 2017 18:55:24 +0000 (18:55 +0000)]
Teach lit to expand glob expressions.
This will enable removing hacks throughout the codebase
in clang and compiler-rt that feed multiple inputs to a
testing utility by globbing, all of which are either disabled
on Windows currently or using xargs / find hacks.
Differential Revision: https://reviews.llvm.org/D30380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296904
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Sanjoy Das [Fri, 3 Mar 2017 18:53:09 +0000 (18:53 +0000)]
Fix a compiler warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296903
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Zachary Turner [Fri, 3 Mar 2017 18:38:22 +0000 (18:38 +0000)]
Add missing #includes for FreeBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296902
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Krzysztof Parzyszek [Fri, 3 Mar 2017 18:30:54 +0000 (18:30 +0000)]
Make TargetInstrInfo::isPredicable take a const reference, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296901
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Mike Aizatsky [Fri, 3 Mar 2017 18:22:20 +0000 (18:22 +0000)]
[sancov] better input parameters validation
Differential Revision: https://reviews.llvm.org/D30370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296900
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Zachary Turner [Fri, 3 Mar 2017 18:21:04 +0000 (18:21 +0000)]
Try again to appease the FreeBSD bot.
The actual logic was wrong, not just the type conversion.
This should get it correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296899
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Sanjoy Das [Fri, 3 Mar 2017 18:19:15 +0000 (18:19 +0000)]
[LoopUnrolling] Peel loops with invariant backedge Phi input
Summary:
If a loop contains a Phi node which has an invariant input from back
edge, it is profitable to peel such loops (rather than unroll them) to
use the advantage that this Phi is always invariant starting from 2nd
iteration. After the 1st iteration is peeled, other optimizations can
potentially simplify calculations with this invariant.
Patch by Max Kazantsev!
Reviewers: sanjoy, apilipenko, igor-laevsky, anna, mkuper, reames
Reviewed By: mkuper
Subscribers: mkuper, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D30161
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296898
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Sanjoy Das [Fri, 3 Mar 2017 18:19:10 +0000 (18:19 +0000)]
[LoopUnrolling] Re-prioritize Peeling and Partial unrolling
Summary:
In current implementation the loop peeling happens after trip-count based partial unrolling and may
sometimes not happen at all due to it (for example, if trip count is known, but UP.Partial = false). This
is generally bad, the more than there are some situations where peeling is profitable even if the partial
unrolling is disabled.
This patch is a NFC which reorders peeling and partial unrolling application and prepares the code for
implementation of the said optimizations.
Patch by Max Kazantsev!
Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper
Reviewed By: mkuper
Subscribers: mkuper, llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D30243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296897
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Sanjay Patel [Fri, 3 Mar 2017 17:58:39 +0000 (17:58 +0000)]
[x86] clean up materializeSBB(); NFCI
This is producing SBB where it is obviously not necessary, so it needs to be limited.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296894
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Zachary Turner [Fri, 3 Mar 2017 17:56:14 +0000 (17:56 +0000)]
Try to appease the FreeBSD bots.
pthread_self() returns a pthread_t, but we were setting it to
an int. It seems the cast to int when calling sysctl is still
the correct thing to do, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296892
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Zachary Turner [Fri, 3 Mar 2017 17:39:24 +0000 (17:39 +0000)]
Don't bring in llvm/Support/thread.h in Threading.cpp
Doing so defines the type llvm::thread. On FreeBSD, we need
to call a macro which references its own ::thread type, which
causes an ambiguity due to ADL when inside of the llvm namespace.
Since we don't even need this unless LLVM_ENABLE_THREADS == 1,
we don't even need this type anyway, as it is always equal to
std::thread, so we can just use that directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296891
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Zachary Turner [Fri, 3 Mar 2017 17:24:55 +0000 (17:24 +0000)]
Add #include for unistd.h on Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296890
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Zachary Turner [Fri, 3 Mar 2017 17:15:17 +0000 (17:15 +0000)]
[Support] Provide access to current thread name/thread id.
Applications often need the current thread id when making
system calls, and some operating systems provide the notion
of a thread name, which can be useful in enabling better
diagnostics when debugging or logging.
This patch adds an accessor for the thread id, and "best effort"
getters and setters for the thread name. Since this is
non critical functionality, no error is returned to indicate
that a platform doesn't support thread names.
Differential Revision: https://reviews.llvm.org/D30526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296887
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Simon Pilgrim [Fri, 3 Mar 2017 17:03:52 +0000 (17:03 +0000)]
Use APInt::setBits instead of OR'ing in a separate APInt::getBitsSet call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296886
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Sanjay Patel [Fri, 3 Mar 2017 16:58:51 +0000 (16:58 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296883
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Simon Pilgrim [Fri, 3 Mar 2017 16:56:33 +0000 (16:56 +0000)]
Use APInt::getLowBitsSet instead of APInt::getBitsSet for lower bit mask creation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296882
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 3 Mar 2017 16:45:57 +0000 (16:45 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296881
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 3 Mar 2017 16:42:43 +0000 (16:42 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296880
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 3 Mar 2017 16:35:57 +0000 (16:35 +0000)]
Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation
Avoids all the unnecessary extra bitrange creation/shift stages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296879
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 3 Mar 2017 16:34:35 +0000 (16:34 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296877
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 3 Mar 2017 15:17:41 +0000 (15:17 +0000)]
[x86] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296875
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 3 Mar 2017 14:37:57 +0000 (14:37 +0000)]
Use APInt::getHighBitsSet instead of APInt::getBitsSet for upper bit mask creation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296874
91177308-0d34-0410-b5e6-
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Dmitry Preobrazhensky [Fri, 3 Mar 2017 14:31:06 +0000 (14:31 +0000)]
[AMDGPU][MC] Fix for Bug 30829 + LIT tests
Added code to check constant bus restrictions for VOP formats (only one SGPR value or literal-constant may be used by the instruction).
Note that the same checks are performed by SIInstrInfo::verifyInstruction (used by lowering code).
Added LIT tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296873
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Fri, 3 Mar 2017 14:27:53 +0000 (14:27 +0000)]
Revert "Re-apply "[GVNHoist] Move GVNHoist to function simplification part of pipeline.""
This reverts commit r296759. Miscompiles bash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296872
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 3 Mar 2017 14:25:46 +0000 (14:25 +0000)]
Use APInt::getOneBitSet instead of APInt::getBitsSet for sign bit mask creation
Avoids all the unnecessary extra bitrange creation/shift stages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296871
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Fri, 3 Mar 2017 12:09:11 +0000 (12:09 +0000)]
Fix Wdocumentation warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296866
91177308-0d34-0410-b5e6-
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Ranjeet Singh [Fri, 3 Mar 2017 11:40:07 +0000 (11:40 +0000)]
[ARM] fpscr read/write intrinsics not aware of each other
The intrinsics __builtin_arm_get_fpscr and __builtin_arm_set_fpscr read and
write to the fpscr (Floating-Point Status and Control Register) register.
A bug exists in the __builtin_arm_get_fpscr intrinsic definition in llvm which
treats this intrinsic as a IntroNoMem which means it's not a memory access and
doesn't have any other side-effects. Having this property on this intrinsic
means that various optimizations can be done on this such as common
sub-expression elimination with other reads. This can cause issues if there has
been write to this register, e.g.
void foo(int *p) {
p[0] = __builtin_arm_get_fpscr();
__builtin_arm_set_fpscr(1);
p[1] = __builtin_arm_get_fpscr();
}
in the above example the second read is currently CSE'd into the first read,
this is because llvm isn't aware that the write done by __builtin_arm_set_fpscr
effects the same register that __builtin_arm_get_fpscr reads from, to fix this
problem I've removed the property IntrNoMem so that __builtin_arm_get_fpscr is
treated as a memory access.
Differential Revision: https://reviews.llvm.org/D30542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296865
91177308-0d34-0410-b5e6-
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Mohammad Shahid [Fri, 3 Mar 2017 10:02:47 +0000 (10:02 +0000)]
[SLP] Fixes the bug due to absence of in order uses of scalars which needs to be available
for VectorizeTree() API.This API uses it for proper mask computation to be used in shufflevector IR.
The fix is to compute the mask for out of order memory accesses while building the vectorizable tree
instead of actual vectorization of vectorizable tree.It also needs to recompute the proper Lane for
external use of vectorizable scalars based on shuffle mask.
Reviewers: mkuper
Differential Revision: https://reviews.llvm.org/D30159
Change-Id: Ide8773ce0ad3562f3cf4d1a0ad0f487e2f60ce5d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296863
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Chandler Carruth [Fri, 3 Mar 2017 10:02:25 +0000 (10:02 +0000)]
[SDAG] Revert r296476 (and r296486, r296668, r296690).
This patch causes compile times for some patterns to explode. I have
a (large, unreduced) test case that slows down by more than 20x and
several test cases slow down by 2x. I'm sending some of the test cases
directly to Nirav and following up with more details in the review log,
but this should unblock anyone else hitting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296862
91177308-0d34-0410-b5e6-
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Sylvestre Ledru [Fri, 3 Mar 2017 09:36:04 +0000 (09:36 +0000)]
Fix a typo in the comments. Patch by marktwtn from https://github.com/llvm-mirror/llvm/pull/16/files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296860
91177308-0d34-0410-b5e6-
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Amjad Aboud [Fri, 3 Mar 2017 09:03:24 +0000 (09:03 +0000)]
[X86] Generate VZEROUPPER for Skylake-avx512.
VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be.
Differential Revision: https://reviews.llvm.org/D29874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296859
91177308-0d34-0410-b5e6-
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Sjoerd Meijer [Fri, 3 Mar 2017 08:12:47 +0000 (08:12 +0000)]
[AArch64AsmParser] rewrite of function parseSysAlias
This is a cleanup/rewrite of the parseSysAlias function. It was not using the
tablegen instruction descriptions, but was “manually” matching the mnemonics
and recreating the operands whereas all this information is already in
tablegen; all this code has been replaced with calls to lookupXYZByName
tablegen calls.
Differential Revision: https://reviews.llvm.org/D30491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296857
91177308-0d34-0410-b5e6-
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Igor Breger [Fri, 3 Mar 2017 08:06:46 +0000 (08:06 +0000)]
[GlobalISel][X86] Support float/double and vector types.
Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector.
Reviewers: delena, zvi
Reviewed By: zvi
Subscribers: dberris, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30533
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296856
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Fri, 3 Mar 2017 02:00:22 +0000 (02:00 +0000)]
Revert r296730, "cmake: Configure the ThinLTO cache directory when using ELF lld or gold."
Causes a build failure on the clang-with-thin-lto-ubuntu bot.
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/2117/steps/build-stage3-compiler/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296850
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Fri, 3 Mar 2017 01:12:43 +0000 (01:12 +0000)]
[msan] Handle x86_sse_stmxcsr and x86_sse_ldmxcsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296848
91177308-0d34-0410-b5e6-
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Adrian Prantl [Fri, 3 Mar 2017 01:08:25 +0000 (01:08 +0000)]
LiveDebugValues: Assume calls never clobber SP.
A call should never modify the stack pointer, but some backends are
not so sure about this and never list SP in the regmask. For the
purposes of LiveDebugValues we assume a call never clobbers SP. We
already have a similar workaround in DbgValueHistoryCalculator (which
we hopefully can retire soon).
This fixes the availabilty of local ASANified variables on AArch64.
rdar://problem/
27757381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296847
91177308-0d34-0410-b5e6-
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Eugene Zelenko [Fri, 3 Mar 2017 01:07:34 +0000 (01:07 +0000)]
[ProfileData] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296846
91177308-0d34-0410-b5e6-
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Kyle Butt [Fri, 3 Mar 2017 01:00:22 +0000 (01:00 +0000)]
CodeGen: BlockPlacement: Precompute layout for chains of triangles.
For chains of triangles with small join blocks that can be tail duplicated, a
simple calculation of probabilities is insufficient. Tail duplication
can be profitable in 3 different ways for these cases:
1) The post-dominators marked 50% are actually taken 56% (This shrinks with
longer chains)
2) The chains are statically correlated. Branch probabilities have a very
U-shaped distribution.
[http://nrs.harvard.edu/urn-3:HUL.InstRepos:
24015805]
If the branches in a chain are likely to be from the same side of the
distribution as their predecessor, but are independent at runtime, this
transformation is profitable. (Because the cost of being wrong is a small
fixed cost, unlike the standard triangle layout where the cost of being
wrong scales with the # of triangles.)
3) The chains are dynamically correlated. If the probability that a previous
branch was taken positively influences whether the next branch will be
taken
We believe that 2 and 3 are common enough to justify the small margin in 1.
The code pre-scans a function's CFG to identify this pattern and marks the edges
so that the standard layout algorithm can use the computed results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296845
91177308-0d34-0410-b5e6-
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Evgeniy Stepanov [Fri, 3 Mar 2017 00:25:56 +0000 (00:25 +0000)]
[msan] Remove stale comments.
ClStoreCleanOrigin flag was removed back in 2014.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296844
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 2 Mar 2017 23:50:51 +0000 (23:50 +0000)]
AMDGPU: Fix missing dominator tree dependency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296842
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Thu, 2 Mar 2017 23:10:17 +0000 (23:10 +0000)]
ThinLTOBitcodeWriter: Do not follow operand edges of type GlobalValue when looking for virtual functions.
Such edges may otherwise result in infinite recursion if a pointer to a vtable
is reachable from the vtable itself. This can happen in practice if a TU
defines the ABI types used to implement RTTI, and is itself compiled with RTTI.
Fixes PR32121.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296839
91177308-0d34-0410-b5e6-
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Daniel Berlin [Thu, 2 Mar 2017 23:06:46 +0000 (23:06 +0000)]
Move defClobbersUseOrDef to being a protected member of a class since we don't want anyone else using it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296838
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Nikolai Bozhenov [Thu, 2 Mar 2017 22:12:15 +0000 (22:12 +0000)]
[BypassSlowDivision] Use ValueTracking to simplify run-time checks
ValueTracking is used for more thorough analysis of operands. Based on the
analysis, either run-time checks can be simplified (e.g. check only one operand
instead of two) or the transformation can be avoided. For example, it is quite
often the case that a divisor is promoted from a shorter type and run-time
checks for it are redundant.
With additional compile-time analysis of values, two special cases naturally
arise and are addressed by the patch:
1) Both operands are known to be short enough. Then, the long division can be
simply replaced with a short one without CFG modification.
2) If a division is unsigned and the dividend is known to be short then the
long division is not needed at all. Because if the divisor is too big for
short division then the quotient is obviously zero (and the remainder is
equal to the dividend). Actually, the division is not needed when
(divisor > dividend).
Differential Revision: https://reviews.llvm.org/D29897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296832
91177308-0d34-0410-b5e6-
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Tom Stellard [Thu, 2 Mar 2017 22:05:13 +0000 (22:05 +0000)]
CMake: Clean up VersionFromVCS.cmake
Summary:
Fix a few problems in VersionFromVCS.cmake to make it more reliable:
- Stop using git svn info to retrieve the svn revision. I am unable to
determine what the svn revision returned by this command means.
During my testing this command returned a revision from a month
ago which was not the HEAD of any of my local branches.
Also, this revision was never actually added to the version string due
to a typo in the script. All it was used for was to reject the
revision number returned by git svn find-rev HEAD when the revision
numbers didn't match.
- Populate GIT_COMMIT even when we detect a git repo without any
svn information.
Reviewers: mehdi_amini, beanz
Reviewed By: beanz
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D30092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296829
91177308-0d34-0410-b5e6-
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Nikolai Bozhenov [Thu, 2 Mar 2017 22:05:07 +0000 (22:05 +0000)]
[BypassSlowDivision] Refactor fast division insertion logic (NFC)
The most important goal of the patch is to break large insertFastDiv function
into separate pieces, so that later a different fast insertion logic can be
implemented using some of these pieces.
Differential Revision: https://reviews.llvm.org/D29896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296828
91177308-0d34-0410-b5e6-
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Taewook Oh [Thu, 2 Mar 2017 21:58:35 +0000 (21:58 +0000)]
[DAGCombiner] Fix DebugLoc propagation when folding !(x cc y) -> (x !cc y)
Summary:
Currently, when 't1: i1 = setcc t2, t3, cc' followed by 't4: i1 = xor t1, Constant:i1<-1>' is folded into 't5: i1 = setcc t2, t3 !cc', SDLoc of newly created SDValue 't5' follows SDLoc of 't4', not 't1'. However, as the opcode of newly created SDValue is 'setcc', it make more sense to take DebugLoc from 't1' than 't4'. For the code below
```
extern int bar();
extern int baz();
int foo(int x, int y) {
if (x != y)
return bar();
else
return baz();
}
```
, following is the bitcode representation of 'foo' at the end of llvm-ir level optimization:
```
define i32 @foo(i32 %x, i32 %y) !dbg !4 {
entry:
tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !11), !dbg !12
tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !10, metadata !11), !dbg !13
%cmp = icmp ne i32 %x, %y, !dbg !14
br i1 %cmp, label %if.then, label %if.else, !dbg !16
if.then: ; preds = %entry
%call = tail call i32 (...) @bar() #3, !dbg !17
br label %return, !dbg !18
if.else: ; preds = %entry
%call1 = tail call i32 (...) @baz() #3, !dbg !19
br label %return, !dbg !20
return: ; preds = %if.else, %if.then
%retval.0 = phi i32 [ %call, %if.then ], [ %call1, %if.else ]
ret i32 %retval.0, !dbg !21
}
!14 = !DILocation(line: 5, column: 9, scope: !15)
!16 = !DILocation(line: 5, column: 7, scope: !4)
```
As you can see, in 'entry' block, 'icmp' instruction and 'br' instruction have different debug locations. However, with current implementation, there's no distinction between debug locations of these two when they are lowered to asm instructions. This is because 'icmp' and 'br' become 'setcc' 'xor' and 'brcond' in SelectionDAG, where SDLoc of 'setcc' follows the debug location of 'icmp' but SDLOC of 'xor' and 'brcond' follows the debug location of 'br' instruction, and SDLoc of 'xor' overwrites SDLoc of 'setcc' when they are folded. This patch addresses this issue.
Reviewers: atrick, bogner, andreadb, craig.topper, aprantl
Reviewed By: andreadb
Subscribers: jlebar, mkuper, jholewinski, andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D29813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296825
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Sanjay Patel [Thu, 2 Mar 2017 21:56:43 +0000 (21:56 +0000)]
[DAG] early exit to improve readability and formatting of visitMemCmpCall(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296824
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Thu, 2 Mar 2017 21:49:49 +0000 (21:49 +0000)]
[Hexagon] Pick the right branch opcode depending on branch probabilities
Specifically, pick the opcode with the correct branch prediction, i.e.
jump:t or jump:nt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296821
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Tobias Grosser [Thu, 2 Mar 2017 21:47:51 +0000 (21:47 +0000)]
Revert "AMDGPU: Re-do update for branch-relaxation test"
This commit also relied on r296812, which I just reverted. We should probably
apply it again, after the r296812 has been discussed and been reapplied in some
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296820
91177308-0d34-0410-b5e6-
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Kyle Butt [Thu, 2 Mar 2017 21:44:24 +0000 (21:44 +0000)]
CodeGen: MachineBlockPlacement: Remove the unused outlining heuristic.
Outlining optional branches isn't a good heuristic, and it's never been
on by default. Remove it to clean things up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296818
91177308-0d34-0410-b5e6-
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Eli Friedman [Thu, 2 Mar 2017 21:39:39 +0000 (21:39 +0000)]
[ARM] Fix insert point for store rescheduling.
In ARMPreAllocLoadStoreOpt::RescheduleOps, LastOp should be the last
operation which we want to merge. If we break out of the loop because
an operation has the wrong offset, we shouldn't use that operation
as LastOp.
This patch fixes some cases where we would move stores to the wrong
insert point.
Re-commit with a fix to increment NumMove in the right place.
Differential Revision: https://reviews.llvm.org/D30124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296815
91177308-0d34-0410-b5e6-
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Tobias Grosser [Thu, 2 Mar 2017 21:08:37 +0000 (21:08 +0000)]
Revert "Fix PR 24415 (at least), by making our post-dominator tree behavior sane."
and also "clang-format GenericDomTreeConstruction.h, since the current
formatting makes it look like their is a bug in the loop indentation, and there
is not"
This reverts commit r296535.
There are still some open design questions which I would like to discuss. I
revert this for Daniel (who gave the OK), as he is on vacation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296812
91177308-0d34-0410-b5e6-
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Guozhi Wei [Thu, 2 Mar 2017 21:07:59 +0000 (21:07 +0000)]
[PPC] Fix code generation for bswap(int32) followed by store16
This patch fixes pr32063.
Current code in PPCTargetLowering::PerformDAGCombine can transform
bswap
store
into a single PPCISD::STBRX instruction. but it doesn't consider the case that the operand size of bswap may be larger than store size. When it occurs, we need 2 modifications,
1 For the last operand of PPCISD::STBRX, we should not use DAG.getValueType(N->getOperand(1).getValueType()), instead we should use cast<StoreSDNode>(N)->getMemoryVT().
2 Before PPCISD::STBRX, we need to shift the original operand of bswap to the right side.
Differential Revision: https://reviews.llvm.org/D30362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296811
91177308-0d34-0410-b5e6-
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Zachary Turner [Thu, 2 Mar 2017 20:52:51 +0000 (20:52 +0000)]
[Support] Move Stream library from MSF -> Support.
After several smaller patches to get most of the core improvements
finished up, this patch is a straight move and header fixup of
the source.
Differential Revision: https://reviews.llvm.org/D30266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296810
91177308-0d34-0410-b5e6-
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Chad Rosier [Thu, 2 Mar 2017 20:48:11 +0000 (20:48 +0000)]
[AArch64] Extend redundant copy elimination pass to handle non-zero stores.
This patch extends the current functionality of the AArch64 redundant copy
elimination pass to handle non-zero cases such as:
BB#0:
cmp x0, #1
b.eq .LBB0_1
.LBB0_1:
orr x0, xzr, #0x1 ; <-- redundant copy; x0 known to hold #1.
Differential Revision: https://reviews.llvm.org/D29344
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296809
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 2 Mar 2017 20:48:08 +0000 (20:48 +0000)]
[DAG] improve documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296808
91177308-0d34-0410-b5e6-
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Vadzim Dambrouski [Thu, 2 Mar 2017 20:25:10 +0000 (20:25 +0000)]
[MSP430] Add SRet support to MSP430 target
This patch adds support for struct return values to the MSP430
target backend. It also reverses the order of argument and return
registers in the calling convention to bring it into closer
alignment with the published EABI from TI.
Patch by Andrew Wygle (awygle).
Differential Revision: https://reviews.llvm.org/D29069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296807
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Evgeny Stupachenko [Thu, 2 Mar 2017 19:41:38 +0000 (19:41 +0000)]
The patch fixes r296770
Summary:
Extend -unroll-partial-threshold to 200 for runtime-loop3.ll test
as epilogue unroll initially add 1 more IV to the loop.
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296803
91177308-0d34-0410-b5e6-
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Artem Belevich [Thu, 2 Mar 2017 19:14:14 +0000 (19:14 +0000)]
[NVPTX] Reduce amount of boilerplate code used to select load instruction opcode.
Make opcode selection code for the load instruction a bit easier
to read and maintain.
This patch also catches number of f16 load/store variants that were
not handled before.
Differential Revision: https://reviews.llvm.org/D30513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296785
91177308-0d34-0410-b5e6-
96231b3b80d8
Artem Belevich [Thu, 2 Mar 2017 19:14:10 +0000 (19:14 +0000)]
[NVPTX] Added missing LDU/LDG intrinsics for f16.
Differential Revision: https://reviews.llvm.org/D30512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296784
91177308-0d34-0410-b5e6-
96231b3b80d8