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Simon Pilgrim [Tue, 13 Nov 2018 11:28:46 +0000 (11:28 +0000)]
Add bracket that was lost in rL346727 and has been causing buildbot failures for some time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346752
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Alexander Richardson [Tue, 13 Nov 2018 10:54:49 +0000 (10:54 +0000)]
Fix .cfi_restore with register numbers > 64
Summary:
DW_CFA_restore can only encode register numbers up to 64 (6 bits unsigned
int). For regsiter numbers > 64 we have to use DW_CFA_restore_extended
instead which uses a ULEB128 value.
I discovered this problem in the out-of-tree CHERI target since we use
DWARF register number 89 for our return capability register.
Reviewers: probinson, dblaikie, aprantl, espindola
Reviewed By: dblaikie
Subscribers: JohnReagan, emaste, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D54420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346751
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Alexander Richardson [Tue, 13 Nov 2018 10:54:44 +0000 (10:54 +0000)]
Fix modules build of AVRAsmParser.cpp
Summary:
Without this change I get the following error:
lib/Target/AVR/AVRGenAsmMatcher.inc:1135:1: error: redundant #include of module 'LLVM_Utils.Support.Format' appears within namespace 'llvm' [-Wmodules-import-nested-redundant]
Reviewers: dylanmckay
Reviewed By: dylanmckay
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346750
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Jonas Paulsson [Tue, 13 Nov 2018 08:37:09 +0000 (08:37 +0000)]
[SystemZ] Increase the number of VLREPs
If a loaded value is replicated it is best to combine these two operations
into a VLREP (load and replicate), but isel will not produce this if the load
has other users as well.
This patch handles this by putting the other users of the load to use the
REPLICATE 0-element instead of the load. This way the load has only the
REPLICATE node as user, and we get a VLREP.
Review: Ulrich Weigand
https://reviews.llvm.org/D54264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346746
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Craig Topper [Tue, 13 Nov 2018 07:47:52 +0000 (07:47 +0000)]
[X86] Add more tests for -x86-experimental-vector-widening-legalization
I'm looking into whether we can make this the default legalization strategy. Adding these tests to help cover the changes that will be necessary.
This patch adds copies of some tests with the command line switch enabled. By making copies its easier to compare the two legalization strategies.
I've also removed RUN lines from some of these tests that already had -x86-experimental-vector-widening-legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346745
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Fedor Sergeev [Tue, 13 Nov 2018 05:47:01 +0000 (05:47 +0000)]
[FileCheck] fixing docs buildbot - use proper code-block type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346740
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George Karpenkov [Tue, 13 Nov 2018 02:59:27 +0000 (02:59 +0000)]
[BuildingAJIT] Fixing the build by inserting a forgotten paren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346730
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Xing GUO [Tue, 13 Nov 2018 02:14:38 +0000 (02:14 +0000)]
[commit test] Add blank line to test/tools/llvm-objdump/full-contents.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346729
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Craig Topper [Tue, 13 Nov 2018 01:59:32 +0000 (01:59 +0000)]
[DAGCombiner] Enable tryToFoldExtendOfConstant to run after legalize vector ops
It should be ok to create a new build_vector after legal operations so long as it doesn't cause an infinite loop in DAG combiner.
Unfortunately, X86's custom constant folding in combineVSZext is hiding any test changes from this. But I'm trying to get to a point where that X86 specific code isn't necessary at all.
Differential Revision: https://reviews.llvm.org/D54285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346728
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Lang Hames [Tue, 13 Nov 2018 01:26:25 +0000 (01:26 +0000)]
[BuildingAJIT] Clang-format chapters 1 and 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346727
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Lang Hames [Tue, 13 Nov 2018 01:25:34 +0000 (01:25 +0000)]
[BuildingAJIT] Update chapter 2 to use the ORCv2 APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346726
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Fedor Sergeev [Tue, 13 Nov 2018 01:12:19 +0000 (01:12 +0000)]
[FileCheck] fixing small formatting error in docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346725
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Jake Ehrlich [Tue, 13 Nov 2018 01:10:35 +0000 (01:10 +0000)]
[libObject] Fix getDesc for Elf_Note_Impl
This change fixes a bug in Elf_Note_Impl in which Elf_Word was used
where uint8_t should have been used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346724
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Fedor Sergeev [Tue, 13 Nov 2018 01:09:53 +0000 (01:09 +0000)]
[FileCheck] fixing typo in assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346723
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Fedor Sergeev [Tue, 13 Nov 2018 00:46:13 +0000 (00:46 +0000)]
[FileCheck] introduce CHECK-COUNT-<num> repetition directive
In some cases it is desirable to match the same pattern repeatedly
many times. Currently the only way to do it is to copy the same
check pattern as many times as needed. And that gets pretty unwieldy
when its more than count is big.
Introducing CHECK-COUNT-<num> directive which acts like a plain CHECK
directive yet matches the same pattern exactly <num> times.
Extended FileCheckType to a struct to add Count there.
Changed some parsing routines to handle non-fixed length of directive
(all currently existing directives were fixed-length).
The code is generic enough to allow future support for COUNT in more
than just PlainCheck directives.
See motivating example for this feature in reviews.llvm.org/D54223.
Reviewed By: chandlerc, dblaikie
Differential Revision: https://reviews.llvm.org/D54336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346722
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Jessica Paquette [Tue, 13 Nov 2018 00:32:09 +0000 (00:32 +0000)]
[MachineOutliner][NFC] Simplify isMBBSafeToOutlineFrom check in AArch64 outliner
Turns out it's way simpler to do this check with one LRU. Instead of
maintaining two, just keep one. Check if each of the registers is available,
and then check if it's a live out from the block. If it's a live out, but
available in the block, we know we're in an unsafe case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346721
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Zhizhou Yang [Tue, 13 Nov 2018 00:31:22 +0000 (00:31 +0000)]
Introduce DebugCounter into ConstProp pass
Summary:
This patch introduces DebugCounter into ConstProp pass at per-transformation level.
It will provide an option to skip first n or stop after n transformations for the whole ConstProp pass.
This will make debug easier for the pass, also providing chance to do transformation level bisecting.
Reviewers: davide, fhahn
Reviewed By: fhahn
Subscribers: llozano, george.burgess.iv, llvm-commits
Differential Revision: https://reviews.llvm.org/D50094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346720
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Sanjay Patel [Mon, 12 Nov 2018 23:58:59 +0000 (23:58 +0000)]
[InstCombine] add rotate variants that include select; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346719
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Jessica Paquette [Mon, 12 Nov 2018 23:51:32 +0000 (23:51 +0000)]
[MachineOutliner][NFC] Change getMachineOutlinerMBBFlags to isMBBSafeToOutlineFrom
Instead of returning Flags, return true if the MBB is safe to outline from.
This lets us check for unsafe situations, like say, in AArch64, X17 is live
across a MBB without being defined in that MBB. In that case, there's no point
in performing an instruction mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346718
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Fangrui Song [Mon, 12 Nov 2018 23:46:22 +0000 (23:46 +0000)]
[llvm-objcopy] Don't copy Config when processing --keep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346717
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Sanjay Patel [Mon, 12 Nov 2018 22:52:25 +0000 (22:52 +0000)]
[InstCombine] narrow width of rotate patterns, part 3
This is a longer variant for the pattern handled in
rL346713
This one includes zexts.
Eventually, we should canonicalize all rotate patterns
to the funnel shift intrinsics, but we need a bit more
infrastructure to make sure the vectorizers handle those
intrinsics as well as the shift+logic ops.
https://rise4fun.com/Alive/FMn
Name: narrow rotateright
%neg = sub i8 0, %shamt
%rshamt = and i8 %shamt, 7
%rshamtconv = zext i8 %rshamt to i32
%lshamt = and i8 %neg, 7
%lshamtconv = zext i8 %lshamt to i32
%conv = zext i8 %x to i32
%shr = lshr i32 %conv, %rshamtconv
%shl = shl i32 %conv, %lshamtconv
%or = or i32 %shl, %shr
%r = trunc i32 %or to i8
=>
%maskedShAmt2 = and i8 %shamt, 7
%negShAmt2 = sub i8 0, %shamt
%maskedNegShAmt2 = and i8 %negShAmt2, 7
%shl2 = lshr i8 %x, %maskedShAmt2
%shr2 = shl i8 %x, %maskedNegShAmt2
%r = or i8 %shl2, %shr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346716
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Simon Atanasyan [Mon, 12 Nov 2018 22:43:17 +0000 (22:43 +0000)]
[DWARF] Do not use PRIx32 for printing uint64_t values
The `DWARFDebugAddrTable::dump` routine prints 32/64-bits addresses.
These values are stored in a vector of `uint64_t` independently of their
original sizes. But `format` function gets format string with PRIx32
suffix in case of 32-bit address size. At least on MIPS 32-bit targets
that leads to incorrect output.
This patch changes formats strings and always use PRIx64 to print
`uint64_t` values.
Differential Revision: http://reviews.llvm.org/D54424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346715
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Sanjay Patel [Mon, 12 Nov 2018 22:11:09 +0000 (22:11 +0000)]
[InstCombine] narrow width of rotate patterns, part 2 (PR39624)
The sub-pattern for the shift amount in a rotate can take on
several different forms, and there's apparently no way to
canonicalize those without seeing the entire rotate sequence.
This is the form noted in:
https://bugs.llvm.org/show_bug.cgi?id=39624
https://rise4fun.com/Alive/qnT
%zx = zext i8 %x to i32
%maskedShAmt = and i32 %shAmt, 7
%shl = shl i32 %zx, %maskedShAmt
%negShAmt = sub i32 0, %shAmt
%maskedNegShAmt = and i32 %negShAmt, 7
%shr = lshr i32 %zx, %maskedNegShAmt
%rot = or i32 %shl, %shr
%r = trunc i32 %rot to i8
=>
%truncShAmt = trunc i32 %shAmt to i8
%maskedShAmt2 = and i8 %truncShAmt, 7
%shl2 = shl i8 %x, %maskedShAmt2
%negShAmt2 = sub i8 0, %truncShAmt
%maskedNegShAmt2 = and i8 %negShAmt2, 7
%shr2 = lshr i8 %x, %maskedNegShAmt2
%r = or i8 %shl2, %shr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346713
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Philip Reames [Mon, 12 Nov 2018 22:03:53 +0000 (22:03 +0000)]
[GC][NFC] Simplify code now that we only have one safepoint kind
This is the NFC follow up to exploit the semantic simplification from r346701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346712
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Sanjay Patel [Mon, 12 Nov 2018 22:00:00 +0000 (22:00 +0000)]
[InstCombine] refactor code for matching shift amount of a rotate; NFC
As shown in existing test cases and with:
https://bugs.llvm.org/show_bug.cgi?id=39624
...we're missing at least 2 more patterns for rotate narrowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346711
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Ali Tamur [Mon, 12 Nov 2018 21:43:43 +0000 (21:43 +0000)]
Use a data structure better suited for large sets in SimplificationTracker.
Summary:
D44571 changed SimplificationTracker to use SmallSetVector to keep phi nodes. As a result, when the number of phi nodes is large, the build time performance suffers badly. When building for power pc, we have a case where there are more than 600.000 nodes, and it takes too long to compile.
In this change, I partially revert D44571 to use SmallPtrSet, which does an acceptable job with any number of elements. In the original patch, having a deterministic iteration order was mentioned as a motivation, however I think it only applies to the nodes already matched in MatchPhiSet method, which I did not touch.
Reviewers: bjope, skatkov
Reviewed By: bjope, skatkov
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346710
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Simon Pilgrim [Mon, 12 Nov 2018 21:12:38 +0000 (21:12 +0000)]
[X86][SSE] Add lowerVectorShuffleAsByteRotateAndPermute (PR39387)
This patch adds the ability to use a PALIGNR to rotate a pair of inputs to select a range containing all the referenced elements, followed by a single input permute to put them in the right location.
Differential Revision: https://reviews.llvm.org/D54267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346706
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Aakanksha Patil [Mon, 12 Nov 2018 21:04:06 +0000 (21:04 +0000)]
AMDGPU: Adding more median3 patterns
min(max(a, b), max(min(a, b), c)) -> med3 a, b, c
Differential Revision: https://reviews.llvm.org/D54331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346704
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Sanjay Patel [Mon, 12 Nov 2018 20:32:59 +0000 (20:32 +0000)]
[InstCombine] add more tests for rotate narrowing; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346703
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Philip Reames [Mon, 12 Nov 2018 20:30:50 +0000 (20:30 +0000)]
[GC docs] Update the gcroot documentation to reflect recent simplifcations to GCStrategy configurability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346702
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Philip Reames [Mon, 12 Nov 2018 20:15:34 +0000 (20:15 +0000)]
[GC] Remove so called PreCall safepoints
Remove another bit of unused configuration potential from GCStrategy. It's not entirely clear what the intention here was, but from the docs, it sounds like this may have been subsumed by patchable call support.
Note: This change is deliberately small to make it clear that while implemented, there's nothing using the option. A following NFC will do most of the simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346701
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Wouter van Oortmerssen [Mon, 12 Nov 2018 20:15:01 +0000 (20:15 +0000)]
[WebAssembly] Added WasmAsmParser.
Summary:
This is to replace the ELFAsmParser that WebAssembly was using, which
so far was a stub that didn't do anything, and couldn't work correctly
with wasm.
This new class is there to implement generic directives related to
wasm as a binary format. Wasm target specific directives are still
parsed in WebAssemblyAsmParser as before. The two classes now
cooperate more correctly too.
Also implemented .result which was missing. Any unknown directives
will now result in errors.
Reviewers: dschuff, sbc100
Subscribers: mgorny, jgravelle-google, eraman, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346700
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Philip Reames [Mon, 12 Nov 2018 20:00:53 +0000 (20:00 +0000)]
[GC][InstCombine] Fix a potential iteration issue
Noticed via inspection. Appears to be largely innocious in practice, but slight code change could have resulted in either visit order dependent missed optimizations or infinite loops. May be a minor compile time problem today.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346698
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Craig Topper [Mon, 12 Nov 2018 19:37:29 +0000 (19:37 +0000)]
[X86] In LowerMULH, use generic truncate and vector shuffle nodes instead of directly emitting PACKUS.
Truncate and shuffle lowering are already capable of matching to PACKUS using known bits analysis.
This features one test change where we now prefer to extend v16i16->v16i32 then trunc v16i32->v16i8 over extract_subvector+packus when avx512f is available, but avx512bw is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346697
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David Blaikie [Mon, 12 Nov 2018 18:53:28 +0000 (18:53 +0000)]
NFC: DebugInfo: Reduce scope of DebugOffset to simplify code
This was being used as a sort of indirect out parameter from shouldDump
- seems simpler to use it as the actual result of the call. (this does
mean using a pointer to an Optional & actually using all 3 states (null,
None, and present) which is, admittedly, a tad subtle - but given the
limited scope, seems OK to me - open to discussion though, if others
feel strongly about it)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346691
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Stanislav Mekhanoshin [Mon, 12 Nov 2018 18:48:17 +0000 (18:48 +0000)]
[AMDGPU] Optimize S_CBRANCH_VCC[N]Z -> S_CBRANCH_EXEC[N]Z
Sometimes after basic block placement we end up with a code like:
sreg = s_mov_b64 -1
vcc = s_and_b64 exec, sreg
s_cbranch_vccz
This happens as a join of a block assigning -1 to a saved mask and
another block which consumes that saved mask with s_and_b64 and a
branch.
This is essentially a single s_cbranch_execz instruction when moved
into a single new basic block.
Differential Revision: https://reviews.llvm.org/D54164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346690
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Sanjay Patel [Mon, 12 Nov 2018 18:41:08 +0000 (18:41 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346689
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Simon Pilgrim [Mon, 12 Nov 2018 18:27:54 +0000 (18:27 +0000)]
[CostModel][X86] Add funnel shift rotation special case costs
When we repeat the 2 shifting operands then this is a bit rotation - annoyingly this has to be done in the other getIntrinsicInstrCost than most intrinsics as we need to check the operands are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346688
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Stanislav Mekhanoshin [Mon, 12 Nov 2018 18:12:28 +0000 (18:12 +0000)]
Fix MachineInstr::findRegisterUseOperandIdx subreg checks
The function only checks that instruction reads a super-register
containing requested physical register. In case if a sub-register
if being read that is also a use of a super-reg, so added the check.
In particular MI->readsRegister() is broken because of the missing
check. The resulting check is essentially regsOverlap().
Differential Revision: https://reviews.llvm.org/D54128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346686
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Jordan Rupprecht [Mon, 12 Nov 2018 18:02:38 +0000 (18:02 +0000)]
[llvm-readelf] Make llvm-readelf more compatible with GNU readelf.
Summary:
This change adds a bunch of options that GNU readelf supports. There is one breaking change when invoked as `llvm-readobj`, and three breaking changes when invoked as `llvm-readelf`:
- Add --all (implies --file-header, --program-headers, etc.)
- [Breaking] -a is --all instead of --arm-attributes
- Add --file-header as an alias for --file-headers
- Replace --sections with --sections-headers, keeping --sections as an alias for it
- Add --relocs as an alias for --relocations
- Add --dynamic as an alias for --dynamic-table
- Add --segments as an alias for --program-headers
- Add --section-groups as an alias for --elf-section-groups
- Add --dyn-syms as an alias for --dyn-symbols
- Add --syms as an alias for --symbols
- Add --histogram as an alias for --elf-hash-histogram
- [Breaking] When invoked as `llvm-readelf`, -s is --symbols instead of --sections
- [Breaking] When invoked as `llvm-readelf`, -t is no longer an alias for --symbols
Reviewers: MaskRay, phosek, mcgrathr, jhenderson
Reviewed By: MaskRay, jhenderson
Subscribers: sbc100, aheejin, edd, jhenderson, silvas, echristo, compnerd, kristina, javed.absar, kristof.beyls, llvm-commits, Bigcheese
Differential Revision: https://reviews.llvm.org/D54124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346685
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Simon Pilgrim [Mon, 12 Nov 2018 17:56:59 +0000 (17:56 +0000)]
[CostModel][X86] Add SHLD/SHRD scalar funnel shift costs
The costs match the typical reg-reg cases - the RMW case can be a lot slower but we don't model that at this level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346683
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Jessica Paquette [Mon, 12 Nov 2018 17:50:56 +0000 (17:50 +0000)]
[MachineOutliner][NFC] Early exit pruning when candidates don't share an MBB
There's no way they can overlap in this case.
This can save a few iterations when the candidate is close to the beginning
of a MachineBasicBlock. It's particularly useful when the average length of
a MachineBasicBlock in the program is small.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346682
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Jessica Paquette [Mon, 12 Nov 2018 17:50:55 +0000 (17:50 +0000)]
[MachineOutliner][NFC] Put suffix tree in buildCandidateList
It's only used there, so it doesn't make much sense to have it in runOnModule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346681
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Paul Robinson [Mon, 12 Nov 2018 16:55:11 +0000 (16:55 +0000)]
[DWARFv5] Emit split type units in .debug_info.dwo.
Differential Revision: https://reviews.llvm.org/D54350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346674
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Simon Pilgrim [Mon, 12 Nov 2018 16:39:41 +0000 (16:39 +0000)]
[CostModel][X86] Add some initial cost tests for funnel shifts
Still need to add full uniform/constant coverage but this is enough to check basic fshl/fshr cost handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346670
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Simon Pilgrim [Mon, 12 Nov 2018 15:48:06 +0000 (15:48 +0000)]
[CostModel][X86] SK_ExtractSubvector is cheap if the (legal) subvector is aligned within the source vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346664
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Jonas Paulsson [Mon, 12 Nov 2018 15:32:27 +0000 (15:32 +0000)]
[SystemZ::TTI] Improve accuracy of costs for vector fp <-> int conversions
Improve getCastInstrCost() by respecting the different types of Src and Dst
for vector integer <-> fp conversions.
This means that extracting from integer becomes more expensive (by the
extraction penalty), and the extraction from fp becomes cheaper (no longer
has a false extraction penalty).
Review: Ulrich Weigand
https://reviews.llvm.org/D54423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346663
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Simon Pilgrim [Mon, 12 Nov 2018 15:20:24 +0000 (15:20 +0000)]
[CostModel] Add more realistic SK_InsertSubvector generic costs.
Instead of defaulting to a cost = 1, expand to element extract/insert like we do for other shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346662
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Sanjay Patel [Mon, 12 Nov 2018 15:20:14 +0000 (15:20 +0000)]
[VectorUtils] add funnel-shifts to the list of vectorizable intrinsics
This just identifies the intrinsics as candidates for vectorization.
It does not mean we will attempt to vectorize under normal conditions
(the test file is forcing vectorization).
The cost model must be fixed to show that the transform is profitable
in general.
Allowing vectorization with these intrinsics is required to avoid
potential regressions from canonicalizing to the intrinsics from
generic IR:
https://bugs.llvm.org/show_bug.cgi?id=37417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346661
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Sanjay Patel [Mon, 12 Nov 2018 15:10:30 +0000 (15:10 +0000)]
[VectorUtils] reorder list of vectorizable intrinsics; NFC
We need to add funnel-shifts to this list, so clean up
the random order before it gets worse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346660
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Sanjay Patel [Mon, 12 Nov 2018 14:52:01 +0000 (14:52 +0000)]
[LoopVectorize] add tests for funnel shifts; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346658
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 12 Nov 2018 14:48:39 +0000 (14:48 +0000)]
Fix unused variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346657
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 12 Nov 2018 14:25:23 +0000 (14:25 +0000)]
[CostModel] Add more realistic SK_ExtractSubvector generic costs.
Instead of defaulting to a cost = 1, expand to element extract/insert like we do for other shuffles.
This exposes an issue in LoopVectorize which could call SK_ExtractSubvector with a scalar subvector type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346656
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Alex Bradbury [Mon, 12 Nov 2018 14:25:07 +0000 (14:25 +0000)]
[RISCV] Support .option relax and .option norelax
This extends the .option support from D45864 to enable/disable the relax
feature flag from D44886
During parsing of the relax/norelax directives, the RISCV::FeatureRelax
feature bits of the SubtargetInfo stored in the AsmParser are updated
appropriately to reflect whether relaxation is currently enabled in the
parser. When an instruction is parsed, the parser checks if relaxation is
currently enabled and if so, gets a handle to the AsmBackend and sets the
ForceRelocs flag. The AsmBackend uses a combination of the original
RISCV::FeatureRelax feature bits set by e.g -mattr=+/-relax and the
ForceRelocs flag to determine whether to emit relocations for symbol and
branch diffs. Diff relocations should therefore only not be emitted if the
relax flag was not set on the command line and no instruction was ever parsed
in a section with relaxation enabled to ensure correct diffs are emitted.
Differential Revision: https://reviews.llvm.org/D46423
Patch by Lewis Revill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346655
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Nirav Dave [Mon, 12 Nov 2018 14:05:40 +0000 (14:05 +0000)]
[DAGCombiner] Fix load-store forwarding of indexed loads.
Summary:
Handle extra output from index loads in cases where we wish to
forward a load value directly from a preceeding store.
Fixes PR39571.
Reviewers: peter.smith, rengolin
Subscribers: javed.absar, hiraditya, arphaman, llvm-commits
Differential Revision: https://reviews.llvm.org/D54265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346654
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Andrea Di Biagio [Mon, 12 Nov 2018 13:09:39 +0000 (13:09 +0000)]
[llvm-mca] Correctly update the resource strategy for processor resources with multiple units.
When looking at the tests committed by Roman at r346587, I noticed that numbers
reported by the resource pressure for PdAGU01 were wrong.
In particular, according to the aut-generated CHECK lines in tests
memcpy-like-test.s and store-throughput.s, resource pressure for PdAGU01
was not uniformly distributed among the two AGEN pipes.
It turns out that the reason why pressure was not correctly distributed, was
because the "resource selection strategy" object associated with PdAGU01 was not
correctly updated on the event of AGEN pipe used.
As a result, llvm-mca was not simulating a round-robin pipeline allocation for
PdAGU01. Instead, PdAGU1 was always prioritized over PdAGU0.
This patch fixes the issue; now processor resource strategy objects for
resources declaring multiple units, are correctly notified in the event of
"resource used".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346650
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Philip Pfaffe [Mon, 12 Nov 2018 12:27:58 +0000 (12:27 +0000)]
[newpm] Fix r346645: Missing consume of the Error return by the pipeline parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346649
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Philip Pfaffe [Mon, 12 Nov 2018 11:17:07 +0000 (11:17 +0000)]
Add an OptimizerLast EP
Summary:
It turns out that we need an OptimizerLast PassBuilder extension point
after all. I missed the relevance of this EP the first time. By legacy PM magic,
function passes added at this EP get added to the last _Function_ PM, which is a
feature we lost when dropping this EP for the new PM.
A key difference between this and the legacy PassManager's OptimizerLast
callback is that this extension point is not triggered at O0. Extensions
to the O0 pipeline should append their passes to the end of the overall
pipeline.
Differential Revision: https://reviews.llvm.org/D54374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346645
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Max Kazantsev [Mon, 12 Nov 2018 09:29:58 +0000 (09:29 +0000)]
[LICM] Hoist guards from non-header blocks
This patch relaxes overconservative checks on whether or not we could write
memory before we execute an instruction. This allows us to hoist guards out of
loops even if they are not in the header block.
Differential Revision: https://reviews.llvm.org/D50891
Reviewed By: fedor.sergeev
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346643
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Calixte Denizet [Mon, 12 Nov 2018 09:01:43 +0000 (09:01 +0000)]
[GCOV] Add options to filter files which must be instrumented.
Summary:
When making code coverage, a lot of files (like the ones coming from /usr/include) are removed when post-processing gcno/gcda so finally they doen't need to be instrumented nor to appear in gcno/gcda.
The goal of the patch is to be able to filter the files we want to instrument, there are several advantages to do that:
- improve speed (no overhead due to instrumentation on files we don't care)
- reduce gcno/gcda size
- it gives the possibility to easily instrument only few files (e.g. ones modified in a patch) without changing the build system
- need to accept this patch to be enabled in clang: https://reviews.llvm.org/D52034
Reviewers: marco-c, vsk
Reviewed By: marco-c
Subscribers: llvm-commits, sylvestre.ledru
Differential Revision: https://reviews.llvm.org/D52033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346641
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Jonas Paulsson [Mon, 12 Nov 2018 08:12:20 +0000 (08:12 +0000)]
[SystemZ] Replicate the load with most uses in buildVector()
Iterate over all elements and count the number of uses among them for each
used load. Then make sure to REPLICATE the load which has the most uses in
order to minimize the number of needed element insertions.
Review: Ulrich Weigand
https://reviews.llvm.org/D54322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346637
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Fangrui Song [Mon, 12 Nov 2018 08:10:14 +0000 (08:10 +0000)]
[llvm-objdump] add more constraints for tests
Patch by Higuoxing (Xing)
Reviewers: jhenderson
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D54299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346636
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Philip Reames [Mon, 12 Nov 2018 02:34:54 +0000 (02:34 +0000)]
[GC] Remove unused configuration variable
The custom root mechanism didn't actually do anything. ShadowStackGC, the only one which used it, just removed the gcroots before they reached the normal lowering in SelectionDAG. As a result, the state flag had no value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346632
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Philip Reames [Mon, 12 Nov 2018 02:26:26 +0000 (02:26 +0000)]
[GC] Minor style modernization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346631
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Fangrui Song [Sun, 11 Nov 2018 23:17:46 +0000 (23:17 +0000)]
[IPSCCP] Delete two forward declarations
Summary: Use forward declaration as the reviewer is in favor of #include and delete a redundant declaration of Function.
Reviewers: fhahn
Reviewed By: fhahn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54398
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346627
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Jonas Devlieghere [Sun, 11 Nov 2018 22:12:21 +0000 (22:12 +0000)]
[llvm-nm] Use WithColor for error reporting
Use helpers from Support/WithError.h to print errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346624
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Jonas Devlieghere [Sun, 11 Nov 2018 22:12:04 +0000 (22:12 +0000)]
[llvm-objdump] Use WithColor for error reporting
Use helpers from Support/WithError.h to print errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346623
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Jonas Devlieghere [Sun, 11 Nov 2018 22:11:47 +0000 (22:11 +0000)]
[llvm-undname] Use WithColor for error reporting
Use helpers from Support/WithError.h to print errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346622
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Philip Reames [Sun, 11 Nov 2018 21:13:09 +0000 (21:13 +0000)]
[GCRoot] Remove some unneccessary complexity
The GCStrategy provides three configuration options were are largely redundant.
1) Support for conditionally lowering gcread and gcwrite to loads and stores. This is redundant since any GC which wished to use these abstractions would lower them out of existance before the built in lowering anyways. As such, there's no need to have the lowering being conditional.
2) Conditional initialization for allocas marked via gcroot. Semantically, roots have to be initialized before first potential use. Arguably, the frontend really should have responsibility for that, but the old API allowed the frontend to ignore this detail. Only one builtin GC used the non-initializing mode. Since no one to my knowledge actually uses the ErlangGC strategy, I decide the slight pessimization was worth the simplicity. If that turns out to be problematic, we can always improve the insertion algorithm to detect more existing initializing stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346621
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Florian Hahn [Sun, 11 Nov 2018 20:57:04 +0000 (20:57 +0000)]
[IPSCCP] Use forward declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346620
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Fangrui Song [Sun, 11 Nov 2018 20:44:13 +0000 (20:44 +0000)]
[IPSCCP,PM] Add missing #include in rL346618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346619
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Florian Hahn [Sun, 11 Nov 2018 20:22:45 +0000 (20:22 +0000)]
[IPSCCP,PM] Preserve PDT in the new pass manager.
Reviewers: kuhar, chandlerc, NutshellySima, brzycki
Reviewed By: NutshellySima, brzycki
Differential Revision: https://reviews.llvm.org/D54317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346618
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Fangrui Song [Sun, 11 Nov 2018 19:15:27 +0000 (19:15 +0000)]
[MC] Fix 3 objdump tests after rL346610
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346617
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Fangrui Song [Sun, 11 Nov 2018 18:57:28 +0000 (18:57 +0000)]
[DWARF] Change pubnames to use DWARFSection instead of StringRef
Summary: The debug_info_offset values in .debug_{,gnu_}pub{name,types} may be relocated. Change it to DWARFSection so that we can get relocated values.
Reviewers: ruiu, dblaikie, grimar, JDevlieghere
Reviewed By: JDevlieghere
Subscribers: aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D54375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346615
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Kristina Brooks [Sun, 11 Nov 2018 18:40:33 +0000 (18:40 +0000)]
[llvm][test] Update tests using objdump
Update tests using llvm-objdump since check strings don't
match anymore due to the extra `O` in place. This is a
followup for rL346610.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346611
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Kristina Brooks [Sun, 11 Nov 2018 17:47:13 +0000 (17:47 +0000)]
[llvm-objdump] Add symbol 'O' for object data
Improve compatibility with GNU objdump by showing `O` next to
global symbol names, instead of a blank space.
Patch by Higuoxing (Xing).
Reviewers: MaskRay
Differential Revision: https://reviews.llvm.org/D54380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346610
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Sanjay Patel [Sun, 11 Nov 2018 14:57:26 +0000 (14:57 +0000)]
[x86] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346609
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Nico Weber [Sun, 11 Nov 2018 10:04:00 +0000 (10:04 +0000)]
Make initializeOutputStream() return false on error and true on success.
As discussed in https://reviews.llvm.org/D52104
Differential Revision: https://reviews.llvm.org/D52143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346606
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Craig Topper [Sun, 11 Nov 2018 07:24:36 +0000 (07:24 +0000)]
[X86] Use DAG.getConstant instead of getZeroVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346605
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Jonas Devlieghere [Sun, 11 Nov 2018 01:46:03 +0000 (01:46 +0000)]
[Support] Make error banner optional in logAllUnhandledErrors
In a lot of places an empty string was passed as the ErrorBanner to
logAllUnhandledErrors. This patch makes that argument optional to
simplify the call sites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346604
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Craig Topper [Sun, 11 Nov 2018 01:40:04 +0000 (01:40 +0000)]
[X86] Replace calls to getOnesVector/getZeroVector with getConstant.
getConstant will create a BUILD_VECTOR for us and use a legal type if necessary. So just create the simple node and let BUILD_VECTOR legalization do the canonicalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346603
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Jonas Devlieghere [Sun, 11 Nov 2018 01:24:02 +0000 (01:24 +0000)]
[llvm-cxxdump] Use error reporting helpers from support
This patch makes llvm-cxxdump use the error reporting helpers from
Support/WithColor.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346602
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Craig Topper [Sat, 10 Nov 2018 23:46:03 +0000 (23:46 +0000)]
[DAGCombiner] Make tryToFoldExtendOfConstant return an SDValue instead of an SDNode*. NFC
Removes the need to call getNode internally and to recreate an SDValue after the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346600
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Sanjay Patel [Sat, 10 Nov 2018 20:29:25 +0000 (20:29 +0000)]
[InstCombine] simplify code for merging stores; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346596
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Sanjay Patel [Sat, 10 Nov 2018 20:05:31 +0000 (20:05 +0000)]
[x86] allow vector load narrowing with multi-use values
This is a long-awaited follow-up suggested in D33578. Since then, we've picked up even more
opportunities for vector narrowing from changes like D53784, so there are a lot of test diffs.
Apart from 2-3 strange cases, these are all wins.
I've structured this to be no-functional-change-intended for any target except for x86
because I couldn't tell if AArch64, ARM, and AMDGPU would improve or not. All of those
targets have existing regression tests (4, 4, 10 files respectively) that would be
affected. Also, Hexagon overrides the shouldReduceLoadWidth() hook, but doesn't show
any regression test diffs. The trade-off is deciding if an extra vector load is better
than a single wide load + extract_subvector.
For x86, this is almost always better (on paper at least) because we often can fold
loads into subsequent ops and not increase the official instruction count. There's also
some unknown -- but potentially large -- benefit from using narrower vector ops if wide
ops are implemented with multiple uops and/or frequency throttling is avoided.
Differential Revision: https://reviews.llvm.org/D54073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346595
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Sanjay Patel [Sat, 10 Nov 2018 18:51:10 +0000 (18:51 +0000)]
[InstCombine] auto-generate full checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346594
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David Carlier [Sat, 10 Nov 2018 18:47:00 +0000 (18:47 +0000)]
Fix DragonFlyBSD linkage issue.
environ global failed on LTO linkage step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346593
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Benjamin Kramer [Sat, 10 Nov 2018 18:11:11 +0000 (18:11 +0000)]
[X86] Remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346592
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Craig Topper [Sat, 10 Nov 2018 17:44:28 +0000 (17:44 +0000)]
[X86] Remove apparently unneeded code from combineVSZext.
No lit tests fail with this code removed.
This is a pre-commit for D54346.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346590
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Simon Pilgrim [Sat, 10 Nov 2018 17:37:52 +0000 (17:37 +0000)]
[CostModel][X86] SK_ExtractSubvector costs must only be tested for vector types (PR39615)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346589
91177308-0d34-0410-b5e6-
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Philip Reames [Sat, 10 Nov 2018 16:08:10 +0000 (16:08 +0000)]
[GC] Rename a header for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346588
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Roman Lebedev [Sat, 10 Nov 2018 14:31:43 +0000 (14:31 +0000)]
[X86][BdVer2] Fix loads/stores throughput for Piledriver (PR39465)
There are two AGU units, and per 1cy, there can be either two loads,
or a load and a store; but not two stores, or two loads and a store.
Additionally, loads shouldn't affect the store scheduler and vice versa.
(but *should* affect the PdEX scheduler.)
Required rL346545.
Fixes https://bugs.llvm.org/show_bug.cgi?id=39465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346587
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Roman Lebedev [Sat, 10 Nov 2018 10:56:58 +0000 (10:56 +0000)]
[NFC][MCA][BdVer2] Add bdver2 runline into register-file-statistics.s test
Missed this one by accident when adding
the initial version in rL345463 / rL345462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346585
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Eugene Leviant [Sat, 10 Nov 2018 08:31:21 +0000 (08:31 +0000)]
[ThinLTO] Internalize readonly globals
This patch allows internalising globals if all accesses to them
(from live functions) are from non-volatile load instructions
Differential revision: https://reviews.llvm.org/D49362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346584
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Craig Topper [Sat, 10 Nov 2018 06:04:33 +0000 (06:04 +0000)]
[X86] Use a MOVSX instruction instead of a MOVZX instruction in isel for an any_extend of the remainder from an 8-bit sdivrem.
The sdivrem will emit its own MOVSX to move %ah to the low byte of a register. By using a MOVSX for an any_extend this allows a post-isel peephole to merge them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346581
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Craig Topper [Sat, 10 Nov 2018 06:04:09 +0000 (06:04 +0000)]
[X86] Add a test case to show scalarized vector srem to demonstrate unnecessary instructions. NFC
After the division %ah is being sign extended to move it to lower byte of a register while avoiding a partial register read. We then zero extend the low byte to the full 32 bit register. But we don't use any of the zero extended bits. In the DAG the zero extend was really an any_extend so the sign extend should have been enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346580
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David Carlier [Sat, 10 Nov 2018 01:01:03 +0000 (01:01 +0000)]
Fix DragonFlyBSD build
Reviewers: rnk, thakis
Reviewed By: krytarowski
Differential Revision: https://reviews.llvm.org/D54363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346577
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Matthias Braun [Sat, 10 Nov 2018 00:36:27 +0000 (00:36 +0000)]
RegAllocFast: Further cleanups; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346576
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Matthias Braun [Sat, 10 Nov 2018 00:34:09 +0000 (00:34 +0000)]
test/CodeGen/X86: Relax test case
No need to hardcode register or expecting totally unnecessary spills
from the allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346575
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Craig Topper [Sat, 10 Nov 2018 00:26:42 +0000 (00:26 +0000)]
[X86] In LowerHorizontalByteSum, emit vector_shuffle nodes instead of directly using X86ISD::UNPCKL/X86ISD::UNPCKH.
This gives shuffle lowering the freedom to use zero_extend_vector_inreg for the unpckl shuffle. Shuffle combining usually makes this swap later, but not when AVX512 is enabled it seems.
While there also use DAG.getConstant to create a 0 vector instead of using the helper the forces a specific BUILD_VECTOR. I don't think that helper is usually needed. We're basically free to create a constant build_vector anytime and it will be legalized on its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346574
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