OSDN Git Service
Zvi Rackover [Sat, 8 Oct 2016 18:44:47 +0000 (18:44 +0000)]
[X86] Apply the Update LLC Test Checks tool on the rotate tests.
Also added cases demonstrating pr30644.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283667
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Simon Pilgrim [Sat, 8 Oct 2016 18:36:57 +0000 (18:36 +0000)]
[X86][AVX2] Regenerate and add 32-bit tests to core tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283666
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Colin LeMahieu [Sat, 8 Oct 2016 17:18:51 +0000 (17:18 +0000)]
[Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this restriction rather than implying it from TypeJR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283665
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Teresa Johnson [Sat, 8 Oct 2016 16:11:42 +0000 (16:11 +0000)]
[ThinLTO] Record calls to aliases
Summary:
When there is a call to an alias in the same module, we were not
adding a call edge. So we could incorrectly think that the alias
was dead if it was inlined in that function, despite having a
reference imported elsewhere. This resulted in unsats at link time.
Add a call edge when the call is to an alias.
Reviewers: davide, mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283664
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Sebastian Pop [Sat, 8 Oct 2016 12:30:07 +0000 (12:30 +0000)]
[AArch64] Avoid generating indexed vector instructions for Exynos
Avoid generating indexed vector instructions for Exynos. This is needed for
fmla/fmls/fmul/fmulx. For example, the instruction
fmla v0.4s, v1.4s, v2.s[1]
is less efficient than the instructions
dup v2.4s, v2.s[1]
fmla v0.4s, v1.4s, v2.4s
Patch written by Abderrazek Zaafrani.
Differential Revision: https://reviews.llvm.org/D21571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283663
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Adam Nemet [Sat, 8 Oct 2016 04:47:20 +0000 (04:47 +0000)]
[OptRemarks] Remove non-printable chars from function name
Value names may be prefixed with a binary '1' to indicate that the
backend should not modify the symbols due to any platform naming
convention.
This should not show up in the YAML opt record file because it breaks
the YAML parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283656
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Mehdi Amini [Sat, 8 Oct 2016 04:44:23 +0000 (04:44 +0000)]
ThinLTO: don't perform incremental LTO on module without a hash
Clang always emit a hash for ThinLTO, but as other frontend are
starting to use ThinLTO, this could be a serious bug.
Differential Revision: https://reviews.llvm.org/D25379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283655
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Mehdi Amini [Sat, 8 Oct 2016 04:44:18 +0000 (04:44 +0000)]
ThinLTO: handles modules with empty summaries
We need to add an entry in the combined-index for modules that have
a hash but otherwise empty summary, this is needed so that we can
get the hash for the module.
Also, if no entry is present in the combined index for a module, we
need to skip it when trying to compute a cache entry.
Differential Revision: https://reviews.llvm.org/D25300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283654
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Mehdi Amini [Sat, 8 Oct 2016 04:39:34 +0000 (04:39 +0000)]
Requires the AVR backend for running test/CodeGen/AVR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283653
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Kyle Butt [Sat, 8 Oct 2016 01:47:05 +0000 (01:47 +0000)]
Revert "Codegen: Tail-duplicate during placement."
This reverts commit
71c312652c10f1855b28d06697c08d47e7a243e4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283647
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Dylan McKay [Sat, 8 Oct 2016 01:14:23 +0000 (01:14 +0000)]
[AVR] Add backend dependencies to MCTargetDesc/LLVMBuild.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283642
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Zachary Turner [Sat, 8 Oct 2016 01:12:01 +0000 (01:12 +0000)]
[pdb] Dump Module Symbols to Yaml.
This is the first step towards round-tripping symbol information,
and thusly being able to write symbol information to a PDB.
This patch writes the symbol information for each compiland to
the Yaml when running in pdb2yaml mode. There's still some loose
ends, such as what to do about relocations (necessary in order to
print linkage names), how to print enums with friendly names, and
how to give the dumper access to the StringTable, but this is a
good first start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283641
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Dylan McKay [Sat, 8 Oct 2016 01:10:36 +0000 (01:10 +0000)]
Fix incorrect assertion in AVRFrameLowering.cpp
This wasn't looking at the right instruction, and would always fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283640
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Dylan McKay [Sat, 8 Oct 2016 01:10:31 +0000 (01:10 +0000)]
[AVR] Don't worry about call frame size when initializing frame pointer
We previously only used the frame pointer if the frame pointer was too
big. This was to work around a bug (described in this old commit)
https://sourceforge.net/p/avr-llvm/code/204/tree//llvm/trunk/AVR/AVRFrameLowering.cpp?diff=
50d64d912718465cb887d17a:203
I mistakenly invered the condition assuming it was a typo. I am now
removing it because it doesn't seem to be a problem anymore (plus it's a
dirty hack).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283639
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Dylan McKay [Sat, 8 Oct 2016 01:09:06 +0000 (01:09 +0000)]
[AVR] Don't shadow container while iterating in range-based loop
This works on clang, but fails on GCC 4.6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283638
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Dylan McKay [Sat, 8 Oct 2016 01:06:21 +0000 (01:06 +0000)]
[AVR] Use references rather than pointers in AVRISelLowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283636
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Dylan McKay [Sat, 8 Oct 2016 01:05:09 +0000 (01:05 +0000)]
Allow a maximum of 64 bits to be returned in registers
The rest spills to the stack
Authored by Jake Goulding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283635
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Dylan McKay [Sat, 8 Oct 2016 01:01:49 +0000 (01:01 +0000)]
[AVR] Expand MULHS for all types
Once MULHS was expanded, this exposed an issue where the condition
register was thought to be 16-bit. This caused an attempt to copy a
16-bit register to an 8-bit register.
Authored by Jake Goulding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283634
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Dylan McKay [Sat, 8 Oct 2016 00:55:46 +0000 (00:55 +0000)]
[AVR] Add the 'SoftFail' field to all instruction formats
This will be used in the future for disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283630
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Dylan McKay [Sat, 8 Oct 2016 00:50:11 +0000 (00:50 +0000)]
[AVR] Set up the instruction printer and the assembly backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283629
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Dylan McKay [Sat, 8 Oct 2016 00:45:24 +0000 (00:45 +0000)]
[AVR] Add dependencies to AVR libraries in AVRCodeGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283628
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Dylan McKay [Sat, 8 Oct 2016 00:42:58 +0000 (00:42 +0000)]
[AVR] Add missing subdirectories to LLVMBuild
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283627
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Hal Finkel [Sat, 8 Oct 2016 00:26:54 +0000 (00:26 +0000)]
[llvm-opt-report] Don't leave space for opts that never happen
Because screen space is precious, if an optimization (vectorization, for
example) never happens, don't leave empty space for the associated markers on
every line of the output. This makes the output much more compact, and allows
for the later inclusion of markers for more (although perhaps rare)
optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283626
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Gor Nishanov [Sat, 8 Oct 2016 00:22:50 +0000 (00:22 +0000)]
[coroutines] Store an address of destroy OR cleanup part in the coroutine frame.
Summary:
If heap allocation of a coroutine is elided, we need to make sure that we will update an address stored in the coroutine frame from f.destroy to f.cleanup.
Before this change, CoroSplit synthesized these stores after coro.begin:
```
store void (%f.Frame*)* @f.resume, void (%f.Frame*)** %resume.addr
store void (%f.Frame*)* @f.destroy, void (%f.Frame*)** %destroy.addr
```
In those cases where we did heap elision, but were not able to devirtualize all indirect calls, destroy call will attempt to "free" the coroutine frame stored on the stack. Oops.
Now we use select to put an appropriate coroutine subfunction in the destroy slot. As bellow:
```
store void (%f.Frame*)* @f.resume, void (%f.Frame*)** %resume.addr
%0 = select i1 %need.alloc, void (%f.Frame*)* @f.destroy, void (%f.Frame*)* @f.cleanup
store void (%f.Frame*)* %0, void (%f.Frame*)** %destroy.addr
```
Reviewers: majnemer
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D25377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283625
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Lang Hames [Sat, 8 Oct 2016 00:20:42 +0000 (00:20 +0000)]
[docs] Fix indentation bug in LangRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283624
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Dylan McKay [Sat, 8 Oct 2016 00:02:36 +0000 (00:02 +0000)]
[AVR] Add the assembly printer
Summary: This adds the AVRAsmPrinter class.
Reviewers: arsenm, kparzysz
Subscribers: llvm-commits, wdng, beanz, japaric, mgorny
Differential Revision: https://reviews.llvm.org/D25271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283623
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Tom Stellard [Fri, 7 Oct 2016 23:42:48 +0000 (23:42 +0000)]
AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283622
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Kyle Butt [Fri, 7 Oct 2016 22:33:20 +0000 (22:33 +0000)]
Codegen: Tail-duplicate during placement.
The tail duplication pass uses an assumed layout when making duplication
decisions. This is fine, but passes up duplication opportunities that
may arise when blocks are outlined. Because we want the updated CFG to
affect subsequent placement decisions, this change must occur during
placement.
In order to achieve this goal, TailDuplicationPass is split into a
utility class, TailDuplicator, and the pass itself. The pass delegates
nearly everything to the TailDuplicator object, except for looping over
the blocks in a function. This allows the same code to be used for tail
duplication in both places.
This change, in concert with outlining optional branches, allows
triangle shaped code to perform much better, esepecially when the
taken/untaken branches are correlated, as it creates a second spine when
the tests are small enough.
Issue from previous rollback fixed, and a new test was added for that
case as well. Issue was worklist/scheduling/taildup issue in layout.
Issue from 2nd rollback fixed, with 2 additional tests. Issue was
tail merging/loop info/tail-duplication causing issue with loops that share
a header block.
Differential revision: https://reviews.llvm.org/D18226
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283619
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Arnold Schwaighofer [Fri, 7 Oct 2016 22:06:55 +0000 (22:06 +0000)]
swifterror: Don't compute swifterror vregs during instruction selection
The code used llvm basic block predecessors to decided where to insert phi
nodes. Instruction selection can and will liberally insert new machine basic
block predecessors. There is not a guaranteed one-to-one mapping from pred.
llvm basic blocks and machine basic blocks.
Therefore the current approach does not work as it assumes we can mark
predecessor machine basic block as needing a copy, and needs to know the set of
all predecessor machine basic blocks to decide when to insert phis.
Instead of computing the swifterror vregs as we select instructions, propagate
them at the end of instruction selection when the MBB CFG is complete.
When an instruction needs a swifterror vreg and we don't know the value yet,
generate a new vreg and remember this "upward exposed" use, and reconcile this
at the end of instruction selection.
This will only happen if the target supports promoting swifterror parameters to
registers and the swifterror attribute is used.
rdar://
28300923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283617
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Sanjay Patel [Fri, 7 Oct 2016 21:55:42 +0000 (21:55 +0000)]
[DAG] clean up foldSelectOfConstants(); NFCI
Rename variables, simplify logic.
Not clear yet why we don't handle a target with ZeroOrNegativeOneBooleanContent too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283613
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Davide Italiano [Fri, 7 Oct 2016 21:53:09 +0000 (21:53 +0000)]
[InstCombine] Don't unpack arrays that are too large (part 2).
This is similar to r283599, but for store instructions.
Thanks to David for pointing out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283612
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Zachary Turner [Fri, 7 Oct 2016 21:40:06 +0000 (21:40 +0000)]
Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283610
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Zachary Turner [Fri, 7 Oct 2016 21:34:46 +0000 (21:34 +0000)]
Refactor Symbol visitor code.
Type visitor code had already been refactored previously to
decouple the visitor and the visitor callback interface. This
was necessary for having the flexibility to visit in different
ways (for example, dumping to yaml, reading from yaml, dumping
to ScopedPrinter, etc).
This patch merely implements the same visitation pattern for
symbol records that has already been implemented for type records.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283609
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Hongbin Zheng [Fri, 7 Oct 2016 21:32:47 +0000 (21:32 +0000)]
[cmake] Treat polly as "in tree" if LLVM_EXTERNAL_POLLY_SOURCE_DIR is provided
Differential Revision: https://reviews.llvm.org/D25354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283608
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Davide Italiano [Fri, 7 Oct 2016 20:57:42 +0000 (20:57 +0000)]
[InstCombine] Don't unpack arrays that are too large
Differential Revision: https://reviews.llvm.org/D25376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283599
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Sanjay Patel [Fri, 7 Oct 2016 20:47:51 +0000 (20:47 +0000)]
[DAG] move fold (select C, 0, 1 -> xor C, 1) to a helper function; NFC
We're missing at least 3 other similar folds based on what we have in InstCombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283596
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Tom Stellard [Fri, 7 Oct 2016 20:36:58 +0000 (20:36 +0000)]
AMDGPU/SI: Add support for 8-byte relocations
Reviewers: arsenm, kzhuravl
Subscribers: wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283593
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Anna Thomas [Fri, 7 Oct 2016 20:34:00 +0000 (20:34 +0000)]
[RS4GC] Strengthen coverage: add more tests
Summary: Add tests for cases where we have zero coverage in RS4GC.
Reviewers: sanjoy, reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283591
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Colin LeMahieu [Fri, 7 Oct 2016 19:11:28 +0000 (19:11 +0000)]
[Hexagon][NFC] Using documented instruction type name V4LDST instead of MEMOP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283582
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Mehdi Amini [Fri, 7 Oct 2016 19:05:14 +0000 (19:05 +0000)]
Recommit "Use StringRef in LTOModule implementation (NFC)""
This reverts commit r283456 and reapply r282997, with explicitly
zeroing the struct member to workaround a bug in MSVC2013 with
zero-initialization: https://connect.microsoft.com/VisualStudio/feedback/details/802160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283581
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Davide Italiano [Fri, 7 Oct 2016 18:39:43 +0000 (18:39 +0000)]
[LoopIdiomRecognize] Merge two if conditions into one. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283579
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Sanjay Patel [Fri, 7 Oct 2016 17:53:07 +0000 (17:53 +0000)]
[InstCombine] fold select X, (ext X), C
If we're going to canonicalize IR towards select of constants, try harder to create those.
Also, don't lose the metadata.
This is actually 4 related transforms in one patch:
// select X, (sext X), C --> select X, -1, C
// select X, (zext X), C --> select X, 1, C
// select X, C, (sext X) --> select X, C, 0
// select X, C, (zext X) --> select X, C, 0
Differential Revision: https://reviews.llvm.org/D25126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283575
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Adam Nemet [Fri, 7 Oct 2016 17:06:34 +0000 (17:06 +0000)]
New utility to visualize optimization records
This is a new tool built on top of the new YAML ouput generated from
optimization remarks. It produces HTML for easy navigation and
visualization.
The tool assumes that hotness information for the remarks is available
(the YAML file was produced with PGO). It uses hotness to list the
remarks prioritized by the hotness on the index page. Clicking the
source location of the remark in the list takes you the source where the
remarks are rendedered inline in the source.
For now, the tool is meant as prototype.
It's written in Python. It uses PyYAML to parse the input.
Differential Revision: https://reviews.llvm.org/D25348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283571
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Tom Stellard [Fri, 7 Oct 2016 16:01:18 +0000 (16:01 +0000)]
AMDGPU/SI: Emit fixups for long branches
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283570
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Simon Pilgrim [Fri, 7 Oct 2016 16:00:59 +0000 (16:00 +0000)]
[X86][SSE] Reapplied: Add vector fcopysign combine tests
Now with better lowering and fix for PR30443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283569
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Artem Tamazov [Fri, 7 Oct 2016 15:53:16 +0000 (15:53 +0000)]
[AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.
Partially fixes Bug 28232.
Lit tests added.
Differential Revision: https://reviews.llvm.org/D25367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283567
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Dehao Chen [Fri, 7 Oct 2016 15:21:31 +0000 (15:21 +0000)]
Invoke add-discriminator at -g0 -fsample-profile
Summary: -fsample-profile needs discriminator, which will not be added if built with -g0. This patch makes sure the discriminator is added for sample-profile at -g0. A followup patch will be send out to update clang tests.
Reviewers: davidxl, dblaikie, echristo, dnovillo
Subscribers: mehdi_amini, probinson, llvm-commits
Differential Revision: https://reviews.llvm.org/D25132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283565
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Matthew Simpson [Fri, 7 Oct 2016 15:20:13 +0000 (15:20 +0000)]
[LV] Don't mark multi-use branch conditions uniform
Previously, we marked the branch conditions of latch blocks uniform after
vectorization if they were instructions contained in the loop. However, if a
condition instruction has users other than the branch, it may not remain
uniform. This patch ensures the conditions we mark uniform are only used by the
branch. This should fix PR30627.
Reference: https://llvm.org/bugs/show_bug.cgi?id=30627
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283563
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Krzysztof Parzyszek [Fri, 7 Oct 2016 14:50:49 +0000 (14:50 +0000)]
Only track physical registers in LivePhysRegs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283561
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Sam Kolton [Fri, 7 Oct 2016 14:46:06 +0000 (14:46 +0000)]
[AMDGPU] Assembler: support v_mac_f32 DPP and SDWA. Move getNamedOperandIdx to AMDGPUBaseInfo.h
Reviewers: artem.tamazov, tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D25084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283560
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Simon Pilgrim [Fri, 7 Oct 2016 14:42:22 +0000 (14:42 +0000)]
[X86][SSE] Tidied up tests - use standard check prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283559
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Fri, 7 Oct 2016 14:39:53 +0000 (14:39 +0000)]
[AMDGPU] AMDGPUCodeGenPrepare: remove extra ';'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283558
91177308-0d34-0410-b5e6-
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Tom Stellard [Fri, 7 Oct 2016 14:23:29 +0000 (14:23 +0000)]
[ValueTracking] Fix crash in GetPointerBaseWithConstantOffset()
Summary:
While walking defs of pointer operands we were assuming that the pointer
size would remain constant. This is not true, because addresspacecast
instructions may cast the pointer to an address space with a different
pointer width.
This partial reverts r282612, which was a more conservative solution
to this problem.
Reviewers: reames, sanjoy, apilipenko
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D24772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283557
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Fri, 7 Oct 2016 14:22:58 +0000 (14:22 +0000)]
[AMDGPU] Promote uniform (i1, i16] operations to i32
Differential Revision: https://reviews.llvm.org/D25302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283555
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Fri, 7 Oct 2016 13:46:38 +0000 (13:46 +0000)]
Remove spurious non-printable character from source file.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283552
91177308-0d34-0410-b5e6-
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Javed Absar [Fri, 7 Oct 2016 13:41:55 +0000 (13:41 +0000)]
[ARM]: add missing switch case for cortex-r52
Adds a missing switch case for handling cortex-r52
in init-subtarget-features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283551
91177308-0d34-0410-b5e6-
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Martin Storsjo [Fri, 7 Oct 2016 13:28:53 +0000 (13:28 +0000)]
[ARM] Reapply: Use __rt_div functions for divrem on Windows
Reapplying r283383 after revert in r283442. The additional fix
is a getting rid of a stray space in a function name, in the
refactoring part of the commit.
This avoids falling back to calling out to the GCC rem functions
(__moddi3, __umoddi3) when targeting Windows.
The __rt_div functions have flipped the two arguments compared
to the __aeabi_divmod functions. To match MSVC, we emit a
check for division by zero before actually calling the library
function (even if the library function itself also might do
the same check).
Not all calls to __rt_div functions for division are currently
merged with calls to the same function with the same parameters
for the remainder. This is more wasteful than a div + mls as before,
but avoids calls to __moddi3.
Differential Revision: https://reviews.llvm.org/D25332
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283550
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Javed Absar [Fri, 7 Oct 2016 12:06:40 +0000 (12:06 +0000)]
[ARM]: Add Cortex-R52 target to LLVM
This patch adds Cortex-R52, the new ARM real-time processor, to LLVM.
Cortex-R52 implements the ARMv8-R architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283542
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 7 Oct 2016 11:18:38 +0000 (11:18 +0000)]
[X86][SSE] Update register class during MOVSD/MOVSS - BLENDPD/BLENDPS commutation
MOVSD/MOVSS take a 128-bit register and a FR32/FR64 register input, the commutation code wasn't taking this into account leading to verification errors.
This patch inserts a vreg copy mi to ensure that the registers are correct.
Fix for PR30607
Differential Revision: https://reviews.llvm.org/D25280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283539
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Alexey Bataev [Fri, 7 Oct 2016 09:39:22 +0000 (09:39 +0000)]
[SLPVectorizer] Fix for PR25748: reduction vectorization after loop
unrolling.
The next code is not vectorized by the SLPVectorizer:
```
int test(unsigned int *p) {
int sum = 0;
for (int i = 0; i < 8; i++)
sum += p[i];
return sum;
}
```
During optimization this loop is fully unrolled and SLPVectorizer is
unable to vectorize it. Patch tries to fix this problem.
Differential Revision: https://reviews.llvm.org/D24796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283535
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Oliver Stannard [Fri, 7 Oct 2016 08:48:24 +0000 (08:48 +0000)]
[ARM] Don't convert switches to lookup tables of pointers with ROPI/RWPI
With the ROPI and RWPI relocation models we can't always have pointers
to global data or functions in constant data, so don't try to convert switches
into lookup tables if any value in the lookup table would require a relocation.
We can still safely emit lookup tables of other values, such as simple
constants.
Differential Revision: https://reviews.llvm.org/D24462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283530
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Mehdi Amini [Fri, 7 Oct 2016 08:48:07 +0000 (08:48 +0000)]
Use StringRef in ARMELFStreamer (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283529
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Fri, 7 Oct 2016 08:40:14 +0000 (08:40 +0000)]
AMDGPU: Fix use-after-free in SIOptimizeExecMasking
Summary:
There was a bug with sequences like
s_mov_b64 s[0:1], exec
s_and_b64 s[2:3]<def>, s[0:1], s[2:3]<kill>
...
s_mov_b64_term exec, s[2:3]
because s[2:3] was defined and used in the same instruction, ending up with
SaveExecInst inside OtherUseInsts.
Note that the test case also exposes an unrelated bug.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98028
Reviewers: tstellarAMD, arsenm
Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283528
91177308-0d34-0410-b5e6-
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Mehdi Amini [Fri, 7 Oct 2016 08:37:29 +0000 (08:37 +0000)]
Use StringReg in TargetParser APIs (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283527
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Mehdi Amini [Fri, 7 Oct 2016 08:25:42 +0000 (08:25 +0000)]
Revert "Revert "Add a static_assert to enforce that parameters to llvm::format() are not totally unsafe""
This reverts commit r283510 and reapply r283509, with updates to
clang-tools-extra as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283525
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Craig Topper [Fri, 7 Oct 2016 06:54:43 +0000 (06:54 +0000)]
[X86] Fix patterns for VPMULLD and VPCMPEQQ to not require aligned loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283524
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 7 Oct 2016 06:54:39 +0000 (06:54 +0000)]
[X86] Remove unused PatFrags. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283523
91177308-0d34-0410-b5e6-
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Dylan McKay [Fri, 7 Oct 2016 06:13:09 +0000 (06:13 +0000)]
[AVR] Add the AVRMCInstLower class
Summary:
This class deals with the lowering of CodeGen `MachineInstr` objects to
MC `MCInst` objects.
Reviewers: kparzysz, arsenm
Subscribers: wdng, beanz, japaric, mgorny
Differential Revision: https://reviews.llvm.org/D25269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283522
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Matt Arsenault [Fri, 7 Oct 2016 03:55:04 +0000 (03:55 +0000)]
AMDGPU: Change check prefix in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283521
91177308-0d34-0410-b5e6-
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Hal Finkel [Fri, 7 Oct 2016 02:01:03 +0000 (02:01 +0000)]
[llvm-opt-report] Left justify unrolling counts, etc.
In the left part of the reports, we have things like U<number>; if some of
these numbers use more digits than others, we don't want a space in between the
U and the start of the number. Instead, the space should come afterward. This
way it is clear that the number goes with the U and not any other optimization
indicator that might come later on the line.
Tests committed in r283518.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283519
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Hal Finkel [Fri, 7 Oct 2016 01:57:06 +0000 (01:57 +0000)]
[llvm-opt-report] Left justify unrolling counts, etc.
In the left part of the reports, we have things like U<number>; if some of
these numbers use more digits than others, we don't want a space in between the
U and the start of the number. Instead, the space should come afterward. This
way it is clear that the number goes with the U and not any other optimization
indicator that might come later on the line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283518
91177308-0d34-0410-b5e6-
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David Majnemer [Fri, 7 Oct 2016 01:38:35 +0000 (01:38 +0000)]
[SimplifyCFG] Correctly test for unconditional branches in GetCaseResults
GetCaseResults assumed that a terminator with one successor was an
unconditional branch. This is not necessarily the case, it could be a
cleanupret.
Strengthen the check by querying whether or not the terminator is
exceptional.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283517
91177308-0d34-0410-b5e6-
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Hal Finkel [Fri, 7 Oct 2016 01:30:59 +0000 (01:30 +0000)]
[llvm-opt-report] Use -no-demangle to disable demangling
As this is intended to be a user-facing option, -no-demangle seems much better
than -demangle=0. Add testing for the option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283516
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Peter Collingbourne [Fri, 7 Oct 2016 00:30:49 +0000 (00:30 +0000)]
Target: Remove unused patterns and transforms. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283515
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Colin LeMahieu [Fri, 7 Oct 2016 00:15:07 +0000 (00:15 +0000)]
[Hexagon] NFC Removing 'V4_' prefix from duplex instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283514
91177308-0d34-0410-b5e6-
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Michael Kuperstein [Thu, 6 Oct 2016 23:57:25 +0000 (23:57 +0000)]
[LV] Remove triples from target-independent vectorizer tests. NFC.
Vectorizer tests in the target-independent directory should not have a target
triple. If a test really needs to query a specific backend, it belongs in the
right target subdirectory (which "REQUIRES" the right backend). Otherwise, it
should not specify a triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283512
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Mehdi Amini [Thu, 6 Oct 2016 23:41:49 +0000 (23:41 +0000)]
Revert "Add a static_assert to enforce that parameters to llvm::format() are not totally unsafe"
This reverts commit r283509, clang is hitting the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283510
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Mehdi Amini [Thu, 6 Oct 2016 23:26:29 +0000 (23:26 +0000)]
Add a static_assert to enforce that parameters to llvm::format() are not totally unsafe
Summary:
I had for the second time today a bug where llvm::format("%s", Str)
was called with Str being a StringRef. The Linux and MacOS bots were
fine, but windows having different calling convention, it printed
garbage.
Instead we can catch this at compile-time: it is never expected to
call a C vararg printf-like function with non scalar type I believe.
Reviewers: bogner, Bigcheese, dexonsmith
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283509
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Colin LeMahieu [Thu, 6 Oct 2016 23:02:11 +0000 (23:02 +0000)]
[Hexagon] NFC. Canonicalizing absolute address instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283507
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Vedant Kumar [Thu, 6 Oct 2016 22:53:43 +0000 (22:53 +0000)]
Delete some dead code in SelectionDAG (NFC)
Differential Revision: https://reviews.llvm.org/D24435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283505
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Dan Gohman [Thu, 6 Oct 2016 22:29:32 +0000 (22:29 +0000)]
[WebAssemby] Implement block signatures.
Per spec changes, this implements block signatures, and adds just enough
logic to produce correct block signatures at the ends of functions.
Differential Revision: https://reviews.llvm.org/D25144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283503
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Dan Gohman [Thu, 6 Oct 2016 22:10:23 +0000 (22:10 +0000)]
[WebAssembly] Remove loop's bottom label.
Per spec changes, loop constructs no longer have a bottom label.
https://reviews.llvm.org/D25118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283502
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Dan Gohman [Thu, 6 Oct 2016 22:08:28 +0000 (22:08 +0000)]
[WebAssembly] Remove the output operand from stores.
Per spec changes, store instructions in WebAssembly no longer have a return
value. Update the instruction descriptions.
Differential Revision: https://reviews.llvm.org/D25122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283501
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Wolfgang Pieb [Thu, 6 Oct 2016 21:43:45 +0000 (21:43 +0000)]
Preserve the debug location when CodeGenPrepare sinks a compare instruction into the
basic block of a user.
Patch by Andrea DiBiagio.
Differential Revision: https://reviews.llvm.org/D24632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283500
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Pirama Arumuga Nainar [Thu, 6 Oct 2016 21:27:05 +0000 (21:27 +0000)]
Handle *_EXTEND_VECTOR_INREG during Integer Legalization
Summary:
These nodes need legalization for 3-element vectors. This commit
handles the legalization and adds tests for zext and sext.
This fixes PR30614.
Reviewers: RKSimon, srhines
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283496
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Rong Xu [Thu, 6 Oct 2016 20:38:13 +0000 (20:38 +0000)]
[PGO] Create weak alias for the renamed Comdat function
Add a weak alias to the renamed Comdat function in IR level instrumentation,
using it's original name. This ensures the same behavior w/ and w/o IR
instrumentation, even for non standard conforming code.
Differential Revision: http://reviews.llvm.org/D25339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283490
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Michael Kuperstein [Thu, 6 Oct 2016 19:31:27 +0000 (19:31 +0000)]
[X86] Preserve BasePtr for LEA64_32r
When replacing FrameIndex with BasePtr, we must preserve BasePtr for
LEA64_32r since BasePtr is used later for stack adjustment if it is
the same as StackPtr.
Patch by H.J Lu <hjl.tools@gmail.com>
Differential Revision: https://reviews.llvm.org/D23575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283486
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Simon Pilgrim [Thu, 6 Oct 2016 19:29:25 +0000 (19:29 +0000)]
[X86][SSE] Add f16/f80/f128 vector sitofp test cases
As discussed on D23808
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283485
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Michael Kuperstein [Thu, 6 Oct 2016 18:58:24 +0000 (18:58 +0000)]
[DAG] Generalize build_vector -> vector_shuffle combine for more than 2 inputs
This generalizes the build_vector -> vector_shuffle combine to support any
number of inputs. The idea is to create a binary tree of shuffles, where
the first layer performs pairwise shuffles of the input vectors placing each
input element into the correct lane, and the rest of the tree blends these
shuffles together.
This doesn't try to be smart and create any sort of "optimal" shuffles.
The assumption is that even a "poor" shuffle sequence is better than extracting
and inserting the elements one by one.
Differential Revision: https://reviews.llvm.org/D24683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283480
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Michael Ilseman [Thu, 6 Oct 2016 18:30:26 +0000 (18:30 +0000)]
Revert "Add -strip-nonlinetable-debuginfo capability"
This reverts commit r283473.
Reverted until review is completed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283478
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Matt Arsenault [Thu, 6 Oct 2016 18:12:13 +0000 (18:12 +0000)]
AMDGPU: Don't fold undef uses or copies with implicit uses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283476
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 6 Oct 2016 18:12:07 +0000 (18:12 +0000)]
AMDGPU: Remove scheduling info from si_mask_branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283475
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Michael Ilseman [Thu, 6 Oct 2016 17:58:38 +0000 (17:58 +0000)]
Add -strip-nonlinetable-debuginfo capability
This adds a new function to DebugInfo.cpp that takes an llvm::Module
as input and removes all debug info metadata that is not directly
needed for line tables, thus effectively stripping all type and
variable information from the module.
The primary motivation for this feature was the bitcode work flow
(cf. http://lists.llvm.org/pipermail/llvm-dev/2016-June/100643.html
for more background). This is not wired up yet, but will be in
subsequent patches. For testing, the new functionality is exposed to
opt with a -strip-nonlinetable-debuginfo option.
The secondary use-case (and one that works right now!) is as a
reduction pass in bugpoint. I added two new bugpoint options
(-disable-strip-debuginfo and -disable-strip-debug-types) to control
the new features. By default it will first attempt to remove all debug
information, then only the type info, and then proceed to hack at any
remaining MDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283473
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Matt Arsenault [Thu, 6 Oct 2016 17:54:30 +0000 (17:54 +0000)]
AMDGPU: Remove leftover implicit operands when folding immediates
When constant folding an operation to a copy or an immediate
mov, the implicit uses/defs of the old instruction were left behind,
e.g. replacing v_or_b32 left the implicit exec use on the new copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283471
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Matt Arsenault [Thu, 6 Oct 2016 17:19:11 +0000 (17:19 +0000)]
Reapply "AMDGPU: Support using tablegened MC pseudo expansions"
Fix bad merge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283470
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Matt Arsenault [Thu, 6 Oct 2016 17:08:01 +0000 (17:08 +0000)]
Revert "AMDGPU: Support using tablegened MC pseudo expansions"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283469
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Matt Arsenault [Thu, 6 Oct 2016 16:56:41 +0000 (16:56 +0000)]
AMDGPU: Support using tablegened MC pseudo expansions
Make the necessary refactorings to make use of PseudoInstExpansion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283467
91177308-0d34-0410-b5e6-
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Brian Gesiak [Thu, 6 Oct 2016 16:39:22 +0000 (16:39 +0000)]
[docs] Add PR to Lexicon
Summary:
The acronym PR could be ambiguous to some users, especially those who
are used to interpreting it as GitHub's "pull request".
Reviewers: ddunbar, jordan_rose, void, beanz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283465
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Matt Arsenault [Thu, 6 Oct 2016 16:20:41 +0000 (16:20 +0000)]
BranchRelaxation: Support expanding unconditional branches
AMDGPU needs to expand unconditional branches in a new
block with an indirect branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283464
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Krzysztof Parzyszek [Thu, 6 Oct 2016 16:18:04 +0000 (16:18 +0000)]
[Hexagon] Avoid replacing full regs with subregisters in tied operands
Doing so will result in the two-address pass generating incorrect code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283463
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