OSDN Git Service
Craig Topper [Wed, 20 Mar 2019 03:13:28 +0000 (03:13 +0000)]
[X86] Remove X32 check lines from a test that doesn't have an X32 FileCheck prefix. Regenerate the test using update_llc_test_checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356535
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Douglas Yung [Wed, 20 Mar 2019 01:52:40 +0000 (01:52 +0000)]
Retry to add workaround to build scoped enums with VS2015. NFCI.
We need this as we still have internal build bots on VS2015.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356534
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Douglas Yung [Wed, 20 Mar 2019 00:41:12 +0000 (00:41 +0000)]
Revert "Add workaround to build scoped enums with VS2015. NFCI."
This reverts commit
6080a6fb1949a2bdf053245d6062c7bf58dae7a6 (r356532).
Clang does not accept this syntax, so reverting this until I can find something that works across all compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356533
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Douglas Yung [Wed, 20 Mar 2019 00:26:56 +0000 (00:26 +0000)]
Add workaround to build scoped enums with VS2015. NFCI.
We need this as we still have internal build bots on VS2015.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356532
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Craig Topper [Tue, 19 Mar 2019 23:57:16 +0000 (23:57 +0000)]
[X86] Re-disable cmpxchg16b for 32-bit mode assembly parsing.
This was broken recently when I factored the 64 bit mode check into hasCmpxchg16 without thinking about the AssemblerPredicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356531
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Eli Friedman [Tue, 19 Mar 2019 21:48:08 +0000 (21:48 +0000)]
[ARM] Make sure to save/restore LR when we use tBfar.
This change does two things. One, it ensures compilation will abort
instead of miscompiling if ARMFrameLowering::determineCalleeSaves
chooses not to save LR in a case where it's necessary. Two, it changes
the way we estimate the size of a function to be more conservative in
the presence of constant pool entries and jump tables.
EstimateFunctionSizeInBytes probably still isn't really conservative
enough, but I'm not sure how we can come up with a reliable estimate
before constant islands runs.
Differential Revision: https://reviews.llvm.org/D59439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356527
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Amara Emerson [Tue, 19 Mar 2019 21:43:05 +0000 (21:43 +0000)]
[AArch64][GlobalISel] Add an optimization to select vector DUP instructions.
This adds pattern matching for the insert+shufflevector sequence so we can
generate dup instructions instead of the current TBL sequence.
Differential Revision: https://reviews.llvm.org/D59558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356526
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Amara Emerson [Tue, 19 Mar 2019 21:43:02 +0000 (21:43 +0000)]
[AArch64][GlobalISel] Make v4s32 G_IMPLICIT_DEF legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356525
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Reid Kleckner [Tue, 19 Mar 2019 21:40:59 +0000 (21:40 +0000)]
Remove MSVC compat hack since the inline keyword was added in 2015
Our minimum MSVC toolchain requirement is greater than 2015, so we don't
need this conditional macro anymore. New versions of MSVC apparently
have a header, xkeycheck.h, to check that keywords haven't been
redefined.
Fixes PR41144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356524
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 21:32:03 +0000 (21:32 +0000)]
[Remarks] Fix gcc build for r356519
Fails here:
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20046/steps/build%20stage%201/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356522
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Florian Hahn [Tue, 19 Mar 2019 21:18:59 +0000 (21:18 +0000)]
[DwarfDebug] Add triple to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356521
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Nikita Popov [Tue, 19 Mar 2019 21:12:21 +0000 (21:12 +0000)]
[InstSimplify] Add additional cmp of abs without nsw tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356520
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 21:11:07 +0000 (21:11 +0000)]
Reland "[Remarks] Add a new Remark / RemarkParser abstraction"
This adds a Remark class that allows us to share code when working with
remarks.
The C API has been updated to reflect this. Instead of the parser
generating C structs, it's now using a C++ object that is used through
opaque pointers in C. This gives us much more flexibility on what
changes we can make to the internal state of the object and interacts
much better with scenarios where the library is used through dlopen.
* C API updates:
* move from C structs to opaque pointers and functions
* the remark type is now an enum instead of a string
* unit tests updates:
* use mostly the C++ API
* keep one test for the C API
* rename to YAMLRemarksParsingTest
* a typo was fixed: AnalysisFPCompute -> AnalysisFPCommute.
* a new error message was added: "expected a remark tag."
* llvm-opt-report has been updated to use the C++ parser instead of the
C API
Differential Revision: https://reviews.llvm.org/D59049
Original llvm-svn: 356491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356519
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Robert Lougher [Tue, 19 Mar 2019 20:54:20 +0000 (20:54 +0000)]
Revert r356511 "[TailCallElim] Add tailcall elimination pass to LTO pipelines"
Due to buildbot failures (LLD tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356516
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Florian Hahn [Tue, 19 Mar 2019 20:37:06 +0000 (20:37 +0000)]
[DwarfDebug] Skip entries to big for 16 bit size field in Dwarf < 5.
Nothing prevents entries from being bigger than the 16 bit size field in
Dwarf < 5. For entries that are too big, just emit an empty entry
instead of crashing.
This fixes PR41038.
Reviewers: probinson, aprantl, davide
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D59518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356514
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Robert Lougher [Tue, 19 Mar 2019 20:24:28 +0000 (20:24 +0000)]
[TailCallElim] Add tailcall elimination pass to LTO pipelines
LTO provides additional opportunities for tailcall elimination due to
link-time inlining and visibility of nocapture attribute. Testing showed
negligible impact on compilation times.
Differential Revision: https://reviews.llvm.org/D58391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356511
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Philip Reames [Tue, 19 Mar 2019 20:10:00 +0000 (20:10 +0000)]
Demanded elements support for masked.load and masked.gather
Teach instcombine to propagate demanded elements through a masked load or masked gather instruction. This is in the broader context of improving vector pointer instcombine under https://reviews.llvm.org/D57140.
Differential Revision: https://reviews.llvm.org/D57372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356510
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Matt Arsenault [Tue, 19 Mar 2019 19:33:12 +0000 (19:33 +0000)]
CodeGen: Refactor regallocator command line and target selection
This will allow targets more flexibility to replace the
register allocator core passes. In a future commit,
AMDGPU will run the core register assignment passes
twice, and will also want to disallow using the
standard -regalloc option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356506
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Matt Arsenault [Tue, 19 Mar 2019 19:16:04 +0000 (19:16 +0000)]
RegAllocFast: Do not allocate registers for undef uses
Do not actually allocate a register for an undef use. Previously we we
would create unnecessary reload instruction for undef uses where the
register wasn't live.
Patch by Matthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356501
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Matt Arsenault [Tue, 19 Mar 2019 19:01:34 +0000 (19:01 +0000)]
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
The 2nd loop calculates spill costs but reports free registers as cost
0 anyway, so there is little benefit from having a separate early
loop.
Surprisingly this is not NFC, as many register are marked regDisabled
so the first loop often picks up later registers unnecessarily instead
of the first one available in the allocation order...
Patch by Matthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356499
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Simon Pilgrim [Tue, 19 Mar 2019 18:55:46 +0000 (18:55 +0000)]
Fix for ABS legalization on PPC buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356498
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Philip Reames [Tue, 19 Mar 2019 18:27:18 +0000 (18:27 +0000)]
Allow unordered loads to be considered invariant in CodeGen
The actual code change is fairly straight forward, but exercising it isn't. First, it turned out we weren't adding the appropriate flags in SelectionDAG. Second, it turned out that we've got some optimization gaps, so obvious test cases don't work.
My first attempt (in atomic-unordered.ll) points out a deficiency in our peephole-opt folding logic which I plan to fix separately. Instead, I'm exercising this through MachineLICM.
Differential Revision: https://reviews.llvm.org/D59375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356494
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 18:21:43 +0000 (18:21 +0000)]
Revert "[Remarks] Add a new Remark / RemarkParser abstraction"
This reverts commit
51dc6a8c84cd6a58562e320e1828a0158dbbf750.
Breaks
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20034/steps/build%20stage%201/logs/stdio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356492
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 18:09:51 +0000 (18:09 +0000)]
[Remarks] Add a new Remark / RemarkParser abstraction
This adds a Remark class that allows us to share code when working with
remarks.
The C API has been updated to reflect this. Instead of the parser
generating C structs, it's now using a C++ object that is used through
opaque pointers in C. This gives us much more flexibility on what
changes we can make to the internal state of the object and interacts
much better with scenarios where the library is used through dlopen.
* C API updates:
* move from C structs to opaque pointers and functions
* the remark type is now an enum instead of a string
* unit tests updates:
* use mostly the C++ API
* keep one test for the C API
* rename to YAMLRemarksParsingTest
* a typo was fixed: AnalysisFPCompute -> AnalysisFPCommute.
* a new error message was added: "expected a remark tag."
* llvm-opt-report has been updated to use the C++ parser instead of the
C API
Differential Revision: https://reviews.llvm.org/D59049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356491
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Nikita Popov [Tue, 19 Mar 2019 17:53:56 +0000 (17:53 +0000)]
[ValueTracking] Use computeConstantRange() for unsigned add/sub overflow
Improve computeOverflowForUnsignedAdd/Sub in ValueTracking by
intersecting the computeConstantRange() result into the ConstantRange
created from computeKnownBits(). This allows us to detect some
additional never/always overflows conditions that can't be determined
from known bits.
This revision also adds basic handling for constants to
computeConstantRange(). Non-splat vectors will be handled in a followup.
The signed case will also be handled in a followup, as it needs some
more groundwork.
Differential Revision: https://reviews.llvm.org/D59386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356489
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Peter Collingbourne [Tue, 19 Mar 2019 17:30:59 +0000 (17:30 +0000)]
gn build: Merge r356387.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356485
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Peter Collingbourne [Tue, 19 Mar 2019 17:30:50 +0000 (17:30 +0000)]
gn build: Merge r356451.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356484
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Simon Pilgrim [Tue, 19 Mar 2019 17:23:25 +0000 (17:23 +0000)]
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - handle repeated shift amounts
If a value with multiple uses is only ever used for SSE shift amounts then we know that only the bottom 64-bits are needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356483
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Philip Reames [Tue, 19 Mar 2019 17:20:49 +0000 (17:20 +0000)]
[AtomicExpand] Fix a crash bug when lowering unordered loads to cmpxchg
Add tests for wider atomic loads and stores. In the process, fix a crasher where we appearently handled unorder stores, but not loads, when lowering to cmpxchg idioms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356482
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Simon Atanasyan [Tue, 19 Mar 2019 17:01:24 +0000 (17:01 +0000)]
[MIPS][microMIPS] Enable dynamic stack realignment
Dynamic stack realignment was disabled on micromips by checking if
target has standard encoding. We simply change the condition to skip
Mips16 only.
Patch by Mirko Brkusanin.
Differential Revision: http://reviews.llvm.org/D59499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356478
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Jordan Rupprecht [Tue, 19 Mar 2019 16:52:40 +0000 (16:52 +0000)]
[NFC] Fix unused variable in release builds
This was introduced in rL356468.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356477
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Justin Bogner [Tue, 19 Mar 2019 16:52:00 +0000 (16:52 +0000)]
[DAGCombine] Fix a miscompile when reducing BUILD_VECTORs to a shuffle
In r311255 we added a case where we split vectors whose elements are
all derived from the same input vector so that we could shuffle it
more efficiently. In doing so, createBuildVecShuffle was taught to
adjust for the fact that all indices would be based off of the first
vector when this happens, but it's possible for the code that checked
that to fire incorrectly if we happen to have a BUILD_VECTOR of
extracts from subvectors and don't hit this new optimization.
Instead of trying to detect if we've split the vector by checking if
we have extracts from the same base vector, we can just pass that
information into createBuildVecShuffle, avoiding the miscompile.
Differential Revision: https://reviews.llvm.org/D59507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356476
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Simon Pilgrim [Tue, 19 Mar 2019 16:49:59 +0000 (16:49 +0000)]
Fix unused variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356474
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Philip Reames [Tue, 19 Mar 2019 16:46:56 +0000 (16:46 +0000)]
[Tests] Update to newer ISA
There are some issues w/missed opts on older platforms, but that's not the purpose of this test. Using a newer API points out that some TODOs are already handled, and allows addition of tests to exercise other issues (future patch.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356473
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Sanjay Patel [Tue, 19 Mar 2019 16:39:17 +0000 (16:39 +0000)]
[InstCombine] fold logic-of-nan-fcmps (PR41069)
Combine 2 fcmps that are checking for nan-ness:
and (fcmp ord X, 0), (and (fcmp ord Y, 0), Z) --> and (fcmp ord X, Y), Z
or (fcmp uno X, 0), (or (fcmp uno Y, 0), Z) --> or (fcmp uno X, Y), Z
This is an exact match for a minimal reassociation pattern.
If we want to handle this more generally that should go in
the reassociate pass and allow removing this code.
This should fix:
https://bugs.llvm.org/show_bug.cgi?id=41069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356471
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Neil Henning [Tue, 19 Mar 2019 16:32:24 +0000 (16:32 +0000)]
[AMDGPU] Add convergent attribute to WWM.
Add the convergent attribute to the WWM intrinsic to stop it ever being
sunk out of cfg.
Differential Revision: https://reviews.llvm.org/D59536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356470
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Simon Pilgrim [Tue, 19 Mar 2019 16:24:55 +0000 (16:24 +0000)]
[SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGBuilder::visitSelect
These changes are related to PR37743 and include:
SelectionDAGBuilder::visitSelect handles the unary SelectPatternFlavor::SPF_ABS case to build ABS node.
Delete the redundant recognizer of the integer ABS pattern from the DAGCombiner.
Add promoting the integer ABS node in the LegalizeIntegerType.
Expand-based legalization of integer result for the ABS nodes.
Expand-based legalization of ABS vector operations.
Add some integer abs testcases for different typesizes for Thumb arch
Add the custom ABS expanding and change the SAD pattern recognizer for X86 arch: The i64 result of the ABS is expanded to:
tmp = (SRA, Hi, 31)
Lo = (UADDO tmp, Lo)
Hi = (XOR tmp, (ADDCARRY tmp, hi, Lo:1))
Lo = (XOR tmp, Lo)
The "detectZextAbsDiff" function is changed for the recognition of pattern with the ABS node. Given a ABS node, detect the following pattern:
(ABS (SUB (ZERO_EXTEND a), (ZERO_EXTEND b))).
Change integer abs testcases for codegen with the ABS node support for AArch64.
Indicate that the ABS is legal for the i64 type when the NEON is supported.
Change the integer abs testcases to show changing of codegen.
Add combine and legalization of ABS nodes for Thumb arch.
Extend 'matchSelectPattern' to recognize the ABS patterns with ICMP_SGE condition.
For discussion, see https://bugs.llvm.org/show_bug.cgi?id=37743
Patch by: @ikulagin (Ivan Kulagin)
Differential Revision: https://reviews.llvm.org/D49837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356468
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Jordan Rupprecht [Tue, 19 Mar 2019 16:09:54 +0000 (16:09 +0000)]
[llvm-ar] Support N [count] modifier
Summary:
GNU ar supports the 'N' count modifier for the extract (x) and delete (d) operations. When an archive contains multiple members with the same name, this can be used to extract (or delete) them individually. For example:
```
$ llvm-ar t archive.a
foo
foo
$ llvm-ar x archive.a
-> Writes foo twice, overwriting it the second time :( :(
$ llvm-ar xN 1 archive.a foo && mv foo foo.1
$ llvm-ar xN 2 archive.a foo && mv foo foo.2
-> Write foo twice, renaming it in between invocations to preserve all versions
```
Reviewers: ruiu, MaskRay
Reviewed By: ruiu, MaskRay
Subscribers: jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356466
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Ryan Taylor [Tue, 19 Mar 2019 16:07:00 +0000 (16:07 +0000)]
[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
Summary:
Add buffer store/load 8/16 overloaded intrinsics for buffer, raw_buffer and struct_buffer
Change-Id: I166a29f071b2ff4e4683fb0392564b1f223ac61d
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356465
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Neil Henning [Tue, 19 Mar 2019 15:50:24 +0000 (15:50 +0000)]
[AMDGPU] Ban i8 min3 promotion.
I found this really weird WWM-related case whereby through the WWM
transformations our isel lowering was trying to promote 2 min's into a
min3 for the i8 type, which our hardware doesn't support.
The new min3_i8.ll test case would previously spew the error:
PromoteIntegerResult #0: t69: i8 = SMIN3 t70, Constant:i8<0>, t68
Before the simple fix to our isel lowering to not do it for i8 MVT's.
Differential Revision: https://reviews.llvm.org/D59543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356464
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Teresa Johnson [Tue, 19 Mar 2019 15:43:56 +0000 (15:43 +0000)]
[InstCombine] Add missing test for icmp transformation (NFC)
This was split out of D59378. There was no testing for the EQ case in
foldICmpWithDominatingICmp, add one here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356463
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Simon Atanasyan [Tue, 19 Mar 2019 15:15:35 +0000 (15:15 +0000)]
[mips] Fix crash on recursive using of .set
Switch to the `MCParserUtils::parseAssignmentExpression` for parsing
assignment expressions in the `.set` directive reduces code and allows
to print an error message instead of crashing in case of incorrect
recursive using of the `.set`.
Fix for the bug https://bugs.llvm.org/show_bug.cgi?id=41053.
Differential Revision: http://reviews.llvm.org/D59452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356461
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Markus Lavin [Tue, 19 Mar 2019 15:15:28 +0000 (15:15 +0000)]
[DebugInfo] Move test files added in r356451
Moved the X86 dependant .ll tests added in r356451 from
test/DebugInfo/Generic to test/DebugInfo/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356460
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Simon Pilgrim [Tue, 19 Mar 2019 14:08:23 +0000 (14:08 +0000)]
[InstSimplify] SimplifyICmpInst - icmp eq/ne %X, undef -> undef
As discussed on PR41125 and D59363, we have a mismatch between icmp eq/ne cases with an undef operand:
When the other operand is constant we fold to undef (handled in ConstantFoldCompareInstruction)
When the other operand is non-constant we fold to a bool constant based on isTrueWhenEqual (handled in SimplifyICmpInst).
Neither is really wrong, but this patch changes the logic in SimplifyICmpInst to consistently fold to undef.
The NewGVN test change is annoying (as with most heavily reduced tests) but AFAICT I have kept the purpose of the test based on rL291968.
Differential Revision: https://reviews.llvm.org/D59541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356456
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Petar Jovanovic [Tue, 19 Mar 2019 13:49:03 +0000 (13:49 +0000)]
[DebugInfoMetadata] Move main subprogram DIFlag into DISPFlags
Moving subprogram specific flags into DISPFlags makes IR code more readable.
In addition, we provide free space in DIFlags for other
'non-subprogram-specific' debug info flags.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D59288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356454
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Sanjay Patel [Tue, 19 Mar 2019 13:39:29 +0000 (13:39 +0000)]
[InstCombine] add FMF to tests for extra coverage; NFC
ninf is probably the only relevant possible flag here
(nnan allows simplification and nsz never makes a difference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356453
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Markus Lavin [Tue, 19 Mar 2019 13:16:28 +0000 (13:16 +0000)]
[DebugInfo] Introduce DW_OP_LLVM_convert
Introduce a DW_OP_LLVM_convert Dwarf expression pseudo op that allows
for a convenient way to perform type conversions on the Dwarf expression
stack. As an additional bonus it paves the way for using other Dwarf
v5 ops that need to reference a base_type.
The new DW_OP_LLVM_convert is used from lib/Transforms/Utils/Local.cpp
to perform sext/zext on debug values but mainly the patch is about
preparing terrain for adding other Dwarf v5 ops that need to reference a
base_type.
For Dwarf v5 the op maps to DW_OP_convert and for earlier versions a
complex shift & mask pattern is generated to emulate sext/zext.
This is a recommit of r356442 with trivial fixes for the failing tests.
Differential Revision: https://reviews.llvm.org/D56587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356451
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Simon Pilgrim [Tue, 19 Mar 2019 11:44:22 +0000 (11:44 +0000)]
[InstCombine] Regenerate + add icmp with undef tests
Better test coverage for PR41125 and D59363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356448
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Markus Lavin [Tue, 19 Mar 2019 09:17:28 +0000 (09:17 +0000)]
Revert "[DebugInfo] Introduce DW_OP_LLVM_convert"
This reverts commit
1cf4b593a7ebd666fc6775f3bd38196e8e65fafe.
Build bots found failing tests not detected locally.
Failing Tests (3):
LLVM :: DebugInfo/Generic/convert-debugloc.ll
LLVM :: DebugInfo/Generic/convert-inlined.ll
LLVM :: DebugInfo/Generic/convert-linked.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356444
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Serge Guelton [Tue, 19 Mar 2019 09:14:09 +0000 (09:14 +0000)]
Use response file when generating LLVM-C.dll
As discovered in D56774 the command line gets to long, so use a response file
to give the script the libs. This change has been tested and is confirmed
working for me.
Commited on behalf of Jakob Bornecrantz.
Differential Revision: https://reviews.llvm.org/D56781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356443
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Markus Lavin [Tue, 19 Mar 2019 08:48:19 +0000 (08:48 +0000)]
[DebugInfo] Introduce DW_OP_LLVM_convert
Introduce a DW_OP_LLVM_convert Dwarf expression pseudo op that allows
for a convenient way to perform type conversions on the Dwarf expression
stack. As an additional bonus it paves the way for using other Dwarf
v5 ops that need to reference a base_type.
The new DW_OP_LLVM_convert is used from lib/Transforms/Utils/Local.cpp
to perform sext/zext on debug values but mainly the patch is about
preparing terrain for adding other Dwarf v5 ops that need to reference a
base_type.
For Dwarf v5 the op maps to DW_OP_convert and for earlier versions a
complex shift & mask pattern is generated to emulate sext/zext.
Differential Revision: https://reviews.llvm.org/D56587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356442
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Heejin Ahn [Tue, 19 Mar 2019 05:26:33 +0000 (05:26 +0000)]
[WebAssembly] Small improvements in FixIrreducibleControlFlow (NFC)
Summary:
- Make some class member methods const
- Delete unnecessary includes
- Use a simpler form of `BuildMI`
Reviewers: kripken
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356440
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Heejin Ahn [Tue, 19 Mar 2019 05:10:39 +0000 (05:10 +0000)]
[WebAssembly] Improve readability of irreducibility tests
Summary:
This adds `preds` comment lines to BB names for readability, while also
fixes some of existing incorrect comment lines. Also deletes a few
unnecessary attributes. Autogenerated by `opt`.
Reviewers: kripken
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356439
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Heejin Ahn [Tue, 19 Mar 2019 05:07:33 +0000 (05:07 +0000)]
[WebAssembly] Rename methods according to instruction name changes (NFC)
Reviewers: tlively, sbc100
Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356438
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Heejin Ahn [Tue, 19 Mar 2019 05:02:30 +0000 (05:02 +0000)]
[WebAssembly] Add immarg attribute to intrinsics
Summary:
After r355981, intrinsic arguments that are immediate values should be
marked as `ImmArg`.
Reviewers: dschuff, tlively
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356437
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Thomas Lively [Tue, 19 Mar 2019 00:55:34 +0000 (00:55 +0000)]
[WebAssembly] Lower SIMD nnan setcc nodes
Summary:
Adds patterns to lower all the remaining setcc modes: lt, gt,
le, and ge. Fixes PR40912.
Reviewers: aheejin, sbc100, dschuff
Reviewed By: dschuff
Subscribers: jgravelle-google, hiraditya, sunfish, jdoerfert, llvm-commits, srj
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356431
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Nikita Popov [Mon, 18 Mar 2019 22:26:27 +0000 (22:26 +0000)]
Revert "[ValueTracking][InstSimplify] Support min/max selects in computeConstantRange()"
This reverts commit
106f0cdefb02afc3064268dc7a71419b409ed2f3.
This change impacts the AMDGPU smed3.ll and umed3.ll codegen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356424
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Kostya Serebryany [Mon, 18 Mar 2019 22:20:47 +0000 (22:20 +0000)]
[libFuzzer] document -len_control
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356422
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Craig Topper [Mon, 18 Mar 2019 22:06:19 +0000 (22:06 +0000)]
[X86] Add coverage for 16-bit and 64-bit versions of bsf/bsr/bt/btc/btr/bts in the assembly tests that are supposed to provide full coverage. Add coverage for cwtl/cltq/cwtd/cqto as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356420
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Craig Topper [Mon, 18 Mar 2019 22:06:14 +0000 (22:06 +0000)]
[X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356419
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Nikita Popov [Mon, 18 Mar 2019 21:35:19 +0000 (21:35 +0000)]
[ValueTracking][InstSimplify] Support min/max selects in computeConstantRange()
Add support for min/max flavor selects in computeConstantRange(),
which allows us to fold comparisons of a min/max against a constant
in InstSimplify. This was suggested by spatel as an alternative
approach to D59378. I've also added the infinite looping test from
that revision here.
Differential Revision: https://reviews.llvm.org/D59506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356415
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Nikita Popov [Mon, 18 Mar 2019 21:35:09 +0000 (21:35 +0000)]
[InstCombine] Add tests for add nuw + uaddo; NFC
Baseline tests for D59471 (InstCombine of `add nuw` and `uaddo` with
constants).
Patch by Dan Robertson.
Differential Revision: https://reviews.llvm.org/D59472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356414
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Craig Topper [Mon, 18 Mar 2019 21:33:59 +0000 (21:33 +0000)]
[X86] Allow any 8-bit immediate to be used with BT/BTC/BTR/BTS not just sign extended 8-bit immediates.
We need to allow [128,255] in addition to [-128, 127] to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356413
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Amara Emerson [Mon, 18 Mar 2019 21:29:21 +0000 (21:29 +0000)]
[GlobalISel] Include missing change from r356396
Forgot to add a change to relax some asserts in r356396.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356411
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Sam Clegg [Mon, 18 Mar 2019 21:21:12 +0000 (21:21 +0000)]
[WebAssembly] Don't override default implementation of isOffsetFoldingLegal. NFC.
The default implementation does we want and is going to more compatible
with dynamic linking (-fPIC) support that is planned.
This is NFC because currently we only build wasm with
`-relocation-model=static` which in turn means that the default
`isOffsetFoldingLegal` always returns true today.
Differential Revision: https://reviews.llvm.org/D54661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356410
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Nikita Popov [Mon, 18 Mar 2019 21:20:03 +0000 (21:20 +0000)]
[ValueTracking][InstSimplify] Move abs handling into computeConstantRange(); NFC
This is preparation for D59506. The InstructionSimplify abs handling
is moved into computeConstantRange(), which is the general place for
such calculations. This is NFC and doesn't affect the existing tests
in test/Transforms/InstSimplify/icmp-abs-nabs.ll.
Differential Revision: https://reviews.llvm.org/D59511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356409
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Nikita Popov [Mon, 18 Mar 2019 21:19:56 +0000 (21:19 +0000)]
[InstSimplify] Add additional icmp of min/max tests; NFC
These are baseline tests for D59506.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356408
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Craig Topper [Mon, 18 Mar 2019 20:43:15 +0000 (20:43 +0000)]
[X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be consistent with the ROR patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356407
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Craig Topper [Mon, 18 Mar 2019 20:43:09 +0000 (20:43 +0000)]
[X86] Replace uses of i64immSExt32_su with i64relocImmSExt32_su.
For the i8, i16, and i32 instructions we were using a relocImm. Presumably we should for i64 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356406
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Michael Liao [Mon, 18 Mar 2019 20:40:09 +0000 (20:40 +0000)]
[AMDGPU] Enable code selection using `s_mul_hi_u32`/`s_mul_hi_i32`.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356405
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Jake Ehrlich [Mon, 18 Mar 2019 20:35:18 +0000 (20:35 +0000)]
[llvm-objcopy] Make .build-id linking atomic
This change makes linking into .build-id atomic and safe to use.
Some users under particular workflows are reporting that this races
more than half the time under particular conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356404
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Nikita Popov [Mon, 18 Mar 2019 20:08:35 +0000 (20:08 +0000)]
[InstCombine] Improve with.overflow intrinsic tests; NFC
- Do not use unnamed values in saddo tests
- Add tests for canonicalization of a constant arg0
Patch by Dan Robertson.
Differential Revision: https://reviews.llvm.org/D59476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356403
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Sam Clegg [Mon, 18 Mar 2019 20:04:34 +0000 (20:04 +0000)]
Restore comment regarding why Reloc::PIC_ can't be PIC
The original change back in rL29307 explained this but it was
lost somewhere along the way.
Differential Revision: https://reviews.llvm.org/D59445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356402
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Alexandre Ganea [Mon, 18 Mar 2019 19:38:04 +0000 (19:38 +0000)]
Fix flat-error-unsupported-gpu-hsa test
Differential Revision: https://reviews.llvm.org/D59505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356400
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Tim Renouf [Mon, 18 Mar 2019 19:35:44 +0000 (19:35 +0000)]
[AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic
Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.
This involved adding a clamp operand to the affected instructions in MIR
and MC, and thus having to fix up several places in codegen and MIR
tests.
Differential Revision: https://reviews.llvm.org/D59267
Change-Id: Ic7775105f02a985b668fa658a0cd7837846a534e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356399
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Tim Renouf [Mon, 18 Mar 2019 19:25:39 +0000 (19:25 +0000)]
[AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers
This commit allows v_cndmask_b32_e64 with abs, neg source
modifiers on src0, src1 to be assembled and disassembled.
This does appear to be allowed, even though they are floating point
modifiers and the operand type is b32.
To do this, I added src0_modifiers and src1_modifiers to the
MachineInstr, which involved fixing up several places in codegen and mir
tests.
Differential Revision: https://reviews.llvm.org/D59191
Change-Id: I69bf4a8c73ebc65744f6110bb8fc4e937d79fbea
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356398
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Amara Emerson [Mon, 18 Mar 2019 19:20:10 +0000 (19:20 +0000)]
Revert r356304: remove subreg parameter from MachineIRBuilder::buildCopy()
After review comments, it was preferred to not teach MachineIRBuilder about
non-generic instructions beyond using buildInstr().
For AArch64 I've changed the buildCopy() calls to buildInstr() + a
separate addReg() call.
This also relaxes the MachineIRBuilder's COPY checking more because it may
not always have a SrcOp given to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356396
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Alexandre Ganea [Mon, 18 Mar 2019 19:13:23 +0000 (19:13 +0000)]
[DebugInfo][PDB] Don't write empty debug streams
Before, empty debug streams were written as 8 bytes (4 bytes signature + 4 bytes for the GlobalRefs count).
With this patch, unused empty streams aren't emitted anymore. Modules now encode 65535 as an 'unused stream' value, by convention.
Also fix the * Linker * contrib section which wasn't correctly emitted previously.
Differential Revision: https://reviews.llvm.org/D59502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356395
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Tim Renouf [Mon, 18 Mar 2019 19:00:46 +0000 (19:00 +0000)]
[MsgPack][AMDGPU] Fix unflushed raw_string_ostream bugs on windows expensive checks bot
This fixes a couple of unflushed raw_string_ostream bugs in recent
commits that only show up on a bot building on windows with expensive
checks.
Differential Revision: https://reviews.llvm.org/D59396
Change-Id: I9c6208325503b3ee0786b4b688e13fc24a15babf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356394
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Craig Topper [Mon, 18 Mar 2019 18:54:06 +0000 (18:54 +0000)]
[X86] Rename imm8_su/imm16_su/imm32_su to relocImm8_su/relocImm16_su/relocImm32_su/ to accurately reflect what they are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356393
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Warren Ristow [Mon, 18 Mar 2019 18:52:35 +0000 (18:52 +0000)]
[SCEV] Guard movement of insertion point for loop-invariants
This reinstates r347934, along with a tweak to address a problem with
PHI node ordering that that commit created (or exposed). (That commit
was reverted at r348426, due to the PHI node issue.)
Original commit message:
r320789 suppressed moving the insertion point of SCEV expressions with
dev/rem operations to the loop header in non-loop-invariant situations.
This, and similar, hoisting is also unsafe in the loop-invariant case,
since there may be a guard against a zero denominator. This is an
adjustment to the fix of r320789 to suppress the movement even in the
loop-invariant case.
This fixes PR30806.
Differential Revision: https://reviews.llvm.org/D57428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356392
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Adhemerval Zanella [Mon, 18 Mar 2019 18:50:58 +0000 (18:50 +0000)]
[AArch64] Small fix for getIntImmCost
It uses the generic AArch64_IMM::expandMOVImm to get the correct
number of instruction used in immediate materialization.
Reviewers: efriedma
Differential Revision: https://reviews.llvm.org/D58461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356391
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Adhemerval Zanella [Mon, 18 Mar 2019 18:45:57 +0000 (18:45 +0000)]
[AArch64] Optimize floating point materialization
This patch follows some ideas from r352866 to optimize the floating
point materialization even further. It changes isFPImmLegal to
considere up to 2 mov instruction or up to 5 in case subtarget has
fused literals.
The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but
the mov+fmov sequence is always better because of the reduced d-cache
pressure. The timings are still the same if you consider movw+movk+fmov
vs. adrp+ldr will be fused (although one instruction longer).
Reviewers: efriedma
Differential Revision: https://reviews.llvm.org/D58460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356390
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Adhemerval Zanella [Mon, 18 Mar 2019 18:40:07 +0000 (18:40 +0000)]
[TargetLowering] Add code size information on isFPImmLegal. NFC
This allows better code size for aarch64 floating point materialization
in a future patch.
Reviewers: evandro
Differential Revision: https://reviews.llvm.org/D58690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356389
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Adhemerval Zanella [Mon, 18 Mar 2019 18:23:23 +0000 (18:23 +0000)]
[AArch64] Refactor floating point materialization. NFC
It splits the login of actual instruction emission away from the logic
that figures out the appropriate sequence on AArch64ExpandPseudo::expandMOVImm.
The new function AArch64_IMM::expandMOVImm, which return the list of the
instructions to materialize the immediate constant, is implemented on a
separated unit because it will be used in a subsequent patch to optimize
floating point materialization.
Reviewers: efriedma
Differential Revision: https://reviews.llvm.org/D58915
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356387
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Craig Topper [Mon, 18 Mar 2019 17:59:59 +0000 (17:59 +0000)]
[X86] Remove the _alt forms of (V)CMP instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Similar to previous change done for VPCOM and VPCMP
Differential Revision: https://reviews.llvm.org/D59468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356384
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Sanjay Patel [Mon, 18 Mar 2019 17:37:05 +0000 (17:37 +0000)]
[InstCombine] add/adjust test for NaN checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356383
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Nirav Dave [Mon, 18 Mar 2019 17:02:38 +0000 (17:02 +0000)]
[DAG] Cleanup unused node in SimplifySelectCC.
Delete temporarily constructed node uses for analysis after it's use,
holding onto original input nodes. Ideally this would be rewritten
without making nodes, but this appears relatively complex.
Reviewers: spatel, RKSimon, craig.topper
Subscribers: jdoerfert, hiraditya, deadalnix, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356382
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Michael Liao [Mon, 18 Mar 2019 16:57:40 +0000 (16:57 +0000)]
[MVT] Fix typos in comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356381
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Neil Henning [Mon, 18 Mar 2019 14:44:28 +0000 (14:44 +0000)]
[AMDGPU] Add an experimental buffer fat pointer address space.
Add an experimental buffer fat pointer address space that is currently
unhandled in the backend. This commit reserves address space 7 as a
non-integral pointer repsenting the 160-bit fat pointer (128-bit buffer
descriptor + 32-bit offset) that is heavily used in graphics workloads
using the AMDGPU backend.
Differential Revision: https://reviews.llvm.org/D58957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356373
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Sanjay Patel [Mon, 18 Mar 2019 14:27:51 +0000 (14:27 +0000)]
[InstCombine] allow general vector constants for funnel shift to shift transforms
Follow-up to:
rL356338
rL356369
We can calculate an arbitrary vector constant minus the bitwidth, so there's
no need to limit this transform to scalars and splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356372
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George Rimar [Mon, 18 Mar 2019 14:27:41 +0000 (14:27 +0000)]
[llvm-objcopy] - Calculate the string table section sizes correctly.
This fixes the https://bugs.llvm.org/show_bug.cgi?id=40980.
Previously if string optimization occurred as a result of
StringTableBuilder's finalize() method, the size wasn't updated.
This hopefully also makes the interaction between sections during finalization
processes a bit more clear.
Differential revision: https://reviews.llvm.org/D59488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356371
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Sanjay Patel [Mon, 18 Mar 2019 14:10:11 +0000 (14:10 +0000)]
[InstCombine] extend rotate-left-by-constant canonicalization to funnel shift
Follow-up to:
rL356338
Rotates are a special case of funnel shift where the 2 input operands
are the same value, but that does not need to be a restriction for the
canonicalization when the shift amount is a constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356369
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Simon Pilgrim [Mon, 18 Mar 2019 13:55:28 +0000 (13:55 +0000)]
[SystemZ] Remove icmp undef from reduced tests
Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC)
Approved by @uweigand (Ulrich Weigand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356368
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Sanjay Patel [Mon, 18 Mar 2019 13:35:51 +0000 (13:35 +0000)]
[InstCombine] add funnel shift tests with arbitrary constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356367
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Roman Lebedev [Mon, 18 Mar 2019 11:32:37 +0000 (11:32 +0000)]
[llvm-exegesis] Separate tool options into three categories.
Results in much nicer -help output:
```
$ ./bin/llvm-exegesis -help
USAGE: llvm-exegesis [options]
OPTIONS:
Color Options:
-color - Use colors in output (default=autodetect)
General options:
-enable-cse-in-irtranslator - Should enable CSE in irtranslator
-enable-cse-in-legalizer - Should enable CSE in Legalizer
Generic Options:
-help - Display available options (-help-hidden for more)
-help-list - Display list of available options (-help-list-hidden for more)
-version - Display the version of this program
llvm-exegesis analysis options:
-analysis-clustering-epsilon=<number> - dbscan epsilon for benchmark point clustering
-analysis-clusters-output-file=<string> -
-analysis-display-unstable-clusters - if there is more than one benchmark for an opcode, said benchmarks may end up not being clustered into the same cluster if the measured performance characteristics are different. by default all such opcodes are filtered out. this flag will instead show only such unstable opcodes
-analysis-inconsistencies-output-file=<string> -
-analysis-inconsistency-epsilon=<number> - epsilon for detection of when the cluster is different from the LLVM schedule profile values
-analysis-numpoints=<uint> - minimum number of points in an analysis cluster
llvm-exegesis benchmark options:
-ignore-invalid-sched-class - ignore instructions that do not define a sched class
-mode=<value> - the mode to run
=latency - Instruction Latency
=inverse_throughput - Instruction Inverse Throughput
=uops - Uop Decomposition
=analysis - Analysis
-num-repetitions=<uint> - number of time to repeat the asm snippet
-opcode-index=<int> - opcode to measure, by index
-opcode-name=<string> - comma-separated list of opcodes to measure, by name
-snippets-file=<string> - code snippets to measure
llvm-exegesis options:
-benchmarks-file=<string> - File to read (analysis mode) or write (latency/uops/inverse_throughput modes) benchmark results. “-” uses stdin/stdout.
-mcpu=<string> - cpu name to use for pfm counters, leave empty to autodetect
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356364
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David Stenberg [Mon, 18 Mar 2019 11:27:32 +0000 (11:27 +0000)]
[DebugInfo] Ignore bitcasts when lowering stack arg dbg.values
Summary:
Look past bitcasts when looking for parameter debug values that are
described by frame-index loads in `EmitFuncArgumentDbgValue()`.
In the attached test case we would be left with an undef `DBG_VALUE`
for the parameter without this patch.
A similar fix was done for parameters passed in registers in D13005.
This fixes PR40777.
Reviewers: aprantl, vsk, jmorse
Reviewed By: aprantl
Subscribers: bjope, javed.absar, jdoerfert, llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D58831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356363
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Christof Douma [Mon, 18 Mar 2019 09:21:06 +0000 (09:21 +0000)]
[AArch64] Fix bug 35094 atomicrmw on Armv8.1-A+lse
Fixes https://bugs.llvm.org/show_bug.cgi?id=35094
The Dead register definition pass should leave alone the atomicrmw
instructions on AArch64 (LTE extension). The reason is the following
statement in the Arm ARM:
"The ST<OP> instructions, and LD<OP> instructions where the destination
register is WZR or XZR, are not regarded as doing a read for the purpose
of a DMB LD barrier."
A good example was given in the gcc thread by Will Deacon (linked in the
bugzilla ticket 35094):
P0 (atomic_int* y,atomic_int* x) {
atomic_store_explicit(x,1,memory_order_relaxed);
atomic_thread_fence(memory_order_release);
atomic_store_explicit(y,1,memory_order_relaxed);
}
P1 (atomic_int* y,atomic_int* x) {
atomic_fetch_add_explicit(y,1,memory_order_relaxed); // STADD
atomic_thread_fence(memory_order_acquire);
int r0 = atomic_load_explicit(x,memory_order_relaxed);
}
P2 (atomic_int* y) {
int r1 = atomic_load_explicit(y,memory_order_relaxed);
}
My understanding is that it is forbidden for r0 == 0 and r1 == 2 after
this test has executed. However, if the relaxed add in P1 compiles to
STADD and the subsequent acquire fence is compiled as DMB LD, then we
don't have any ordering guarantees in P1 and the forbidden result could
be observed.
Change-Id: I419f9f9df947716932038e1100c18d10a96408d0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356360
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Craig Topper [Mon, 18 Mar 2019 07:05:01 +0000 (07:05 +0000)]
[X86] Hopefully fix a tautological compare warning in printVecCompareInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356359
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Alex Bradbury [Mon, 18 Mar 2019 06:01:27 +0000 (06:01 +0000)]
[RISCV] Add ImmArg to intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356358
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