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Philippe Mathieu-Daudé [Thu, 26 Nov 2020 10:56:39 +0000 (11:56 +0100)]
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
LLD/SCD opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-13-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 26 Nov 2020 10:56:15 +0000 (11:56 +0100)]
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-12-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 26 Nov 2020 10:54:30 +0000 (11:54 +0100)]
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
LWLE/LWRE/SWLE/SWRE (EVA) opcodes have been removed from
the Release 6. Add a single decodetree entry for the opcodes,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-11-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 26 Nov 2020 10:54:56 +0000 (11:54 +0100)]
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
LWL/LWR/SWL/SWR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 26 Nov 2020 10:55:46 +0000 (11:55 +0100)]
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
CACHE/PREF opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-9-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 24 Nov 2020 10:53:46 +0000 (11:53 +0100)]
target/mips: Convert Rel6 COP1X opcode to decodetree
COP1x opcode has been removed from the Release 6.
Add a single decodetree entry for it, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-8-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 24 Nov 2020 14:17:25 +0000 (15:17 +0100)]
target/mips: Convert Rel6 Special2 opcode to decodetree
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-7-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 8 Dec 2020 18:01:01 +0000 (19:01 +0100)]
target/mips: Remove now unreachable LSA/DLSA opcodes code
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201208203704.243704-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 8 Dec 2020 18:00:44 +0000 (19:00 +0100)]
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-24-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 8 Dec 2020 17:59:36 +0000 (18:59 +0100)]
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-23-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 8 Dec 2020 17:55:47 +0000 (18:55 +0100)]
target/mips: Extract LSA/DLSA translation generators
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-22-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 30 Nov 2020 13:10:32 +0000 (14:10 +0100)]
target/mips: Use decode_ase_msa() generated from decodetree
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-21-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 21:24:40 +0000 (22:24 +0100)]
target/mips: Introduce decode tree bindings for MSA ASE
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-20-f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Tue, 15 Dec 2020 21:40:50 +0000 (22:40 +0100)]
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
Simplify gen_check_zero_element() by passing the TCGCond
argument along.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-25-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 16 Nov 2020 04:13:37 +0000 (05:13 +0100)]
target/mips: Extract MSA translation routines
Extract 2200 lines from the huge translate.c to a new file,
'msa_translate.c'. As there are too many inter-dependencies
we don't compile it as another object yet, but keep including
it in the big translate.o. We gain in code maintainability.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201120210844.
2625602-5-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 20:17:46 +0000 (21:17 +0100)]
target/mips: Declare gen_msa/_branch() in 'translate.h'
Make gen_msa() and gen_msa_branch() public declarations
so we can keep calling them once extracted from the big
translate.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-18-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Mon, 16 Nov 2020 04:56:44 +0000 (05:56 +0100)]
target/mips: Extract MSA helper definitions
Keep all MSA-related code altogether.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20201120210844.
2625602-4-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Sun, 22 Nov 2020 17:20:04 +0000 (18:20 +0100)]
target/mips: Extract MSA helpers from op_helper.c
We have ~400 lines of MSA helpers in the generic op_helper.c,
move them with the other helpers in 'msa_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201123204448.
3260804-5-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Mon, 30 Nov 2020 12:47:40 +0000 (13:47 +0100)]
target/mips: Move msa_reset() to msa_helper.c
translate_init.c.inc mostly contains CPU definitions.
msa_reset() doesn't belong here, move it with the MSA
helpers.
One comment style is updated to avoid checkpatch.pl warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-15-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Philippe Mathieu-Daudé [Mon, 30 Nov 2020 13:03:31 +0000 (14:03 +0100)]
target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD] -> BxZ(true)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 20:16:49 +0000 (21:16 +0100)]
target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
The gen_msa*() methods don't use the "CPUMIPSState *env"
argument. Remove it to simplify.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-9-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 20:12:53 +0000 (21:12 +0100)]
target/mips: Extract msa_translate_init() from mips_tcg_init()
The msa_wr_d[] registers are only initialized/used by MSA.
They are declared static. We want to move them to the new
'msa_translate.c' unit in few commits, without having to
declare them global (with extern).
Extract first the logic initialization of the MSA registers
from the generic initialization. We will later move this
function along with the MSA registers to the new C unit.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-8-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 20:11:00 +0000 (21:11 +0100)]
target/mips: Alias MSA vector registers on FPU scalar registers
Commits
863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
It is not very clear to have FPU registers displayed with MSA
register names, even if MSA ASE is not present.
Instead of aliasing FPU registers to the MSA ones (even when MSA
is absent), we now alias the MSA ones to the FPU ones (only when
MSA is present).
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-7-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 22:32:40 +0000 (23:32 +0100)]
target/mips: Remove now unused ASE_MSA definition
We don't use ASE_MSA anymore (replaced by ase_msa_available()
checking MSAP bit from CP0_Config3). Remove it.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 22:39:04 +0000 (23:39 +0100)]
target/mips: Simplify MSA TCG logic
Only decode MSA opcodes if MSA is present (implemented).
Now than check_msa_access() will only be called if MSA is
present, the only way to have MIPS_HFLAG_MSA unset is if
MSA is disabled (bit CP0C5_MSAEn cleared, see previous
commit). Therefore we can remove the 'reserved instruction'
exception.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-5-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 22:32:27 +0000 (23:32 +0100)]
target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
MSA presence is expressed by the MSAP bit of CP0_Config3.
We don't need to check anything else.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-4-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 22:57:02 +0000 (23:57 +0100)]
target/mips: Simplify msa_reset()
Call msa_reset() unconditionally, but only reset
the MSA registers if MSA is implemented.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 22:22:20 +0000 (23:22 +0100)]
target/mips: Introduce ase_msa_available() helper
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201208003702.
4088927-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 14 Dec 2020 23:54:34 +0000 (00:54 +0100)]
target/mips/translate: Expose check_mips_64() to 32-bit mode
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <
20201215225757.764263-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 9 Dec 2020 13:16:01 +0000 (14:16 +0100)]
target/mips/translate: Extract decode_opc_legacy() from decode_opc()
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201215225757.764263-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 22:45:09 +0000 (23:45 +0100)]
target/mips: Only build TCG code when CONFIG_TCG is set
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201206233949.
3783184-20-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 18:12:49 +0000 (19:12 +0100)]
target/mips: Extract FPU specific definitions to translate.h
Extract FPU specific definitions that can be used by
ISA / ASE / extensions to translate.h header.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-16-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 16:38:13 +0000 (17:38 +0100)]
target/mips: Declare generic FPU / Coprocessor functions in translate.h
Some FPU / Coprocessor translation functions / registers can be
used by ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-15-f4bug@amsat.org>
Philippe Mathieu-Daudé [Thu, 10 Dec 2020 19:44:23 +0000 (20:44 +0100)]
target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-12-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 14 Dec 2020 18:08:45 +0000 (19:08 +0100)]
target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
generate_exception_err(err=0) is simply generate_exception_end().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-11-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 29 Nov 2020 18:13:28 +0000 (19:13 +0100)]
target/mips/translate: Add declarations for generic code
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201207235539.
4070364-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Fri, 13 Nov 2020 18:27:28 +0000 (19:27 +0100)]
target/mips/translate: Extract DisasContext structure
Extract DisasContext to a new 'translate.h' header so
different translation files (ISA, ASE, extensions)
can use it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201207235539.
4070364-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 22:52:07 +0000 (23:52 +0100)]
target/mips: Rename translate_init.c as cpu-defs.c
This file is not TCG specific, contains CPU definitions
and is consumed by cpu.c. Rename it as such.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 22:28:48 +0000 (23:28 +0100)]
target/mips: Move mmu_init() functions to tlb_helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201206233949.
3783184-15-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 21:31:09 +0000 (22:31 +0100)]
target/mips: Fix code style for checkpatch.pl
We are going to move this code, fix its style first.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201206233949.
3783184-14-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 22:27:17 +0000 (23:27 +0100)]
target/mips: Rename helper.c as tlb_helper.c
This file contains functions related to TLB management,
rename it as 'tlb_helper.c'.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201206233949.
3783184-13-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 22:12:23 +0000 (23:12 +0100)]
target/mips: Move common helpers from helper.c to cpu.c
The rest of helper.c is TLB related. Extract the non TLB
specific functions to cpu.c, so we can rename helper.c as
tlb_helper.c in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 13 Dec 2020 16:36:01 +0000 (17:36 +0100)]
target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-5-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sun, 6 Dec 2020 22:20:27 +0000 (23:20 +0100)]
target/mips: Add !CONFIG_USER_ONLY comment after #endif
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-4-f4bug@amsat.org>
Philippe Mathieu-Daudé [Sat, 14 Nov 2020 18:03:11 +0000 (19:03 +0100)]
target/mips: Extract FPU helpers to 'fpu_helper.h'
Extract FPU specific helpers from "internal.h" to "fpu_helper.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20201120210844.
2625602-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 14 Dec 2020 14:07:13 +0000 (15:07 +0100)]
target/mips: Inline cpu_state_reset() in mips_cpu_reset()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201214183739.500368-2-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:34:42 +0000 (12:34 +0100)]
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
The MIPS ISA release 6 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-16-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:30:11 +0000 (12:30 +0100)]
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
The MIPS ISA release 5 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-15-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:29:34 +0000 (12:29 +0100)]
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-14-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:29:00 +0000 (12:29 +0100)]
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
The MIPS ISA release 2 is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-13-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:26:56 +0000 (12:26 +0100)]
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-12-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:14:00 +0000 (12:14 +0100)]
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
Use the single ISA_MIPS32R6 definition to check if the Release 6
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R6 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-11-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:09:08 +0000 (12:09 +0100)]
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
Use the single ISA_MIPS32R5 definition to check if the Release 5
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R5 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-10-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:08:40 +0000 (12:08 +0100)]
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
Use the single ISA_MIPS32R3 definition to check if the Release 3
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R3 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-9-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:06:51 +0000 (12:06 +0100)]
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-8-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 16:23:15 +0000 (17:23 +0100)]
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
Use the single ISA_MIPS32 definition to check if the Release 1
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R1 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-7-f4bug@amsat.org>
Philippe Mathieu-Daudé [Mon, 4 Jan 2021 10:50:15 +0000 (11:50 +0100)]
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
Directly check if the CPU supports 64-bit with the recently
added cpu_type_is_64bit() helper (inlined).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210104221154.
3127610-6-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:41:25 +0000 (12:41 +0100)]
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
MIPS 64-bit ISA is introduced with MIPS3.
Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA,
and the cpu_type_is_64bit() method to check if a CPU supports
this ISA (thus is 64-bit).
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210104221154.
3127610-5-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 22:59:07 +0000 (23:59 +0100)]
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210104221154.
3127610-4-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 11:23:38 +0000 (12:23 +0100)]
target/mips/mips-defs: Reorder CPU_MIPS5 definition
Move CPU_MIPS5 after CPU_MIPS4 :)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210104221154.
3127610-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Wed, 16 Dec 2020 22:56:58 +0000 (23:56 +0100)]
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
Remove a comment added 12 years ago but never used (commit
b6d96beda3a: "Use temporary registers for the MIPS FPU emulation").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20210104221154.
3127610-2-f4bug@amsat.org>
Jiaxun Yang [Tue, 15 Dec 2020 06:45:06 +0000 (14:45 +0800)]
target/mips/addr: Add translation helpers for KSEG1
It's useful for bootloader to do I/O operations.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <
20201215064507.30148-3-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 1 Dec 2020 11:41:39 +0000 (12:41 +0100)]
target/mips: Replace CP0_Config0 magic values by proper definitions
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201201132817.
2863301-3-f4bug@amsat.org>
Philippe Mathieu-Daudé [Tue, 1 Dec 2020 11:29:22 +0000 (12:29 +0100)]
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20201201132817.
2863301-2-f4bug@amsat.org>
Peter Maydell [Thu, 14 Jan 2021 09:54:29 +0000 (09:54 +0000)]
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-
20210113' into staging
Improvements to tcg constant handling.
Force utf8 for decodetree.
# gpg: Signature made Thu 14 Jan 2021 02:15:42 GMT
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-
20210113: (24 commits)
decodetree: Open files with encoding='utf-8'
tcg/aarch64: Use tcg_constant_vec with tcg vec expanders
tcg/ppc: Use tcg_constant_vec with tcg vec expanders
tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
tcg/i386: Use tcg_constant_vec with tcg vec expanders
tcg: Add tcg_reg_alloc_dup2
tcg: Remove movi and dupi opcodes
tcg/tci: Add special tci_movi_{i32,i64} opcodes
tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders
tcg: Use tcg_constant_{i32,i64} with tcg plugins
tcg: Use tcg_constant_{i32,i64} with tcg int expanders
tcg: Use tcg_constant_i32 with icount expander
tcg: Convert tcg_gen_dupi_vec to TCG_CONST
tcg/optimize: Use tcg_constant_internal with constant folding
tcg/optimize: Adjust TempOptInfo allocation
tcg/optimize: Improve find_better_copy
tcg: Introduce TYPE_CONST temporaries
tcg: Expand TempOptInfo to 64-bits
tcg: Rename struct tcg_temp_info to TempOptInfo
tcg: Expand TCGTemp.val to 64-bits
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 13 Jan 2021 19:18:28 +0000 (19:18 +0000)]
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-
20210113' into staging
qemu-macppc updates
# gpg: Signature made Wed 13 Jan 2021 13:02:20 GMT
# gpg: using RSA key
CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg: issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* remotes/mcayland/tags/qemu-macppc-
20210113:
macio: don't set user_creatable to false
macio: wire macio GPIOs to OpenPIC using sysbus IRQs
macio: move OpenPIC inside macio-newworld device
mac_newworld: delay wiring of PCI IRQs in New World machine
macio: move heathrow PIC inside macio-oldworld device
mac_oldworld: move initialisation of grackle before heathrow
mac_oldworld: remove duplicate bus check for PPC_INPUT(env)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Sun, 10 Jan 2021 00:02:40 +0000 (01:02 +0100)]
decodetree: Open files with encoding='utf-8'
When decodetree.py was added in commit
568ae7efae7, QEMU was
using Python 2 which happily reads UTF-8 files in text mode.
Python 3 requires either UTF-8 locale or an explicit encoding
passed to open(). Now that Python 3 is required, explicit
UTF-8 encoding for decodetree source files.
To avoid further problems with the user locale, also explicit
UTF-8 encoding for the generated C files.
Explicit both input/output are plain text by using the 't' mode.
This fixes:
$ /usr/bin/python3 scripts/decodetree.py test.decode
Traceback (most recent call last):
File "scripts/decodetree.py", line 1397, in <module>
main()
File "scripts/decodetree.py", line 1308, in main
parse_file(f, toppat)
File "scripts/decodetree.py", line 994, in parse_file
for line in f:
File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode
return codecs.ascii_decode(input, self.errors)[0]
UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 80:
ordinal not in range(128)
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Suggested-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <
20210110000240.761122-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 8 Sep 2020 00:47:31 +0000 (00:47 +0000)]
tcg/aarch64: Use tcg_constant_vec with tcg vec expanders
Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to
"t1 = -v2, t2 = c - v2". This avoids a serial dependency
between t1 and t2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 7 Sep 2020 23:46:21 +0000 (23:46 +0000)]
tcg/ppc: Use tcg_constant_vec with tcg vec expanders
Improve expand_vec_shi to use sign-extraction for MO_32.
This allows a single VSPLTISB instruction to load all of
the valid shift constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 1 Apr 2020 03:10:20 +0000 (20:10 -0700)]
tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 1 Apr 2020 03:03:16 +0000 (20:03 -0700)]
tcg/i386: Use tcg_constant_vec with tcg vec expanders
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 31 Mar 2020 09:33:21 +0000 (02:33 -0700)]
tcg: Add tcg_reg_alloc_dup2
There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 17 Apr 2020 20:22:43 +0000 (13:22 -0700)]
tcg: Remove movi and dupi opcodes
These are now completely covered by mov from a
TYPE_CONST temporary.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 17 Apr 2020 20:19:47 +0000 (13:19 -0700)]
tcg/tci: Add special tci_movi_{i32,i64} opcodes
The normal movi opcodes are going away. We need something
for TCI to use internally.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 4 Sep 2020 01:18:08 +0000 (18:18 -0700)]
tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 17 Apr 2020 17:31:49 +0000 (10:31 -0700)]
tcg: Use tcg_constant_{i32,i64} with tcg plugins
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 30 Mar 2020 03:07:08 +0000 (20:07 -0700)]
tcg: Use tcg_constant_{i32,i64} with tcg int expanders
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 17 Apr 2020 16:31:55 +0000 (09:31 -0700)]
tcg: Use tcg_constant_i32 with icount expander
We must do this before we adjust tcg_out_movi_i32, lest the
under-the-hood poking that we do for icount be broken.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 7 Sep 2020 00:33:18 +0000 (17:33 -0700)]
tcg: Convert tcg_gen_dupi_vec to TCG_CONST
Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 31 Mar 2020 03:42:43 +0000 (20:42 -0700)]
tcg/optimize: Use tcg_constant_internal with constant folding
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 31 Mar 2020 02:52:02 +0000 (19:52 -0700)]
tcg/optimize: Adjust TempOptInfo allocation
Do not allocate a large block for indexing. Instead, allocate
for each temporary as they are seen.
In general, this will use less memory, if we consider that most
TBs do not touch every target register. This also allows us to
allocate TempOptInfo for new temps created during optimization.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 23 Apr 2020 16:02:23 +0000 (09:02 -0700)]
tcg/optimize: Improve find_better_copy
Prefer TEMP_CONST over anything else.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 30 Mar 2020 01:55:52 +0000 (18:55 -0700)]
tcg: Introduce TYPE_CONST temporaries
These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.
Not used yet, this is all infrastructure.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 6 Sep 2020 23:21:32 +0000 (16:21 -0700)]
tcg: Expand TempOptInfo to 64-bits
This propagates the extended value of TCGTemp.val that we did before.
In addition, it will be required for vector constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 31 Mar 2020 00:44:30 +0000 (17:44 -0700)]
tcg: Rename struct tcg_temp_info to TempOptInfo
Fix this name vs our coding style.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 6 Sep 2020 18:31:44 +0000 (11:31 -0700)]
tcg: Expand TCGTemp.val to 64-bits
This will reduce the differences between 32-bit and 64-bit hosts,
allowing full 64-bit constants to be created with the same interface.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 29 Mar 2020 17:40:49 +0000 (10:40 -0700)]
tcg: Add temp_readonly
In most, but not all, places that we check for TEMP_FIXED,
we are really testing that we do not modify the temporary.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 29 Mar 2020 17:11:56 +0000 (10:11 -0700)]
tcg: Consolidate 3 bits into enum TCGTempKind
The temp_fixed, temp_global, temp_local bits are all related.
Combine them into a single enumeration.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 31 Mar 2020 08:02:08 +0000 (01:02 -0700)]
tcg: Increase tcg_out_dupi_vec immediate to int64_t
While we don't store more than tcg_target_long in TCGTemp,
we shouldn't be limited to that for code generation. We will
be able to use this for INDEX_op_dup2_vec with 2 constants.
Also pass along the minimal vece that may be said to apply
to the constant. This allows some simplification in the
various backends.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 31 Mar 2020 12:43:23 +0000 (05:43 -0700)]
tcg: Use tcg_out_dupi_vec from temp_load
Having dupi pass though movi is confusing and arguably wrong.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Peter Maydell [Wed, 13 Jan 2021 14:19:24 +0000 (14:19 +0000)]
Merge remote-tracking branch 'remotes/armbru/tags/pull-yank-2021-01-13' into staging
Yank patches patches for 2021-01-13
# gpg: Signature made Wed 13 Jan 2021 09:25:46 GMT
# gpg: using RSA key
354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-yank-2021-01-13:
tests/test-char.c: Wait for the chardev to connect in char_socket_client_dupid_test
io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown
io/channel-tls.c: make qio_channel_tls_shutdown thread-safe
migration: Add yank feature
chardev/char-socket.c: Add yank feature
block/nbd.c: Add yank feature
Introduce yank feature
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:19 +0000 (17:56 +0000)]
macio: don't set user_creatable to false
Now that all of the object property links to the heathrow PIC and OpenPIC have
been removed from the macio devices, it is safe to allow the macio-oldworld
and macio-neworld devices to be marked as user_creatable.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20201229175619.6051-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:18 +0000 (17:56 +0000)]
macio: wire macio GPIOs to OpenPIC using sysbus IRQs
This both allows the wiring to be done as Ben suggested in his original comment in
gpio.c and also enables the OpenPIC object property link to be removed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20201229175619.6051-7-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:17 +0000 (17:56 +0000)]
macio: move OpenPIC inside macio-newworld device
The OpenPIC device is located within the macio device on real hardware so make it
a child of the macio-newworld device. This also removes the need for setting and
checking a separate PIC object property link on the macio-newworld device which
currently causes the automated QOM introspection tests to fail.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20201229175619.6051-6-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:16 +0000 (17:56 +0000)]
mac_newworld: delay wiring of PCI IRQs in New World machine
In order to move the OpenPIC device to the macio device, the PCI bus needs to be
initialised before the macio device and also before wiring the OpenPIC IRQs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20201229175619.6051-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:15 +0000 (17:56 +0000)]
macio: move heathrow PIC inside macio-oldworld device
The heathrow PIC is located within the macio device on real hardware so make it
a child of the macio-oldworld device. This also removes the need for setting and
checking a separate PIC object property link on the macio-oldworld device which
currently causes the automated QOM introspection tests to fail.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20201229175619.6051-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:14 +0000 (17:56 +0000)]
mac_oldworld: move initialisation of grackle before heathrow
In order to move the heathrow PIC to the macio device, the PCI bus needs to be
initialised before the macio device and also before wiring the PIC IRQs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20201229175619.6051-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Tue, 29 Dec 2020 17:56:13 +0000 (17:56 +0000)]
mac_oldworld: remove duplicate bus check for PPC_INPUT(env)
This condition will have already been caught when wiring the heathrow PIC
IRQs to the CPU.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <
20201229175619.6051-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Lukas Straub [Mon, 28 Dec 2020 15:09:02 +0000 (16:09 +0100)]
tests/test-char.c: Wait for the chardev to connect in char_socket_client_dupid_test
A connecting chardev object has an additional reference by the connecting
thread, so if the chardev is still connecting by the end of the test,
then the chardev object won't be freed. This in turn means that the yank
instance won't be unregistered and when running the next test-case
yank_register_instance will abort, because the yank instance is
already/still registered.
Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <
1445e97a5800e3f2ba024ad52b500a0315701632.
1609167865.git.lukasstraub2@web.de>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Lukas Straub [Mon, 28 Dec 2020 15:08:59 +0000 (16:08 +0100)]
io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown
Migration and yank code assume that qio_channel_shutdown is thread
-safe and can be called from qmp oob handler. Document this after
checking the code.
Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <
32b8c27e256da043f0f00db05bd7ab8fbc506070.
1609167865.git.lukasstraub2@web.de>
Signed-off-by: Markus Armbruster <armbru@redhat.com>