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Francisco Jerez [Fri, 1 Jul 2016 04:15:26 +0000 (21:15 -0700)]
i965: Make room in the batch epilogue for three more pipe controls.
Review carefully, it sucks to have to keep track of the number of
command packet dwords emitted in the batch epilogue manually. The
MI_REPORT_PERF_COUNT_BATCH_DWORDS calculation was obviously wrong.
Cc: "12.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
0bd3a121c6ea818b656082676f992b41204c5b41)
Francisco Jerez [Fri, 1 Jul 2016 02:41:49 +0000 (19:41 -0700)]
i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.
There were two places in the driver doing a pipe control VF cache
flush, one of them was missing this workaround, move it down into
brw_emit_pipe_control_flush to make sure we don't miss it again.
Cc: "12.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
(cherry picked from commit
a10879f48cedb1ef906becba0abad0af27482f34)
Ian Romanick [Tue, 14 Jun 2016 21:38:04 +0000 (14:38 -0700)]
glsl: Pack integer and double varyings as flat even if interpolation mode is none
v2: Also update varying_matches::compute_packing_class(). Suggested by
Timothy Arceri.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96358
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
3119871bd9558e5881466b70a4c366d2f83bba82)
Ian Romanick [Fri, 10 Jun 2016 15:01:30 +0000 (08:01 -0700)]
mesa: Strip arrayness from interface block names in some IO validation
Outputs from the vertex shader need to be able to match
per-vertex-arrayed inputs of later stages. Acomplish this by stripping
one level of arrayness from the names and types of outputs going to a
per-vertex-arrayed stage.
v2: Add missing checks for TESS_EVAL->GEOMETRY. Noticed by Timothy
Arceri.
v3: Use a slightly simpler stage check suggested by Ilia.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96358
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Cc: Gregory Hainaut <gregory.hainaut@gmail.com>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
73a6a4ce4975016d4f86d644b31d30bb6d3a38f8)
Emil Velikov [Fri, 8 Jul 2016 23:02:13 +0000 (00:02 +0100)]
docs: add sha256 checksums for 12.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Jul 2016 22:45:44 +0000 (23:45 +0100)]
docs: add release notes for 12.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Jul 2016 22:40:03 +0000 (23:40 +0100)]
Update version to 12.0.1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Jul 2016 21:04:34 +0000 (22:04 +0100)]
radeon: reference the correct cdw/max_dw
With commit
f41f78cda10 ("radeonsi: drop the DRAW_PREAMBLE packet on
Polaris") we failed to attribute that the separate current/prev
radeon_winsys_cs_chunk(s) are not applicable/available in branch.
The latter of which introduced with commit
89ba076de4c ("radeon/winsys:
introduce radeon_winsys_cs_chunk").
Just drop "current." from the respective places to get things up and
running again.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96864
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Fri, 8 Jul 2016 22:47:39 +0000 (23:47 +0100)]
docs: add sha256 checksums for 12.0.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 7 Jul 2016 12:39:06 +0000 (13:39 +0100)]
docs: Update 12.0.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 7 Jul 2016 10:39:25 +0000 (11:39 +0100)]
Update version to 12.0.0(final)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Neha Bhende [Tue, 28 Jun 2016 19:59:19 +0000 (12:59 -0700)]
svga: Fix failures caused in fedora 24
SVGA_3D_CMD_DX_GENRATE_MIPMAP & SVGA_3D_CMD_DX_SET_PREDICATION commands
are not presents in fedora 24 kernel module. Because of this
reason application like supertuxkart are not running.
v2: Add few comments and code modifications suggested by Brian P.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit
7988513ac3d86ba367fbe44e73fe483ff96aaa29)
Ilia Mirkin [Fri, 1 Jul 2016 23:10:36 +0000 (19:10 -0400)]
glsl: don't try to lower non-gl builtins as if they were gl_FragData
If a shader has an output array, it will get treated as though it were
gl_FragData and rewritten into gl_out_FragData instances. We only want
this to happen on the actual gl_FragData and not everything else.
This is a small part of the problem pointed out by the below bug.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96765
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
a37e46323c7e18bec4160f2f66847c10b7041dc1)
Emil Velikov [Thu, 7 Jul 2016 10:51:13 +0000 (11:51 +0100)]
bugzilla_mesa.sh: Drop "Bug " from sed command
After a recent Bugzilla update the word is no longer in the title. Thus
the script ended up producing bogus HTML.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
f35f8464ecf35de769629d316db620472a92f995)
Akihiko Odaki [Sun, 26 Jun 2016 01:54:35 +0000 (10:54 +0900)]
mesa: don't install GLX files if GLX is not built
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Akihiko Odaki <akihiko.odaki.4i@stu.hosei.ac.jp>
[Emil Velikov: Drop guards around dri_interface.h, add stable tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
42968424fb4100f2035badf236b005cc8d62a592)
Mathias Fröhlich [Fri, 1 Jul 2016 05:13:46 +0000 (07:13 +0200)]
osmesa: Export OSMesaCreateContextAttribs.
Since the function is exported like any other
public api function and put in the header
as if you could link against it, export it also
from shared objects.
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
13affe0d3f2756771edfab301f31dc69185f91f7)
Rob Clark [Fri, 24 Jun 2016 18:28:51 +0000 (14:28 -0400)]
glsl: add driconf to zero-init unintialized vars
Some games are sloppy.. perhaps because it is defined behavior for DX or
perhaps because nv blob driver defaults things to zero.
So add driconf param to force uninitialized variables to default to zero.
This issue was observed with rust, from steam store. But has surfaced
elsewhere in the past.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
f78a6b1ce398a537d77c25b1a93f156109086975)
Rob Clark [Sat, 25 Jun 2016 00:03:37 +0000 (20:03 -0400)]
i965: don't drop const initializers in vector splitting
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
01ccb0d91e6f976716eb79cdb0fb11ad4d0b4fcf)
Rob Clark [Sun, 3 Jul 2016 15:16:28 +0000 (11:16 -0400)]
freedreno: fix crash on smaller gpus and higher resolutions
Devices with smaller GMEM size need more tiles. On db410c at 2048x1152,
glmark2 shadow needed ~330 tiles for fullscreen. Lets bump it up to
512. (Maybe with MRT you could end up needing more, but at that point
things are probably going to be painfully slow.)
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
7295428e4183cca1840e7ed02159519734fdab0a)
Emil Velikov [Wed, 6 Jul 2016 15:18:21 +0000 (16:18 +0100)]
anv: vulkan: remove the anv_device.$(OBJEXT) rule
Atm the actual rule will expand to foo.o which is used for static
libraries only.
Thus the automake manual recommendation [to use OBJEXT] won't help us,
since since we're working with a shared library.
Thus let's 'demote' the file and add it back to BUILT_SOURCES. This will
manage all the complexity for us, at the (existing expense) of working
only with the all, check and install targets.
The crazy (why the issue was hard to spot):
If the dependencies (.deps/*.Plo) are already created one can alter the
anv_device.$(OBJEXT) line and/or nuke it all together. That won't lead
to any warnings/issues, even though the Makefile is regenerated.
Moral of the story:
Always rm -rf top_builddir or don't resolve the dependencies manually
and use BUILT_SOURCES.
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96825
Fixes:
d7a604c3f7a ("anv: use cache uuid based on the build timestamp.")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Mark Janes <mark.a.janes@intel.com>
(cherry picked from commit
9618e2a24c18b5bbc9ff872d1f6870261d14dee5)
Emil Velikov [Fri, 24 Jun 2016 15:35:05 +0000 (16:35 +0100)]
anv: install the intel_icd.json to ${datarootdir} by default
As mentioned by the spec (and used by Archlinux and Debian) default to
${datarootdir} as opposed to ${sysconfdir} for the default location.
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
cbc37f72e3d0d50a2200d6e6520e22dd5992adb5)
Emil Velikov [Fri, 1 Jul 2016 16:17:13 +0000 (17:17 +0100)]
swr: automake: don't ship LLVM version specific generated sources
Otherwise things will fail to build, if the builder is using another
version of LLVM.
v2: annotate all the dependencies of builder_gen.h
v3: clean the generated files as needed
v4: comment cleanups (Tim)
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Tim Rowley <timothy.o.rowley@intel.com>
Tested-by: Chuck Atkins <chuck.atkins@kitware.com> (v2)
Reported-by: Chuck Atkins <chuck.atkins@kitware.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
744d0d8f3b03b43de19941595f9bd900c7e4b510)
Emil Velikov [Tue, 21 Jun 2016 17:05:23 +0000 (18:05 +0100)]
automake: don't mandate git_sha1.h/MESA_GIT_SHA1
It has proven subtle to get it right both from the build side POV (see
commit list below) and builders due to their varying workflows.
Furthermore it does not fully fulfil the reason why it was enforced -
to detect uniqueness between different builds, in order to distinguish
and invalidate Vulkan/GL caches.
With that having a much better solution (previous commit) we can drop
this solution.
This effectively reverts the following commits:
359d9dfec33 ("mesa: automake: add directory prefix for git_sha1.h")
2c424e00c39 ("mesa: automake: ensure that git_sha1.h.tmp has the right
attributes")
b7f7ec78435 ("mesa: automake: distclean git_sha1.h when building OOT")
8229fe68b5d ("automake: get in-tree `make distclean' working again.")
Cc: Timo Aaltonen <tjaalton@debian.org>
Cc: Haixia Shi <hshi@chromium.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit
22e9357028f45fab2563bdf2f3e171d4490a5d05)
Emil Velikov [Tue, 21 Jun 2016 16:43:35 +0000 (17:43 +0100)]
anv: use cache uuid based on the build timestamp.
Do not rely on the git sha1:
- its current truncated form makes it less unique
- it does not attribute for local (Vulkand or otherwise) changes
Use a timestamp produced at the time of build. It's perfectly unique,
unless someone explicitly thinkers with their system clock. Even then
chances of producing the exact same one are very small, if not zero.
v2: Remove .tmp rule. Its not needed since we want for the header to be
regenerated on each time we call make (Eric).
v3:
- Honour SOURCE_DATE_EPOCH, to make the build reproducible (Michel)
- Replace the generated header with a define, to prevent needless
builds on consecutive `make' and/or `make install' calls. (Dave)
v4:
- Keep the timestamp generation at make time. (Jason)
v5:
- Ensure that file is regenerated on incremental builds.
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Dave Airlie <airlied@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
addb099ce83c9b9909966a5cd364b85cedef1ee1)
Emil Velikov [Tue, 21 Jun 2016 17:21:54 +0000 (18:21 +0100)]
clover: conditionally use MESA_GIT_SHA1
Considering how hard/annoying it was for many peoples' workflow to
properly generate the macro, it will be demoted to conditionally
available with follow-up commits.
v2: Kill off gracious blank line (Vedran).
Cc: mesa-stable@lists.freedesktop.org
Cc: Vedran Miletić <vedran@miletic.net>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Reviewed-by: Vedran Miletić <vedran@miletic.net>
(cherry picked from commit
f98530b73960af1cb17da80159350fbe51352fea)
Dave Airlie [Tue, 5 Jul 2016 00:22:21 +0000 (10:22 +1000)]
Revert "st/glsl_to_tgsi: don't increase immediate index by 1."
This reverts commit
27d456cc87a01998c6fe1dbf45937e2ca6128495.
DOH, what seems right and what is right with fp64 are always
two different things.
This regressed:
spec@arb_gpu_shader_fp64@shader_storage@layout-std140-fp64-mixed-shader
on radeonsi
Reported-by: Michel Dänzer <michel@daenzer.net>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
cb728df9670d8399479db8502145bbc6f653cfb3)
Samuel Pitoiset [Mon, 4 Jul 2016 22:08:03 +0000 (00:08 +0200)]
nvc0/ir: reset the base offset for indirect images accesses
In presence of an indirect image access, the base offset should be
zeroed because the stride will be computed twice. This is a pretty
rare situation but it can happen when tex.r > 0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
f3b9fff3c362146da2e8e2c3eefa812ad166491c)
Samuel Pitoiset [Mon, 4 Jul 2016 11:12:20 +0000 (13:12 +0200)]
gm107/ir: fix sign bit emission for FADD32I
When emitting OP_SUB, the sign bit for FADD and FADD32I is not
at the same position. It's at position 45 for FADD but 51 for FADD32I.
This fixes the following piglit test:
tests/spec/arb_fragment_program/fdo30337b.shader_test
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
cb828b7b18d83cb2ea3dcaed54c1678616c56fc8)
Lionel Landwerlin [Mon, 4 Jul 2016 17:06:58 +0000 (18:06 +0100)]
anv/wsi: create swapchain images using specified image usage
The image usage specified by the caller of vkCreateSwapchainKHR should be
passed onto the internal image creation. Otherwise the driver might later
crash when the user tries to use the image as a combined sampler even though
the creation was explicitly created with VK_IMAGE_USAGE_TRANSFER_SRC_BIT.
Leaving the previous VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT as this might be
expected even if the swapchain is created without any flag.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96791
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
dbbc4fb4cc8792fa25125a9c828b649d61113362)
Dave Airlie [Mon, 6 Jun 2016 23:39:55 +0000 (09:39 +1000)]
st/glsl_to_tgsi: don't increase immediate index by 1.
Immediates are stored into a separate table, and are
consolidated, so if we get an immediate we don't need
to offset it as the index it has is correct.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
27d456cc87a01998c6fe1dbf45937e2ca6128495)
Nicolai Hähnle [Fri, 24 Jun 2016 15:54:51 +0000 (17:54 +0200)]
st/mesa: check the texture image level in st_texture_match_image
Otherwise, 1x1 images of arbitrarily high level are accepted.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96639#add_comment
Cc: 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
07cc838b105dd3f34526db73064f1f21b452240e)
Nicolai Hähnle [Fri, 24 Jun 2016 14:35:36 +0000 (16:35 +0200)]
st/mesa: an incomplete texture may have a zero-size first image
Fixes a regression introduced by commit
42624ea83 which triggered
an assertion in
dEQP-GLES2.functional.texture.completeness.cube.not_positive_level_0
While stImage must have a non-zero size as verified by the caller, we also
look at the size of the base image in an attempt to make a better guess at
the level0 size (this is important when the base image size is odd). However,
the base image may have a zero size even when it exists.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96629
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
0ba053b34c29106817568996ac53b41029cf4e4c)
Chuck Atkins [Wed, 29 Jun 2016 02:32:02 +0000 (22:32 -0400)]
gallium: Force blend color to 16-byte alignment
This aligns the 4-element color float array to 16 byte boundaries. This
should allow compiler vectorizers to generate better optimizations.
Also fixes broken vectorization generated by Intel compiler.
v2: Fixed indentation and added a lengthy comment explaining the
reason for the alignment.
Cc: <mesa-stable@lists.freedesktop.org>
Reported-by: Tim Rowley <timothy.o.rowley@intel.com>
Tested-by: Tim Rowley <timothy.o.rowley@intel.com>
Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit
d8d6091a846ac2a40a011d512d6d57f6c8442e6a)
Emil Velikov [Wed, 6 Jul 2016 11:05:48 +0000 (12:05 +0100)]
Revert "swr: Refactor checks for compiler feature flags"
This reverts commit
a380199e3968462da8291e8dda25888f19e86783.
Chuck Atkins [Tue, 28 Jun 2016 19:50:47 +0000 (15:50 -0400)]
swr: Refactor checks for compiler feature flags
Encapsulate the test for which flags are needed to get a compiler to
support certain features. Along with this, give various options to try
for AVX and AVX2 support. Ideally we want to use specific instruction
set feature flags, like -mavx2 for instance instead of -march=haswell,
but the flags required for certain compilers are different. This
allows, for AVX2 for instance, GCC to use -mavx2 -mfma -mbmi2 -mf16c
while the Intel compiler which doesn't support those flags can fall
back to using -march=core-avx2.
This addresses a bug where the Intel compiler will silently ignore the
AVX2 instruction feature flags and then potentially fail to build.
v2: Pass preprocessor-check argument as true-state instead of
false-state for clarity.
v3: Reduce AVX2 define test to just __AVX2__. Additional defines suchas
__FMA__, __BMI2__, and __F16C__ appear to be inconsistently defined
w.r.t thier availability.
v4: Fix C++11 flags being added globally and add more logic to
swr_require_cxx_feature_flags
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Tested-by: Tim Rowley <timothy.o.rowley@Intel.com>
Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
(cherry picked from commit
c1bf6692beb662e5749e5680e0ebd15af2cd032a)
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Ian Romanick [Fri, 17 Jun 2016 02:51:15 +0000 (19:51 -0700)]
mapi: Export all GLES 3.1 functions in libGLESv2.so
Khronos recommends that the GLES 3.1 library also be called libGLESv2.
It also requires that functions be statically linkable from that
library.
NOTE: Mesa has supported the EGL_KHR_get_all_proc_addresses extension
since at least Mesa 10.5, so applications targeting Linux should use
eglGetProcAddress to avoid problems running binaries on systems with
older, non-GLES 3.1 libGLESv2 libraries.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Cc: Mike Gorchak <mike.gorchak.qnx@gmail.com>
Reported-by: Mike Gorchak <mike.gorchak.qnx@gmail.com>
Acked-by: Chad Versace <chad.versace@intel.com>
(cherry picked from commit
5921f372c89a68fac6ddefc009442721d9df4db2)
sonjiang [Tue, 28 Jun 2016 15:23:41 +0000 (11:23 -0400)]
radeon/uvd: fix a h265 context size bug
Fixes a h265 video corruption bug which caused by uvd fw interface changes.
Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit
b928ff6f62144e20f4260cc1bb897f84b97dc925)
sonjiang [Mon, 27 Jun 2016 21:19:01 +0000 (17:19 -0400)]
radeon/uvd: separate uvd context buffer from DPB
Adapt driver for Polairs uvd firmware interface changes.
Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit
5c80354a23b7d770b2d61b626b9d62fdf764ca9d)
sonjiang [Wed, 29 Jun 2016 15:24:36 +0000 (11:24 -0400)]
radeon: uvd add uvd fw version for amdgpu
Because Polaris uvd fw interface changes, the driver need to check fw version
to apply right interface. This change is to add uvd fw version.
Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit
28f85eab49b28905e99a24fcb7f155063e5482e4)
[Emil Velikov: resolve trivial s/bool/boolean/ conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/radeon/radeon_winsys.h
Samuel Pitoiset [Mon, 27 Jun 2016 22:59:46 +0000 (00:59 +0200)]
gm107/ir: make sure that flagsDef is set when emitting setcond
Rely on the existence of a second destination when emitting a setcond
flag is dangerous, because this doesn't mean that the flag has been
correctly set. Instead rely on flagsDef like what emitX() does
for flagsSrc.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
cc97b6a34a81e58c29bed6dae06613b388506283)
Marek Olšák [Fri, 8 Apr 2016 10:15:50 +0000 (12:15 +0200)]
radeonsi: set PA_SU_SMALL_PRIM_FILTER_CNTL register on Polaris
This was missing.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit
c1dbc563f4a6a6b3438e97a2418922c22c1e77bf)
Kenneth Graunke [Sun, 26 Jun 2016 07:39:19 +0000 (00:39 -0700)]
i965: Make emit_urb_writes() not produce an EOT message for GS.
emit_urb_writes() contains code to emit an EOT write with no actual
data when there are no output varyings. This makes sense for the VS
and TES stages, where it's called once at the end of the program.
However, in the geometry shader stage, emit_urb_writes() is called once
for every EmitVertex(). We explicitly emit a URB write with EOT set at
the end of the shader, separately from this path. So we'd better not
terminate the thread. This could get us into trouble for shaders which
do EmitVertex() with no varyings followed by SSBO/image/atomic writes.
It also caused us to emit multiple sends with EOT set, which apparently
confuses the register allocator into not using g112-g127 for all but
the first one. This caused EU validation failures in OglGSCloth
shaders in shader-db. (The actual application was fine, but shader-db
thinks there are no outputs because it doesn't understand transform
feedback.)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit
7e7e501acf3ea609e3e2e8bb4091a5a20ae3adc2)
Kenneth Graunke [Fri, 24 Jun 2016 22:37:35 +0000 (15:37 -0700)]
glsl: Ignore ir_texture in lower_const_arrays_to_uniforms.
The only part of an ir_texture which can be an array is the
offsets array in textureGatherOffsets() calls. We don't want
to lower those, because they're required to remain constants.
Fixes textureGatherOffsets with Gallium drivers such as llvmpipe,
which commit
ef78df8d3b0cf540e5f08c8c2f6caa338b64a6c7 regressed.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit
a36a73a7b8a058c037cb0307b57ac97292953c58)
Samuel Pitoiset [Mon, 27 Jun 2016 22:13:05 +0000 (00:13 +0200)]
gm107/ir: add missing setcond flags for LOP variants
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
7b9b0967756c7d552f5ad80eba46379b2115e604)
Samuel Pitoiset [Mon, 27 Jun 2016 21:55:53 +0000 (23:55 +0200)]
gm107/ir: make use of LOP32I for all immediates
LOP only allows to emit 19-bits immediates.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
83a4f28dc27bd3f679d001fb0065940ad1f0f422)
Dave Airlie [Mon, 27 Jun 2016 20:45:28 +0000 (06:45 +1000)]
virgl: reduce some limits for now
These need to be passed from the host in caps structure if they
are larger, this fixes a bunch of tests on Intel hw, that I'd
put the limits too high for.
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
c7cc264ca97fe52688f26dd9249a68f574b18f56)
Samuel Pitoiset [Sun, 26 Jun 2016 22:52:46 +0000 (00:52 +0200)]
gm107/ir: make use of MOV32I for all immediates
MOV only allows to emit 19-bits immediates. This is similar to the
previous fix I did for IMUL.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
c7fa3c92f8fc9634af966e760a7601922cca43f6)
Jordan Justen [Sun, 12 Jun 2016 01:16:47 +0000 (18:16 -0700)]
i965: Use miptree to decide format on multi-plane images for gen < 7
This wasn't handled correctly for multi-plane images on gen < 7 in
727a9b24933d384f5440ed4318fb720ed11d6dd1.
Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96674
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
367cf3a2e3e51466429a6446ef14ed398a5fb948)
Samuel Pitoiset [Sun, 26 Jun 2016 16:42:22 +0000 (18:42 +0200)]
gm107/ir: make use of IMUL32I for all immediates
IMUL only allows to emit 19-bits immediates. This is similar to
d30768025a2283d4cc57930b784798bf278969da which fixed the same thing
for the GK110 emitter.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
b84c97587b4a838c32fb7ac4eab31a6ba4f69886)
Jordan Justen [Sun, 12 Jun 2016 01:16:47 +0000 (18:16 -0700)]
i965: Skip update_texture_surface when the plane doesn't exist
Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
(cherry picked from commit
727a9b24933d384f5440ed4318fb720ed11d6dd1)
Kenneth Graunke [Thu, 23 Jun 2016 00:01:12 +0000 (17:01 -0700)]
i965: Set fs_inst::base_mrf = -1 by default.
On MRF platforms, we need to set base_mrf to the first MRF value we'd
like to use for the message. On send-from-GRF platforms, we set it to
-1 to indicate that the operation doesn't use MRFs.
As MRF platforms are becoming increasingly a thing of the past, we've
forgotten to bother with this. It makes more sense to set it to -1 by
default, so we don't have to think about it for new code.
I searched the code for every instance of 'mlen =' in brw_fs*cpp, and
it appears that all MRF-based messages correctly program a base_mrf.
Forgetting to set base_mrf = -1 can confuse the register allocator,
causing it to think we have a large fake-MRF region. This ends up
moving the send-with-EOT registers earlier, sometimes even out of
the g112-g127 range, which is illegal. For example, this fixes
illegal sends in Piglit's arb_gpu_shader_fp64-layout-std430-fp64-shader,
which had SSBO messages with mlen > 0 but base_mrf == 0.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit
3e04e3758e90b2a65eaefb95155d43605f506961)
Marek Olšák [Fri, 24 Jun 2016 00:17:38 +0000 (02:17 +0200)]
radeonsi: fix fractional odd tessellation spacing for Polaris
ported from Vulkan (and no source explains why this is needed)
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
28d0d0c5b4ba9e636b540fafa3b9b2157e848757)
Marek Olšák [Fri, 24 Jun 2016 00:22:42 +0000 (02:22 +0200)]
radeonsi: fix a compute shader hang with big threadgroups on SI & CI
ported from Vulkan
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
1e8adb0ee43062210ca54821a880ef08bfdba1b7)
[Emil Velikov: resolve trivial conflict in si_launch_grid()]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/radeonsi/si_compute.c
Ilia Mirkin [Fri, 24 Jun 2016 02:33:59 +0000 (22:33 -0400)]
nvc0: when mapping directly, provide accurate xfer info + start
We were ignoring the incoming box parameters, and were providing totally
bogus stride/layer stride, and other bits, for when a non-full-surface
map was requested.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
b433cb51e50cab878cbaa023662bacd1f923a183)
Nicolai Hähnle [Thu, 23 Jun 2016 23:11:09 +0000 (01:11 +0200)]
radeonsi: drop the DRAW_PREAMBLE packet on Polaris
It will be removed from the firmware for the Polaris.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
0da890e62cf14fef273500491d14fb8d980fe452)
Nicolai Hähnle [Thu, 23 Jun 2016 13:00:53 +0000 (15:00 +0200)]
radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris
The non-MULTI variants will be removed in Polaris firmware.
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
2aa0485902cdb4cd02b72627a760b00e71bffecf)
Jordan Justen [Wed, 22 Jun 2016 17:34:08 +0000 (17:34 +0000)]
i965: Preserve the internal format of the dri image
Since the OpenGLES API is strict about the internal format matching
the for many operations, we need to preserve it.
See _mesa_es3_error_check_format_and_type in
src/mesa/main/glformats.c.
Fixes ES2-CTS.gtf.GL2ExtensionTests.egl_image.egl_image
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96351
Reported-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>
(cherry picked from commit
c36a363a2d305a987ef2ea843fe9fc860b576eed)
Kenneth Graunke [Wed, 22 Jun 2016 18:25:26 +0000 (11:25 -0700)]
i965: Implement rasterizer discard via SOL unless required for queries.
We currently use CL_INVOCATION_COUNT for the GL_PRIMITIVES_GENERATED
query, which involves passing all primitives to the clipper. When
rasterizer discard is enabled, we program the clipper in REJECT_ALL
mode, rather than using the SOL stage's "Rendering Disable" feature.
See commit
f09b91f78247409f54c975f56cb10d5f350fe64e for an explanation
of why we implement GL_PRIMITIVES_GENERATED this way.
Apparently the SOL stage's "Rendering Disable" feature is a lot faster
than having the clipper reject all primitives. It's safe to use when
no GL_PRIMITIVES_GENERATED query is active, as we don't care about
CL_INVOCATION_COUNT incrementing.
This patch makes us use SO_RENDERING_DISABLE when no query is active,
but continues falling back to the clipper in REJECT_ALL mode when the
queries are enabled. It brings back the perf_debug for the clipper
case (which I removed in commit
1f9445ff57b, thinking it wasn't useful).
Improves performance in Gl32GSCloth by 84.8303% +/- 2.07132% (n = 10)
on my Broadwell GT2 laptop.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
b0629e6894513a2c49a018bc3342a4e55435a236)
Kenneth Graunke [Wed, 22 Jun 2016 07:33:46 +0000 (00:33 -0700)]
i965: Combine 3DSTATE_STREAMOUT emitters and genX_sol_state atoms.
They're basically the same. Let's avoid the code duplication.
v2: Fix SO_BUFFER_ENABLE stuff to only happen on Gen < 8 (caught
by Jason Ekstrand).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
4db98f8beb990676be0833dda6c37566d0283911)
Kenneth Graunke [Sat, 30 Apr 2016 00:57:46 +0000 (17:57 -0700)]
glsl: Don't constant propagate arrays.
Constant propagation on arrays doesn't make a lot of sense. If the
array is only accessed with constant indexes, then opt_array_splitting
would split it up. Otherwise, we have variable indexing. If there's
multiple accesses, then constant propagation would end up replicating
the data.
The lower_const_arrays_to_uniforms pass creates uniforms for each
ir_constant with array type that it encounters. This means that it
creates redundant uniforms for each copy of the constant, which means
uploading too much data. It can even mean exceeding the maximum number
of uniform components, causing link failures.
We could try and teach the pass to de-duplicate the data by hashing
constants, but it makes more sense to avoid duplicating it in the first
place. We should promote constant arrays to uniforms, then propagate
the uniform access.
Fixes the TressFX shaders from Tomb Raider, which exceeded the maximum
number of uniform components by a huge margin and failed to link.
On Broadwell:
total instructions in shared programs:
9067702 ->
9068202 (0.01%)
instructions in affected programs: 10335 -> 10835 (4.84%)
helped: 10 (Hoard, Shadow of Mordor, Amnesia: The Dark Descent)
HURT: 20 (Natural Selection 2)
loops in affected programs: 4 -> 0
The hurt programs appear to no longer have a constarray uniform, as
all constants were successfully propagated. Apparently before this
patch, we successfully unrolled a loop containing array access, but
only after promoting constant arrays to uniforms. With this patch,
we unroll it first, so all array access is direct, and the array
is split up, and individual constants are propagated. This seems
better.
Cc: mesa-stable@lists.freedesktop.org
Reported-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
fb857b5eea43640bfe19dcc12a88a09a6448e55a)
Kenneth Graunke [Sat, 30 Apr 2016 01:05:26 +0000 (18:05 -0700)]
glsl: Make lower_const_arrays_to_uniforms work directly on constants.
There's really no point in looking at ir_dereference_array of a
constant. It also misses cases like:
(assign () (var_ref tmp) (constant (array ...) ...))
No changes in shader-db, but keeps it working after the next commit.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
ef78df8d3b0cf540e5f08c8c2f6caa338b64a6c7)
Kenneth Graunke [Sat, 30 Apr 2016 04:12:15 +0000 (21:12 -0700)]
i965: Copy propagate before doing variable index lowering.
The scalar backend currently doesn't support variable indexing on
temporary arrays, but it does support it on uniform arrays, and
some stages support it for input arrays. Make sure these are
propagated through before exploding indirects into piles of
if-ladders unnecessarily.
On Broadwell, no instruction count change in shader-db.
total cycles in shared programs:
80675652 ->
80674928 (-0.00%)
cycles in affected programs: 649972 -> 649248 (-0.11%)
helped: 386
HURT: 165
This will help avoid code quality regressions in a future commit.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
f7741c521119ce147215d94a4c238e84fc8b1130)
Kenneth Graunke [Wed, 22 Jun 2016 00:42:59 +0000 (17:42 -0700)]
glsl: Propagate invariant/precise after lowering const arrays.
The new uniform may need precise as well.
Fixes copy propagation of constant array uniforms in Tomb Raider shaders.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
586f4a42e78f171c28c3ae37adb8671e09bd74b4)
Kenneth Graunke [Mon, 20 Jun 2016 18:20:51 +0000 (11:20 -0700)]
glsl: Split arrays even in the presence of whole-array copies.
Previously, we failed to split constant arrays. Code such as
int[2] numbers = int[](1, 2);
would generates a whole-array assignment:
(assign () (var_ref numbers)
(constant (array int 4) (constant int 1) (constant int 2)))
opt_array_splitting generally tried to visit ir_dereference_array nodes,
and avoid recursing into the inner ir_dereference_variable. So if it
ever saw a ir_dereference_variable, it assumed this was a whole-array
read and bailed. However, in the above case, there's no array deref,
and we can totally handle it - we just have to "unroll" the assignment,
creating assignments for each element.
This was mitigated by the fact that we constant propagate whole arrays,
so a dereference of a single component would usually get the desired
single value anyway. However, I plan to stop doing that shortly;
early experiments with disabling constant propagation of arrays
revealed this shortcoming.
This patch causes some arrays in Gl32GSCloth's geometry shaders to be
split, which allows other optimizations to eliminate unused GS inputs.
The VS then doesn't have to write them, which eliminates the entire VS
(5 -> 2 instructions). It still renders correctly.
No other change in shader-db.
v2: Drop !AOA check and improve a comment (feedback from Tim Arceri).
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
c264fdbc073a0dfc393f53a8be880f535fd4b988)
Kenneth Graunke [Mon, 20 Jun 2016 23:48:02 +0000 (16:48 -0700)]
glsl: Make constant propagation's folder not propagate into an LHS.
opt_constant_propagation.cpp contains constant folding code which can
actually do constant propagation in some cases. It was happily
propagating constants into the left-hand-side of assignments.
For example,
(assign () (var_ref temp) (constant ...))
would brilliantly be turned into:
(assign () (constant ...) (constant ....))
This is a bigger hammer than necessary - it prevents propagation
into the left-hand-side altogether. We could certainly do better
someday. Notably, the constant propagation pass itself already
takes this approach - it's just the constant propagation pass's
built-in constant folding code (which actually propagates, too)
that was broken.
No change in shader-db, but prevents regressions after future commits.
It seems plausible that this could be hit today, but I haven't seen it
happen.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
(cherry picked from commit
acf544404472488eec85fff249cbface7fa477b1)
Ardinartsev Nikita [Thu, 23 Jun 2016 01:28:11 +0000 (18:28 -0700)]
i965: Avoid division by zero.
Fixes regression introduced by
af5ca43f2676bff7499f93277f908b681cb821d0
Cc: "12.0 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
(cherry picked from commit
01c89ccc5d1529aa1efbae80c8ef641a59abbd93)
Tim Rowley [Fri, 17 Jun 2016 02:09:35 +0000 (21:09 -0500)]
swr: push/pop DEBUG macro around llvm includes
llvm redefines DEBUG; adding push/pop prevents a undefined reference
to debug_refcnt_state in llvm-3.7+.
v2: add undef DEBUG
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
(cherry picked from commit
9ca741c64524a57f972ce050919a0e2dec3e64f3)
Jose Fonseca [Thu, 23 Jun 2016 10:18:21 +0000 (11:18 +0100)]
include: Require MSVC 2013 Update 4.
Earlier MSVC 2013 releases have troubles compiling some of our C99 code,
so make sure we have Update 4 to avoid confusion.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit
805dbdf06d98e6dcfe0b24e38cc13c88eb5f36be)
Jason Ekstrand [Thu, 16 Jun 2016 22:26:54 +0000 (15:26 -0700)]
anv: Use different BOs for different scratch sizes and stages
This solves a race condition where we can end up having different stages
stomp on each other because they're all trying to scratch in the same BO
but they have different views of its layout.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
c2f2c8e407207c31c29aab5570d23cd6e98d287a)
Jason Ekstrand [Thu, 16 Jun 2016 21:58:25 +0000 (14:58 -0700)]
genxml: Make ScratchSpaceBasePointer an address instead of an offset
While we're here, we also fixup MEDIA_VFE_STATE and rename the field in
3DSTATE_VS on gen6-7.5 to be consistent with the others.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
45c0f60999587ed29a7a9b81f09950dd8f58fb49)
Jason Ekstrand [Thu, 16 Jun 2016 21:43:41 +0000 (14:43 -0700)]
anv: Add an allocator for scratch buffers
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
966bed17c1a04854b4a422d90de81744556204b6)
Jason Ekstrand [Tue, 7 Jun 2016 18:37:46 +0000 (11:37 -0700)]
genxml: Put append counter fields before MCS in RENDER_SURFACE_STATE on gen7
The pack header generation scripts can't handle the case where you have
two addresses in the same dword; they just take whatever is the last one.
This meant that the MCS address wasn't properly getting handled. Since we
don't care about append counters, we can just re-arrange the XML for now.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
89ded099f840275d278c408e132ad5db39fdf5af)
Jason Ekstrand [Thu, 9 Jun 2016 20:56:16 +0000 (13:56 -0700)]
anv,isl: Lower storage image formats in anv
ISL was being a bit too clever for its own good and lowering the format for
us. This is all well and good *if* we always want to lower it. However,
the GL driver selectively lowers the format depending on whether the
surface is write-only or not.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
d82322eb188f258a7dca9ea2b59cc0332dbc4d61)
Jason Ekstrand [Fri, 10 Jun 2016 17:45:43 +0000 (10:45 -0700)]
isl/state: Allow for full 31-bit buffer texture sizes
Ivy Bridge and above can handle up to 2^31 elements for RAW buffer
surfaces.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
97f12773b89a409d1368ce6b3b5badb9e75bbf53)
Jason Ekstrand [Sat, 11 Jun 2016 01:28:49 +0000 (18:28 -0700)]
isl/state: Don't use designated initializers for buffer surface state
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
bb64e666ba91ce9b1a7405a1c14d41d294062b9a)
Jason Ekstrand [Fri, 10 Jun 2016 01:48:07 +0000 (18:48 -0700)]
isl/state: Add assertions for buffer surface restrictions
Acked-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
4061fde66e9feefa051a02fe258d69fe817e6a8c)
Jason Ekstrand [Thu, 9 Jun 2016 22:08:13 +0000 (15:08 -0700)]
isl/state: Don't set SurfacePitch for gen9 1-D textures
This field is ignored by the hardware in this case and, on very large 1-D
textures, it can end up being larger than the maximum allowed value.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
ce24097abe1427463ac300a686e4c36ea07464fc)
Jason Ekstrand [Tue, 7 Jun 2016 21:33:40 +0000 (14:33 -0700)]
isl/state: Use TILEWALK_XMAJOR for linear surfaces on gen7
This matches better what happens on gen8 where the "Tiled Surface" and
"Tile Walke" bits are combined into a single two-bit value. This is also
more consistent with what the GL driver does.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
f47e23a8b6abd3bbc1d2d60c023c5a7ffaf70d72)
Jason Ekstrand [Tue, 7 Jun 2016 01:22:21 +0000 (18:22 -0700)]
isl/state: Emit no-op mip tail setup on SKL
This hasn't ever been a problem in the past but it is recommended by the
hardware docs.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
96706bad5ff37e56ee48f9bbb143d39a6e113a62)
Jason Ekstrand [Tue, 7 Jun 2016 01:21:17 +0000 (18:21 -0700)]
isl/state: Only set cube face enables if usage includes CUBE_BIT
It seems safe to set it all the time, but this reduces the diff between
the way i965 does it and what ISL does.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
14d7c16e50f88720fa27722522d4ff89972a4f9d)
Jason Ekstrand [Sun, 5 Jun 2016 04:22:21 +0000 (21:22 -0700)]
isl/state: Use the layout for computing qpitch rather than dimensions
For depth/stencil 1-D textures on SKL, we want them layed out in the old
format that has been used since gen4. In order for the surface state
fill-out code to handle, this it needs to distinguish based on layout
rather than just dimensionality.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
5d24e9cfa126971518be662e57021322ebf67a9a)
Jason Ekstrand [Tue, 7 Jun 2016 15:05:45 +0000 (08:05 -0700)]
isl/state: Set the IntegerSurfaceFormat bit on Haswell
This fixes 688 Vulkan CTS tests on Haswell.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
6a43204afa40359f73684d3ccc7db8c4dad6288b)
Jason Ekstrand [Tue, 7 Jun 2016 21:40:47 +0000 (14:40 -0700)]
isl/format: Mark R9G9B9E5 as containing 9-bit unsigned float channels
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
324103da75abab5003b63ec996a2e8eb8de67049)
Jason Ekstrand [Fri, 17 Jun 2016 23:40:24 +0000 (16:40 -0700)]
isl/state: Don't set RenderTargetViewExtent for texture surfaces
The docs specify that this only matters for render targets and surfaces
used with typed dataport messages. On some platforms (gen4-6) the Depth
field has more bits than RenderTargetViewExtent so we can have textures
with more levels than we can render to.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
215282c9f41432a245e79cdf5f8328c6785e924a)
Jason Ekstrand [Tue, 7 Jun 2016 22:30:00 +0000 (15:30 -0700)]
isl/state: Set SurfaceArray based on the surface dimension
According to the PRM, you can't set SurfaceArray for 3D or buffer textures.
There doesn't seem to be a good reason not to set it when we can. On the
other hand, if we don't set it we can end up getting strange results for
1-layer array textures such as textureSize() returning the wrong results.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
bb326f7b01daeb97e544873f20a23614ed54c548)
Jason Ekstrand [Sun, 5 Jun 2016 03:48:55 +0000 (20:48 -0700)]
isl/state: Don't force-disable L2 bypass for everything
We already set the bit in the few cases where it's required by the docs so
there's no need to set it all the time. This has no noticable perf impact
for Dota 2 on Vulkan with the time demo I have.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
d050ffbce950f8ececd12200145eb209819a421e)
Jason Ekstrand [Fri, 3 Jun 2016 02:02:23 +0000 (19:02 -0700)]
isl/state: Refactor the setup of clear colors
This commit switches clear colors to use #if's instead of a C if. This
lets us properly handle SNB where the clear color field doesn't exist.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
87f0ffa646e97def0f81ba2ad12eab2702dfd7b1)
Jason Ekstrand [Fri, 3 Jun 2016 02:00:10 +0000 (19:00 -0700)]
isl/state: Refactor the per-gen isl_to_gen_h/valign tables
This moves the #if's around so that halign and valign have different sets
of #if conditions. This also prepares us for SNB because isl_to_gen_halign
is not defined at all on gen6.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
62a5e6e03117e5eb3f777633409cb8036be6877d)
Jason Ekstrand [Fri, 3 Jun 2016 01:40:07 +0000 (18:40 -0700)]
isl/state: Return an extent3d from the halign/valign helper
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
b1b0d6fb5415c874cbbd1346e50d04e33b0e9c21)
Jason Ekstrand [Wed, 8 Jun 2016 00:01:56 +0000 (17:01 -0700)]
isl/state: Put pitch calculations together
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
a60ae9e10ab8cd22f80dc91ba29e27db17ab3372)
Jason Ekstrand [Tue, 7 Jun 2016 23:58:54 +0000 (16:58 -0700)]
isl/state: Put all dimension setup together and towards the top
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
70c8afc0c892c2a3819ea01cf5b9467d80b4d7b5)
Jason Ekstrand [Wed, 8 Jun 2016 00:14:39 +0000 (17:14 -0700)]
isl/state: Put surface format setup at the top
This is purely cosmetic, but it makes things look a bit more readable.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
e66e70ef47907264757751206878b703bd95390b)
Jason Ekstrand [Tue, 7 Jun 2016 23:55:21 +0000 (16:55 -0700)]
isl/state: Remove some unused fields
They're already zero-initialized and we have no plans of doing anything
more interesting with them.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
39baea551fe228cfc4647d6a56e80639b7129b6a)
Jason Ekstrand [Tue, 7 Jun 2016 23:53:19 +0000 (16:53 -0700)]
isl/state: Don't use designated initializers for the surface state
While designated initializers are nice, they also force us to put some
things in the initializer and some things later. Surface state setup is
complicated enough that this really hurts readability in the long run.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
caf2af4181c66df8af31662de22120dcf1d16c7c)
Jason Ekstrand [Fri, 3 Jun 2016 01:43:59 +0000 (18:43 -0700)]
genxml/gen8,9: Prefix the multisample format enum with MSFMT
This is what gen7 does and it's nice to have a prefix
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
de1d194856ddcfc946df2df0f076cb42ff1c165d)
Jason Ekstrand [Sat, 11 Jun 2016 04:11:02 +0000 (21:11 -0700)]
i965/gen4: Subtract 1 from buffer sizes
The PRM states that the values put in Width, Height, and Depth should be
various bits from the value size - 1. We seem to have done this wrong
more-or-less from the start.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
2a1cc94d27c80929d91e38b4843333a5408d563e)
Jason Ekstrand [Tue, 7 Jun 2016 02:15:39 +0000 (19:15 -0700)]
i965/fs: Use a default Y coordinate of 0 for TXF on gen9+
Previously, we were incrementing length but not actually putting anything
in the Y coordinate. This meant that 1-D TXF operations had a garbage
array index. If the surface is emitted as 1-D non-array, the coordinate
gets discarded and it works fine. If it happens to be bound as an array
surface, it may count as an out-of-bounds array access and you get zero.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
0195299c868ec99bc6c595c641da81bb2632252e)
Jason Ekstrand [Sat, 4 Jun 2016 21:32:37 +0000 (14:32 -0700)]
i965/gen8: Use the qpitch from the aux_mt for AUX_QPITCH
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
1436238b75e0352439306f120ac1ca03c9fc7df3)
Jason Ekstrand [Sat, 4 Jun 2016 06:25:19 +0000 (23:25 -0700)]
i965/blorp/gen8: Use the correct max level and layer in emit_surface_states
We were adding in the base which is wrong because the values given in the
miptree are relative to zero and not the base layer/level.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
620f81d2edb20ffd9803ee318f60845441459fac)
Jason Ekstrand [Thu, 9 Jun 2016 21:57:33 +0000 (14:57 -0700)]
i965: Drop the maximum 3D texture size to 512 on Sandy Bridge
The RenderTargetViewExtent field of RENDER_SURFACE_STATE is supposed to be
set to the depth of a 3-D texture when rendering. Unfortunatley, that
field is only 9 bits on Sandy Bridge and prior so we can't actually bind
a 3-D texturing for rendering if it has depth > 512. On Ivy Bridge, this
field was bumpped to 11 bits so we can go all the way up to 2048. On Iron
Lake and prior, we don't support layered rendering and we use OffsetX/Y
hacks to render to particular layers so 2048 is ok there too.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "11.1 11.2 12.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
6ba88bce64b343761aabe3a6c7ee285c6020a959)