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2 years agoMerge remote-tracking branch 'remotes/philmd/tags/pmbus-20220308' into staging
Peter Maydell [Wed, 9 Mar 2022 21:16:27 +0000 (21:16 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/pmbus-20220308' into staging

I²C / SMBus / PMBus patches

- Add some Renesas models
- Add Titus Rwantare to MAINTAINERS

# gpg: Signature made Tue 08 Mar 2022 18:11:46 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/pmbus-20220308:
  hw/sensor: add Renesas raa228000 device
  hw/sensor: add Renesas raa229004 PMBus device
  hw/sensor: add Intersil ISL69260 device model
  hw/i2c: Added linear mode translation for pmbus devices
  hw/i2c: pmbus: update MAINTAINERS
  hw/i2c: pmbus: refactor uint handling
  hw/i2c: pmbus: add PEC unsupported warning
  hw/i2c: pmbus: fix error returns and guard against out of range accesses
  hw/i2c: pmbus: add registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull...
Peter Maydell [Wed, 9 Mar 2022 20:01:17 +0000 (20:01 +0000)]
Merge remote-tracking branch 'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging

linux-user pull request 20220308

deliver SIGTRAP on POWERPC_EXCP_TRAP
remove stale "not threadsafe" comments

# gpg: Signature made Tue 08 Mar 2022 15:02:14 GMT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request:
  tests/tcg/ppc64le: change signal_save_restore_xer to use SIGTRAP
  linux-user/ppc: deliver SIGTRAP on POWERPC_EXCP_TRAP
  linux-user: Remove stale "not threadsafe" comments

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220308' into staging
Peter Maydell [Wed, 9 Mar 2022 18:06:40 +0000 (18:06 +0000)]
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220308' into staging

aspeed queue:

* Fix for a potential memory leak
* Aspeed SMC cleanups on the definition of the number of flash devices
* New bletchley-bmc machine, AST2600 based

# gpg: Signature made Tue 08 Mar 2022 08:19:25 GMT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-aspeed-20220308:
  hw: aspeed_gpio: Cleanup stray semicolon after switch
  hw/arm/aspeed: add Bletchley machine type
  hw/arm/aspeed: allow missing spi_model
  hw/block: m25p80: Add support for w25q01jvq
  aspeed/smc: Fix error log
  aspeed/smc: Let the SSI core layer define the bus name
  aspeed/smc: Rename 'max_peripherals' to 'cs_num_max'
  aspeed/smc: Remove 'num_cs' field
  aspeed: Rework aspeed_board_init_flashes() interface
  aspeed/smc: Use max number of CE instead of 'num_cs'
  aspeed: Fix a potential memory leak bug in write_boot_rom()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-20220308' into...
Peter Maydell [Wed, 9 Mar 2022 15:50:39 +0000 (15:50 +0000)]
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-20220308' into staging

qemu-openbios queue

# gpg: Signature made Tue 08 Mar 2022 08:05:09 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-openbios-20220308:
  roms/openbios: update OpenBIOS images to 0e0afae6 built from submodule

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2022-03-07' into staging
Peter Maydell [Wed, 9 Mar 2022 11:38:29 +0000 (11:38 +0000)]
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2022-03-07' into staging

nbd patches for 2022-03-07

- Dan Berrange: Allow qemu-nbd to support TLS over Unix sockets
- Eric Blake: Minor cleanups related to 64-bit block operations

# gpg: Signature made Tue 08 Mar 2022 01:41:35 GMT
# gpg:                using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full]
# gpg:                 aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full]
# gpg:                 aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2  F3AA A7A1 6B4A 2527 436A

* remotes/ericb/tags/pull-nbd-2022-03-07:
  qemu-io: Allow larger write zeroes under no fallback
  qemu-io: Utilize 64-bit status during map
  nbd/server: Minor cleanups
  tests/qemu-iotests: validate NBD TLS with UNIX sockets and PSK
  tests/qemu-iotests: validate NBD TLS with UNIX sockets
  tests/qemu-iotests: validate NBD TLS with hostname mismatch
  tests/qemu-iotests: convert NBD TLS test to use standard filters
  tests/qemu-iotests: introduce filter for qemu-nbd export list
  tests/qemu-iotests: expand _filter_nbd rules
  tests/qemu-iotests: add QEMU_IOTESTS_REGEN=1 to update reference file
  block/nbd: don't restrict TLS usage to IP sockets
  qemu-nbd: add --tls-hostname option for TLS certificate validation
  block/nbd: support override of hostname for TLS certificate validation
  block: pass desired TLS hostname through from block driver client
  crypto: mandate a hostname when checking x509 creds on a client

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into staging
Peter Maydell [Wed, 9 Mar 2022 09:13:39 +0000 (09:13 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into staging

MIPS patches queue

- Fix CP0 cycle counter timing
- Fix VMState of gt64120 IRQs
- Long due PIIX4 QOM cleanups
- ISA IRQ QOM'ification / cleanups

# gpg: Signature made Tue 08 Mar 2022 18:39:42 GMT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20220308:
  tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag
  hw/isa: Inline and remove one-line isa_init_irq()
  hw/isa: Drop unused attributes from ISADevice
  hw/isa/isa-bus: Remove isabus_dev_print()
  hw/input/pckbd: QOM'ify IRQ numbers
  hw/rtc/m48t59-isa: QOM'ify IRQ number
  hw/rtc/mc146818rtc: QOM'ify IRQ number
  hw/mips/gt64xxx_pci: Resolve gt64120_register()
  hw/isa/piix4: Replace some magic IRQ constants
  hw/isa/piix4: Resolve global instance variable
  hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()
  hw/isa/piix4: Resolve redundant i8259[] attribute
  malta: Move PCI interrupt handling from gt64xxx_pci to piix4
  hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration
  target/mips: Remove duplicated MIPSCPU::cp0_count_rate
  target/mips: Fix cycle counter timing calculations

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
Peter Maydell [Tue, 8 Mar 2022 22:27:34 +0000 (22:27 +0000)]
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

virtio,pc,pci: features, cleanups, fixes

vhost-user enabled on non-linux systems
beginning of nvme sriov support
bigger tx queue for vdpa
virtio iommu bypass
FADT flag to detect legacy keyboards

Fixes, cleanups all over the place

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Mon 07 Mar 2022 22:43:31 GMT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream: (47 commits)
  hw/acpi/microvm: turn on 8042 bit in FADT boot architecture flags if present
  tests/acpi: i386: update FACP table differences
  hw/acpi: add indication for i8042 in IA-PC boot flags of the FADT table
  tests/acpi: i386: allow FACP acpi table changes
  docs: vhost-user: add subsection for non-Linux platforms
  configure, meson: allow enabling vhost-user on all POSIX systems
  vhost: use wfd on functions setting vring call fd
  event_notifier: add event_notifier_get_wfd()
  pci: drop COMPAT_PROP_PCP for 2.0 machine types
  hw/smbios: Add table 4 parameter, "processor-id"
  x86: cleanup unused compat_apic_id_mode
  vhost-vsock: detach the virqueue element in case of error
  pc: add option to disable PS/2 mouse/keyboard
  acpi: pcihp: pcie: set power on cap on parent slot
  pci: expose TYPE_XIO3130_DOWNSTREAM name
  pci: show id info when pci BDF conflict
  hw/misc/pvpanic: Use standard headers instead
  headers: Add pvpanic.h
  pci-bridge/xio3130_downstream: Fix error handling
  pci-bridge/xio3130_upstream: Fix error handling
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# docs/specs/index.rst

2 years agoMerge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' into...
Peter Maydell [Tue, 8 Mar 2022 19:31:05 +0000 (19:31 +0000)]
Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' into staging

Python patches

Hopefully, fixes the race conditions witnessed through the NetBSD vm tests.

# gpg: Signature made Mon 07 Mar 2022 22:14:42 GMT
# gpg:                using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full]
# Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
#      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E

* remotes/jsnow-gitlab/tags/python-pull-request:
  scripts/qmp-shell-wrap: Fix import path
  python/aqmp: drop _bind_hack()
  python/aqmp: fix race condition in legacy.py
  python/aqmp: add start_server() and accept() methods
  python/aqmp: stop the server during disconnect()
  python/aqmp: refactor _do_accept() into two distinct steps
  python/aqmp: squelch pylint warning for too many lines
  python/aqmp: split _client_connected_cb() out as _incoming()
  python/aqmp: remove _new_session and _establish_connection
  python/aqmp: rename 'accept()' to 'start_server_and_accept()'
  python/aqmp: add _session_guard()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag
Cleber Rosa [Fri, 25 Feb 2022 21:01:52 +0000 (16:01 -0500)]
tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag

Being explicit about the accelerator used on these tests is a good
thing in itself, but it will also be used in the filtering rules
applied on "make check-avocado".

Signed-off-by: Cleber Rosa <crosa@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220225210156.2032055-6-crosa@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/isa: Inline and remove one-line isa_init_irq()
Bernhard Beschow [Tue, 1 Mar 2022 22:00:37 +0000 (23:00 +0100)]
hw/isa: Inline and remove one-line isa_init_irq()

isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
It can therefore be removed.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> (tpm_tis_isa)
Acked-by: Corey Minyard <cminyard@mvista.com> (isa_ipmi_bt, isa_ipmi_kcs)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20220301220037.76555-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307134353.1950-14-philippe.mathieu.daude@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2 years agohw/isa: Drop unused attributes from ISADevice
Bernhard Beschow [Tue, 1 Mar 2022 22:00:36 +0000 (23:00 +0100)]
hw/isa: Drop unused attributes from ISADevice

Now that the last users of ISADevice::isairq[] have been resolved during the
previous commits, it can be removed for good.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307134353.1950-13-philippe.mathieu.daude@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2 years agohw/isa/isa-bus: Remove isabus_dev_print()
Bernhard Beschow [Tue, 1 Mar 2022 22:00:34 +0000 (23:00 +0100)]
hw/isa/isa-bus: Remove isabus_dev_print()

All isabus_dev_print() did was to print up to two IRQ numbers per
device. This is redundant if the IRQ numbers are present as QOM
properties (see e.g. the modified tests/qemu-iotests/172.out).

Now that the last devices relying on isabus_dev_print() had their IRQ
numbers QOM'ified, the contribution of this function ultimately became
redundant. Remove it.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307134353.1950-12-philippe.mathieu.daude@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2 years agohw/input/pckbd: QOM'ify IRQ numbers
Bernhard Beschow [Tue, 1 Mar 2022 22:00:33 +0000 (23:00 +0100)]
hw/input/pckbd: QOM'ify IRQ numbers

Exposing the IRQ numbers as QOM properties not only allows them to be
configurable but also to be printed by standard QOM mechanisms. This
allows isabus_dev_print() to be retired eventually.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307134353.1950-11-philippe.mathieu.daude@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2 years agohw/rtc/m48t59-isa: QOM'ify IRQ number
Bernhard Beschow [Tue, 1 Mar 2022 22:00:32 +0000 (23:00 +0100)]
hw/rtc/m48t59-isa: QOM'ify IRQ number

Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307134353.1950-10-philippe.mathieu.daude@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2 years agohw/rtc/mc146818rtc: QOM'ify IRQ number
Bernhard Beschow [Tue, 1 Mar 2022 22:00:31 +0000 (23:00 +0100)]
hw/rtc/mc146818rtc: QOM'ify IRQ number

Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be displayed in HMP:

Before:

(qemu) info qtree
       ...
          dev: mc146818rtc, id ""
            gpio-out "" 1
            base_year = 0 (0x0)
            lost_tick_policy = "discard"

After:

          dev: mc146818rtc, id ""
            gpio-out "" 1
            base_year = 0 (0x0)
            irq = 8 (0x8)
            lost_tick_policy = "discard"

The reason the IRQ number didn's show up before is that this device does not
call isa_init_irq().

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307134353.1950-9-philippe.mathieu.daude@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
2 years agohw/mips/gt64xxx_pci: Resolve gt64120_register()
Bernhard Beschow [Thu, 17 Feb 2022 10:19:24 +0000 (11:19 +0100)]
hw/mips/gt64xxx_pci: Resolve gt64120_register()

Now that gt64120_register() lost its pic parameter, there is an
opportunity to remove it. gt64120_register() is old style by wrapping
qdev API, and the new style is to use qdev directly. So take the
opportunity and modernize the code.

Suggested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220217101924.15347-8-shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/isa/piix4: Replace some magic IRQ constants
Bernhard Beschow [Thu, 17 Feb 2022 10:19:23 +0000 (11:19 +0100)]
hw/isa/piix4: Replace some magic IRQ constants

This is a follow-up on patch "malta: Move PCI interrupt handling from
gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably
didn't want to use piix4-specific constants. Now that the interrupt
handing resides in piix4, its constants can be used.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-7-shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/isa/piix4: Resolve global instance variable
Bernhard Beschow [Thu, 17 Feb 2022 10:19:22 +0000 (11:19 +0100)]
hw/isa/piix4: Resolve global instance variable

Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-6-shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()
Bernhard Beschow [Thu, 17 Feb 2022 10:19:21 +0000 (11:19 +0100)]
hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()

Passing PIIX4State rather than just the qemu_irq allows for resolving
the global piix4_dev variable.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-5-shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/isa/piix4: Resolve redundant i8259[] attribute
Bernhard Beschow [Thu, 17 Feb 2022 10:19:20 +0000 (11:19 +0100)]
hw/isa/piix4: Resolve redundant i8259[] attribute

This is a follow-up on patch "malta: Move PCI interrupt handling from
gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to
PIIX4State to make the code movement more obvious. However, i8259[]
seems redundant to *isa, so remove it.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-4-shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agomalta: Move PCI interrupt handling from gt64xxx_pci to piix4
Bernhard Beschow [Thu, 17 Feb 2022 10:19:19 +0000 (11:19 +0100)]
malta: Move PCI interrupt handling from gt64xxx_pci to piix4

Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220217101924.15347-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration
Bernhard Beschow [Thu, 17 Feb 2022 10:19:18 +0000 (11:19 +0100)]
hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration

Based on commit e735b55a8c11dd455e31ccd4420e6c9485191d0c:

  piix_pci: eliminate PIIX3State::pci_irq_levels

  PIIX3State::pci_irq_levels are redundant which is already tracked by
  PCIBus layer. So eliminate them.

The IRQ levels in the PCIBus layer are already preserved during
migration. By reusing them and rather than having a redundant implementation
the bug is avoided in the first place.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220217101924.15347-2-shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/sensor: add Renesas raa228000 device
Titus Rwantare [Mon, 7 Mar 2022 20:06:05 +0000 (12:06 -0800)]
hw/sensor: add Renesas raa228000 device

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-10-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/sensor: add Renesas raa229004 PMBus device
Titus Rwantare [Mon, 7 Mar 2022 20:06:04 +0000 (12:06 -0800)]
hw/sensor: add Renesas raa229004 PMBus device

The Renesas RAA229004 is a PMBus Multiphase Voltage Regulator

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-9-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/sensor: add Intersil ISL69260 device model
Titus Rwantare [Mon, 7 Mar 2022 20:06:03 +0000 (12:06 -0800)]
hw/sensor: add Intersil ISL69260 device model

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-8-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/i2c: Added linear mode translation for pmbus devices
Shengtan Mao [Mon, 7 Mar 2022 20:06:02 +0000 (12:06 -0800)]
hw/i2c: Added linear mode translation for pmbus devices

Signed-off-by: Shengtan Mao <stmao@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-7-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/i2c: pmbus: update MAINTAINERS
Titus Rwantare [Mon, 7 Mar 2022 20:06:01 +0000 (12:06 -0800)]
hw/i2c: pmbus: update MAINTAINERS

add self to MAINTAINERS for the PMBus subsystem and related sensors,
and set PMBus as maintained.

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-6-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/i2c: pmbus: refactor uint handling
Titus Rwantare [Mon, 7 Mar 2022 20:06:00 +0000 (12:06 -0800)]
hw/i2c: pmbus: refactor uint handling

This change cleans up the inputs to pmbus_receive uint, the length of
received data is contained in PMBusDevice state and doesn't need to be
passed around.

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-5-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/i2c: pmbus: add PEC unsupported warning
Titus Rwantare [Mon, 7 Mar 2022 20:05:59 +0000 (12:05 -0800)]
hw/i2c: pmbus: add PEC unsupported warning

Signed-off-by: Titus Rwantare <titusr@google.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220307200605.4001451-4-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/i2c: pmbus: fix error returns and guard against out of range accesses
Titus Rwantare [Mon, 7 Mar 2022 20:05:58 +0000 (12:05 -0800)]
hw/i2c: pmbus: fix error returns and guard against out of range accesses

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-3-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agohw/i2c: pmbus: add registers
Titus Rwantare [Mon, 7 Mar 2022 20:05:57 +0000 (12:05 -0800)]
hw/i2c: pmbus: add registers

   - add the VOUT_MIN and STATUS_MFR registers

Signed-off-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20220307200605.4001451-2-titusr@google.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agoMerge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2022-03-07'...
Peter Maydell [Tue, 8 Mar 2022 17:09:18 +0000 (17:09 +0000)]
Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2022-03-07' into staging

* Fixes for s390x TCG tests
* Update Haiku VM to a usable level
* Some other miscellaneous small fixes

# gpg: Signature made Mon 07 Mar 2022 18:07:00 GMT
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* remotes/thuth-gitlab/tags/pull-request-2022-03-07:
  Check and report for incomplete 'global' option format
  tests/vm: Update haiku test vm to R1/Beta3
  tests/avocado: Cancel BootLinux tests in case there is no free port
  MAINTAINERS: Update the files in the FreeBSD section
  tests/tcg/s390x: Cleanup of mie3 tests.
  tests/tcg/s390x: Fix the exrl-trt* tests with Clang
  tests/tcg/s390x: Fix mvc, mvo and pack tests with Clang

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220307' into...
Peter Maydell [Tue, 8 Mar 2022 15:26:10 +0000 (15:26 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220307' into staging

target-arm queue:
 * cleanups of qemu_oom_check() and qemu_memalign()
 * target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
 * target/arm/translate-neon: Simplify align field check for VLD3
 * GICv3 ITS: add more trace events
 * GICv3 ITS: implement 8-byte accesses properly
 * GICv3: fix minor issues with some trace/log messages
 * ui/cocoa: Use the standard about panel
 * target/arm: Provide cpu property for controling FEAT_LPA2
 * hw/arm/virt: Disable LPA2 for -machine virt-6.2

# gpg: Signature made Mon 07 Mar 2022 16:46:06 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20220307:
  hw/arm/virt: Disable LPA2 for -machine virt-6.2
  target/arm: Provide cpu property for controling FEAT_LPA2
  ui/cocoa: Use the standard about panel
  hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event
  hw/intc/arm_gicv3: Fix missing spaces in error log messages
  hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps
  hw/intc/arm_gicv3_its: Add trace events for table reads and writes
  hw/intc/arm_gicv3_its: Add trace events for commands
  target/arm/translate-neon: Simplify align field check for VLD3
  target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
  osdep: Move memalign-related functions to their own header
  util: Put qemu_vfree() in memalign.c
  util: Use meson checks for valloc() and memalign() presence
  util: Share qemu_try_memalign() implementation between POSIX and Windows
  meson.build: Don't misdetect posix_memalign() on Windows
  util: Return valid allocation for qemu_try_memalign() with zero size
  util: Unify implementations of qemu_memalign()
  util: Make qemu_oom_check() a static function

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotests/tcg/ppc64le: change signal_save_restore_xer to use SIGTRAP
Matheus Ferst [Thu, 13 Jan 2022 17:04:55 +0000 (14:04 -0300)]
tests/tcg/ppc64le: change signal_save_restore_xer to use SIGTRAP

Now that linux-user delivers the signal on tw, we can change
signal_save_restore_xer to use SIGTRAP instead of SIGILL.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220113170456.1796911-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2 years agolinux-user/ppc: deliver SIGTRAP on POWERPC_EXCP_TRAP
Matheus Ferst [Thu, 13 Jan 2022 17:04:54 +0000 (14:04 -0300)]
linux-user/ppc: deliver SIGTRAP on POWERPC_EXCP_TRAP

Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220113170456.1796911-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2 years agolinux-user: Remove stale "not threadsafe" comments
Peter Maydell [Fri, 14 Jan 2022 15:50:32 +0000 (15:50 +0000)]
linux-user: Remove stale "not threadsafe" comments

In linux-user/signal.c we have two FIXME comments claiming that
parts of the signal-handling code are not threadsafe. These are
very old, as they were first introduced in commit 624f7979058
in 2008. Since then we've radically overhauled the signal-handling
logic, while carefully preserving these FIXME comments.

It's unclear exactly what thread-safety issue the original
author was trying to point out -- the relevant data structures
are in the TaskStruct, which makes them per-thread and only
operated on by that thread. The old code at the time of that
commit did have various races involving signal handlers being
invoked at awkward times; possibly this was what was meant.

Delete these FIXME comments:
 * they were written at a time when the way we handled
   signals was completely different
 * the code today appears to us to not have thread-safety issues
 * nobody knows what the problem the comments were trying to
   point out was
so they are serving no useful purpose for us today.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Message-Id: <20220114155032.3767771-1-peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2 years agoMerge remote-tracking branch 'remotes/kraxel/tags/seabios-20220307-pull-request'...
Peter Maydell [Tue, 8 Mar 2022 12:40:58 +0000 (12:40 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20220307-pull-request' into staging

update seabios to 1.16.0

# gpg: Signature made Mon 07 Mar 2022 11:02:40 GMT
# gpg:                using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/seabios-20220307-pull-request:
  update seabios binaries to 1.16.0
  update seabios submodule to 1.16.0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20220307' into staging
Peter Maydell [Tue, 8 Mar 2022 09:06:57 +0000 (09:06 +0000)]
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20220307' into staging

9pfs: introduce macOS host support and cleanup

* Add support for Darwin (a.k.a. macOS) hosts.

* Code cleanup (move qemu_dirent_dup() from osdep -> 9p-util).

* API doc cleanup (convert Doxygen -> kerneldoc format).

# gpg: Signature made Mon 07 Mar 2022 11:14:45 GMT
# gpg:                using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395
# gpg:                issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38  4926 30DB 47C3 A012 D5F4
#      Subkey fingerprint: 96D8 D110 CF7A F808 4F88  5901 34C2 B587 65A4 7395

* remotes/cschoenebeck/tags/pull-9p-20220307:
  fsdev/p9array.h: convert Doxygen -> kerneldoc format
  9pfs/coth.h: drop Doxygen format on v9fs_co_run_in_worker()
  9pfs/9p-util.h: convert Doxygen -> kerneldoc format
  9pfs/9p.c: convert Doxygen -> kerneldoc format
  9pfs/codir.c: convert Doxygen -> kerneldoc format
  9pfs/9p.h: convert Doxygen -> kerneldoc format
  9pfs: drop Doxygen format from qemu_dirent_dup() API comment
  9pfs: move qemu_dirent_dup() from osdep -> 9p-util
  9p: darwin: meson: Allow VirtFS on Darwin
  9p: darwin: Adjust assumption on virtio-9p-test
  9p: darwin: Implement compatibility for mknodat
  9p: darwin: Compatibility for f/l*xattr
  9p: darwin: *xattr_nofollow implementations
  9p: darwin: Move XATTR_SIZE_MAX->P9_XATTR_SIZE_MAX
  9p: darwin: Ignore O_{NOATIME, DIRECT}
  9p: darwin: Handle struct dirent differences
  9p: darwin: Handle struct stat(fs) differences
  9p: Rename 9p-util -> 9p-util-linux
  9p: linux: Fix a couple Linux assumptions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw: aspeed_gpio: Cleanup stray semicolon after switch
Andrew Jeffery [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
hw: aspeed_gpio: Cleanup stray semicolon after switch

Not sure how that got there.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20220207150409.358888-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agohw/arm/aspeed: add Bletchley machine type
Patrick Williams [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
hw/arm/aspeed: add Bletchley machine type

Add the 'bletchley-bmc' machine type based on the kernel DTS[1] and
hardware schematics available to me.  The i2c model is as complete as
the current QEMU models support, but in some cases I substituted devices
that are close enough for present functionality.  Strap registers are
kept the same as the AST2600-EVB until I'm able to confirm correct
values with physical hardware.

This has been tested with an openbmc image built from [2] plus a kernel
patch[3] for the SPI flash module.

1. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts?id=a8c729e966c4e9d033242d948b0e53c2a62d32e2
2. https://github.com/openbmc/openbmc/commit/b9432b980d7f63f7512ffbcc7124386ba896dfc6
3. https://github.com/openbmc/linux/commit/25b566b9a9d7f5d4f10c1b7304007bdb286eefd7

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg : increased number of FMC devices to 2 to match Linux dts ]
Message-Id: <20220305000656.1944589-2-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agohw/arm/aspeed: allow missing spi_model
Patrick Williams [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
hw/arm/aspeed: allow missing spi_model

Generally all BMCs will use the fmc_model to hold their own flash
and most will have a spi_model to hold the managed system's flash,
but not all systems do.  Add a simple NULL check to allow a system
to set the spi_model as NULL to indicate it should not be instantiated.

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Message-Id: <20220305000656.1944589-1-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agohw/block: m25p80: Add support for w25q01jvq
Patrick Williams [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
hw/block: m25p80: Add support for w25q01jvq

The w25q01jvq is a 128MB part.  Support is being added to the kernel[1]
and the two have been tested together.

1. https://lore.kernel.org/lkml/20220222092222.23108-1-potin.lai@quantatw.com/

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Cc: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220304180920.1780992-1-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed/smc: Fix error log
Cédric Le Goater [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed/smc: Fix error log

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220307071856.1410731-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed/smc: Let the SSI core layer define the bus name
Cédric Le Goater [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed/smc: Let the SSI core layer define the bus name

If no id is provided, qdev automatically assigns an unique name with
the following pattern "<type>.<index>" which avoids bus name collision
when using multiple buses.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220307071856.1410731-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed/smc: Rename 'max_peripherals' to 'cs_num_max'
Cédric Le Goater [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed/smc: Rename 'max_peripherals' to 'cs_num_max'

The naming makes more sense in a SPI controller model.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220307071856.1410731-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed/smc: Remove 'num_cs' field
Cédric Le Goater [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed/smc: Remove 'num_cs' field

It is not used anymore.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220307071856.1410731-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed: Rework aspeed_board_init_flashes() interface
Cédric Le Goater [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed: Rework aspeed_board_init_flashes() interface

Currently, the allocation of the flash devices uses the number of
slave selects configured in the SoC realize routine. It is simpler to
use directly the number of FMC devices defined in the machine class
and 1 for spi devices (which is what the SoC does in the back of the
machine).

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220307071856.1410731-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed/smc: Use max number of CE instead of 'num_cs'
Cédric Le Goater [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed/smc: Use max number of CE instead of 'num_cs'

The Aspeed SMC model uses the 'num_cs' field to allocate resources
fitting the number of devices of the machine. This is a small
optimization without real need in the controller. Simplify modelling
and use the max_peripherals field instead.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220307071856.1410731-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoaspeed: Fix a potential memory leak bug in write_boot_rom()
Wentao_Liang [Tue, 8 Mar 2022 08:18:11 +0000 (09:18 +0100)]
aspeed: Fix a potential memory leak bug in write_boot_rom()

A memory chunk is allocated with g_new0() and assigned to the variable
'storage'. However, if the branch takes true, there will be only an
error report but not a free operation for 'storage' before function
returns. As a result, a memory leak bug is triggered.

Use g_autofree to fix the issue.

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com>
[ clg: reworked the commit log ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 years agoqemu-io: Allow larger write zeroes under no fallback
Eric Blake [Fri, 3 Dec 2021 23:15:28 +0000 (17:15 -0600)]
qemu-io: Allow larger write zeroes under no fallback

When writing zeroes can fall back to a slow write, permitting an
overly large request can become an amplification denial of service
attack in triggering a large amount of work from a small request.  But
the whole point of the no fallback flag is to quickly determine if
writing an entire device to zero can be done quickly (such as when it
is already known that the device started with zero contents); in those
cases, artificially capping things at 2G in qemu-io itself doesn't
help us.

Signed-off-by: Eric Blake <eblake@redhat.com>
Message-Id: <20211203231539.3900865-4-eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
2 years agoqemu-io: Utilize 64-bit status during map
Eric Blake [Fri, 3 Dec 2021 23:15:27 +0000 (17:15 -0600)]
qemu-io: Utilize 64-bit status during map

The block layer has supported 64-bit block status from drivers since
commit 86a3d5c688 ("block: Add .bdrv_co_block_status() callback",
v2.12) and friends, with individual driver callbacks responsible for
capping things where necessary.  Artificially capping things below 2G
in the qemu-io 'map' command, added in commit d6a644bbfe ("block: Make
bdrv_is_allocated() byte-based", v2.10) is thus no longer necessary.

One way to test this is with qemu-nbd as server on a raw file larger
than 4G (the entire file should show as allocated), plus 'qemu-io -f
raw -c map nbd://localhost --trace=nbd_\*' as client.  Prior to this
patch, the NBD_CMD_BLOCK_STATUS requests are fragmented at 0x7ffffe00
distances; with this patch, the fragmenting changes to 0x7fffffff
(since the NBD protocol is currently still limited to 32-bit
transactions - see block/nbd.c:nbd_client_co_block_status).  Then in
later patches, once I add an NBD extension for a 64-bit block status,
the same map command completes with just one NBD_CMD_BLOCK_STATUS.

Signed-off-by: Eric Blake <eblake@redhat.com>
Message-Id: <20211203231539.3900865-3-eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
2 years agonbd/server: Minor cleanups
Eric Blake [Fri, 3 Dec 2021 23:15:26 +0000 (17:15 -0600)]
nbd/server: Minor cleanups

Spelling fixes, grammar improvements and consistent spacing, noticed
while preparing other patches in this file.

Signed-off-by: Eric Blake <eblake@redhat.com>
Message-Id: <20211203231539.3900865-2-eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
2 years agotests/qemu-iotests: validate NBD TLS with UNIX sockets and PSK
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:10 +0000 (19:36 +0000)]
tests/qemu-iotests: validate NBD TLS with UNIX sockets and PSK

This validates that connections to an NBD server running on a UNIX
socket can use TLS with pre-shared keys (PSK).

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-13-berrange@redhat.com>
[eblake: squash in rebase fix]
Tested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agotests/qemu-iotests: validate NBD TLS with UNIX sockets
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:09 +0000 (19:36 +0000)]
tests/qemu-iotests: validate NBD TLS with UNIX sockets

This validates that connections to an NBD server running on a UNIX
socket can use TLS, and require a TLS hostname override to pass
certificate validation.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-12-berrange@redhat.com>
[eblake: squash in rebase fix]
Tested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agotests/qemu-iotests: validate NBD TLS with hostname mismatch
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:08 +0000 (19:36 +0000)]
tests/qemu-iotests: validate NBD TLS with hostname mismatch

This validates that connections to an NBD server where the certificate
hostname does not match will fail. It further validates that using the
new 'tls-hostname' override option can solve the failure.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-11-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agotests/qemu-iotests: convert NBD TLS test to use standard filters
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:07 +0000 (19:36 +0000)]
tests/qemu-iotests: convert NBD TLS test to use standard filters

Using standard filters is more future proof than rolling our own.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-10-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agotests/qemu-iotests: introduce filter for qemu-nbd export list
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:06 +0000 (19:36 +0000)]
tests/qemu-iotests: introduce filter for qemu-nbd export list

Introduce a filter for the output of qemu-nbd export list so it can be
reused in multiple tests.

The filter is a bit more permissive that what test 241 currently uses,
as its allows printing of the export count, along with any possible
error messages that might be emitted.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-9-berrange@redhat.com>
Tested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agoroms/openbios: update OpenBIOS images to 0e0afae6 built from submodule
Mark Cave-Ayland [Mon, 7 Mar 2022 23:11:24 +0000 (23:11 +0000)]
roms/openbios: update OpenBIOS images to 0e0afae6 built from submodule

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2 years agohw/acpi/microvm: turn on 8042 bit in FADT boot architecture flags if present
Ani Sinha [Fri, 4 Mar 2022 15:40:32 +0000 (21:10 +0530)]
hw/acpi/microvm: turn on 8042 bit in FADT boot architecture flags if present

The second bit of IAPC_BOOT_ARCH in FADT table indicates the presence of
keyboard controller implemented as 8042 or equivalent micro controller. This
change enables this flag for microvms if such a device exists (for example,
when added explicitly from the QEMU commandline). Change
654701e292d98b308b0 ("hw/acpi: add indication for i8042 in IA-PC boot flags of the FADT table")
enabled this flag for i386 q35 based machines. The reason for doing the same
for micro-vms is to make sure we provide the correct tables to the guest OS
uniformly in all cases when an i8042 device is present. When this bit is not
enabled, guest OSes has to find other indirect methods to detect the device
which we would like to avoid.

Signed-off-by: Ani Sinha <ani@anisinha.ca>
Message-Id: <20220304154032.2071585-5-ani@anisinha.ca>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2 years agotests/qemu-iotests: expand _filter_nbd rules
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:05 +0000 (19:36 +0000)]
tests/qemu-iotests: expand _filter_nbd rules

Some tests will want to use 'localhost' instead of '127.0.0.1', and
some will use the image options syntax rather than the classic URI
syntax.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-8-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agotests/qemu-iotests: add QEMU_IOTESTS_REGEN=1 to update reference file
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:04 +0000 (19:36 +0000)]
tests/qemu-iotests: add QEMU_IOTESTS_REGEN=1 to update reference file

When developing an I/O test it is typical to add some logic to the
test script, run it to view the output diff, and then apply the
output diff to the reference file. This can be drastically simplified
by letting the test runner update the reference file in place.

By setting 'QEMU_IOTESTS_REGEN=1', the test runner will report the
failure and show the diff, but at the same time update the reference
file. So next time the I/O test is run it will succeed.

Continuing to display the diff when updating the reference gives the
developer a chance to review what was changed.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-7-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agoblock/nbd: don't restrict TLS usage to IP sockets
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:03 +0000 (19:36 +0000)]
block/nbd: don't restrict TLS usage to IP sockets

The TLS usage for NBD was restricted to IP sockets because validating
x509 certificates requires knowledge of the hostname that the client
is connecting to.

TLS does not have to use x509 certificates though, as PSK (pre-shared
keys) provide an alternative credential option. These have no
requirement for a hostname and can thus be trivially used for UNIX
sockets.

Furthermore, with the ability to overide the default hostname for
TLS validation in the previous patch, it is now also valid to want
to use x509 certificates with FD passing and UNIX sockets.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-6-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agoqemu-nbd: add --tls-hostname option for TLS certificate validation
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:02 +0000 (19:36 +0000)]
qemu-nbd: add --tls-hostname option for TLS certificate validation

When using the --list option, qemu-nbd acts as an NBD client rather
than a server. As such when using TLS, it has a need to validate
the server certificate. This adds a --tls-hostname option which can
be used to override the default hostname used for certificate
validation.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-5-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agoblock/nbd: support override of hostname for TLS certificate validation
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:01 +0000 (19:36 +0000)]
block/nbd: support override of hostname for TLS certificate validation

When connecting to an NBD server with TLS and x509 credentials,
the client must validate the hostname it uses for the connection,
against that published in the server's certificate. If the client
is tunnelling its connection over some other channel, however, the
hostname it uses may not match the info reported in the server's
certificate. In such a case, the user needs to explicitly set an
override for the hostname to use for certificate validation.

This is achieved by adding a 'tls-hostname' property to the NBD
block driver.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-4-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agoblock: pass desired TLS hostname through from block driver client
Daniel P. Berrangé [Fri, 4 Mar 2022 19:36:00 +0000 (19:36 +0000)]
block: pass desired TLS hostname through from block driver client

In

  commit a71d597b989fd701b923f09b3c20ac4fcaa55e81
  Author: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
  Date:   Thu Jun 10 13:08:00 2021 +0300

    block/nbd: reuse nbd_co_do_establish_connection() in nbd_open()

the use of the 'hostname' field from the BDRVNBDState struct was
lost, and 'nbd_connect' just hardcoded it to match the IP socket
address. This was a harmless bug at the time since we block use
with anything other than IP sockets.

Shortly though, we want to allow the caller to override the hostname
used in the TLS certificate checks. This is to allow for TLS
when doing port forwarding or tunneling. Thus we need to reinstate
the passing along of the 'hostname'.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-3-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agocrypto: mandate a hostname when checking x509 creds on a client
Daniel P. Berrangé [Fri, 4 Mar 2022 19:35:59 +0000 (19:35 +0000)]
crypto: mandate a hostname when checking x509 creds on a client

Currently the TLS session object assumes that the caller will always
provide a hostname when using x509 creds on a client endpoint. This
relies on the caller to detect and report an error if the user has
configured QEMU with x509 credentials on a UNIX socket. The migration
code has such a check, but it is too broad, reporting an error when
the user has configured QEMU with PSK credentials on a UNIX socket,
where hostnames are irrelevant.

Putting the check into the TLS session object credentials validation
code ensures we report errors in only the scenario that matters.

Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20220304193610.3293146-2-berrange@redhat.com>
Signed-off-by: Eric Blake <eblake@redhat.com>
2 years agoscripts/qmp-shell-wrap: Fix import path
John Snow [Fri, 25 Feb 2022 17:08:28 +0000 (12:08 -0500)]
scripts/qmp-shell-wrap: Fix import path

Mea culpa. Dan's patch wound up with the wrong import path because I
re-ordered my most recent pull request and missed that this needed a fix
on rebase.

Fixes: 43912529
Reported-by: Kashyap Chamarthy <kchamart@redhat.com>
Signed-off-by: John Snow <jsnow@redhat.com>
Tested-by: Kashyap Chamarthy <kchamart@redhat.com>
Message-id: 20220225170828.3418305-1-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: drop _bind_hack()
John Snow [Fri, 25 Feb 2022 20:59:48 +0000 (15:59 -0500)]
python/aqmp: drop _bind_hack()

_bind_hack() was a quick fix to allow async QMP to call bind(2) prior to
calling listen(2) and accept(2). This wasn't sufficient to fully address
the race condition present in synchronous clients.

With the race condition in legacy.py fixed (see the previous commit),
there are no longer any users of _bind_hack(). Drop it.

Fixes: b0b662bb2b3
Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-11-jsnow@redhat.com
[Expanded commit message. --js]
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: fix race condition in legacy.py
John Snow [Fri, 25 Feb 2022 20:59:47 +0000 (15:59 -0500)]
python/aqmp: fix race condition in legacy.py

legacy.py provides a synchronous model. iotests frequently uses this
paradigm:

 - create QMP client object
 - start QEMU process
 - await connection from QEMU process

In the switch from sync to async QMP, the QMP client object stopped
calling bind() and listen() during the QMP object creation step, which
creates a race condition if the QEMU process dials in too quickly.

With refactoring out of the way, restore the former behavior of calling
bind() and listen() during __init__() to fix this race condition.

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-10-jsnow@redhat.com
[Expanded commit message. --js]
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: add start_server() and accept() methods
John Snow [Fri, 25 Feb 2022 20:59:46 +0000 (15:59 -0500)]
python/aqmp: add start_server() and accept() methods

Add start_server() and accept() methods that can be used instead of
start_server_and_accept() to allow more fine-grained control over the
incoming connection process.

(Eagle-eyed reviewers will surely notice that it's a bit weird that
"CONNECTING" is a state that's shared between both the start_server()
and connect() states. That's absolutely true, and it's very true that
checking on the presence of _accepted as an indicator of state is a
hack. That's also very certainly true. But ... this keeps client code an
awful lot simpler, as it doesn't have to care exactly *how* the
connection is being made, just that it *is*. Is it worth disrupting that
simplicity in order to provide a better state guard on `accept()`? Hm.)

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-9-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: stop the server during disconnect()
John Snow [Fri, 25 Feb 2022 20:59:45 +0000 (15:59 -0500)]
python/aqmp: stop the server during disconnect()

Before we allow the full separation of starting the server and accepting
new connections, make sure that the disconnect cleans up the server and
its new state, too.

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-8-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: refactor _do_accept() into two distinct steps
John Snow [Fri, 25 Feb 2022 20:59:44 +0000 (15:59 -0500)]
python/aqmp: refactor _do_accept() into two distinct steps

Refactor _do_accept() into _do_start_server() and _do_accept(). As of
this commit, the former calls the latter, but in subsequent commits
they'll be split apart.

(So please forgive the misnomer for _do_start_server(); it will live up
to its name shortly, and the docstring will be updated then too. I'm
just cutting down on some churn.)

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-7-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: squelch pylint warning for too many lines
John Snow [Fri, 25 Feb 2022 20:59:43 +0000 (15:59 -0500)]
python/aqmp: squelch pylint warning for too many lines

I would really like to keep this under 1000 lines, I promise. Doesn't
look like it's gonna happen.

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-6-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: split _client_connected_cb() out as _incoming()
John Snow [Fri, 25 Feb 2022 20:59:42 +0000 (15:59 -0500)]
python/aqmp: split _client_connected_cb() out as _incoming()

As part of disentangling the monolithic nature of _do_accept(), split
out the incoming callback to prepare for factoring out the "wait for a
peer" step. Namely, this means using an event signal we can wait on from
outside of this method.

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-5-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: remove _new_session and _establish_connection
John Snow [Fri, 25 Feb 2022 20:59:41 +0000 (15:59 -0500)]
python/aqmp: remove _new_session and _establish_connection

These two methods attempted to entirely envelop the logic of
establishing a connection to a peer start to finish. However, we need to
break apart the incoming connection step into more granular steps. We
will no longer be able to reasonably constrain the logic inside of these
helper functions.

So, remove them - with _session_guard(), they no longer serve a real
purpose.

Although the public API doesn't change, the internal API does. Now that
there are no intermediary methods between e.g. connect() and
_do_connect(), there's no hook where the runstate is set. As a result,
the test suite changes a little to cope with the new semantics of
_do_accept() and _do_connect().

Lastly, take some pieces of the now-deleted docstrings and move
them up to the public interface level. They were a little more detailed,
and it won't hurt to keep them.

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-4-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: rename 'accept()' to 'start_server_and_accept()'
John Snow [Fri, 25 Feb 2022 20:59:40 +0000 (15:59 -0500)]
python/aqmp: rename 'accept()' to 'start_server_and_accept()'

Previously, I had a method named "accept()" that under-the-hood calls
bind(2), listen(2) *and* accept(2). I meant this as a simplification and
counterpart to the one-shot "connect()" method.

This is confusing to readers who expect accept() to mean *just*
accept(2). Since I need to split apart the "accept()" method into
multiple methods anyway (one of which strongly resembling accept(2)), it
feels pertinent to rename this method *now*.

Rename this all-in-one method "start_server_and_accept()" instead.

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-3-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agopython/aqmp: add _session_guard()
John Snow [Fri, 25 Feb 2022 20:59:39 +0000 (15:59 -0500)]
python/aqmp: add _session_guard()

In _new_session, there's a fairly complex except clause that's used to
give semantic errors to callers of accept() and connect(). We need to
create a new two-step replacement for accept(), so factoring out this
piece of logic will be useful.

Bolster the comments and docstring here to try and demystify what's
going on in this fairly delicate piece of Python magic.

(If we were using Python 3.7+, this would be an @asynccontextmanager. We
don't have that very nice piece of magic, however, so this must take an
Awaitable to manage the Exception contexts properly. We pay the price
for platform compatibility.)

Signed-off-by: John Snow <jsnow@redhat.com>
Acked-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20220225205948.3693480-2-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agotarget/mips: Remove duplicated MIPSCPU::cp0_count_rate
Philippe Mathieu-Daudé [Mon, 13 Dec 2021 10:06:07 +0000 (11:06 +0100)]
target/mips: Remove duplicated MIPSCPU::cp0_count_rate

Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>

2 years agotarget/mips: Fix cycle counter timing calculations
Simon Burge [Mon, 13 Dec 2021 13:51:27 +0000 (00:51 +1100)]
target/mips: Fix cycle counter timing calculations

The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
constant in target/mips/cpu.c.  The cycle counter resolution is defined
per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
cp0_count_ns.  Fixings timing problems on guest OSs for the 20Kc CPU
which has a CCRes of 1.

Signed-off-by: Simon Burge <simonb@NetBSD.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211213135125.18378-1-simonb@NetBSD.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agoMerge remote-tracking branch 'remotes/philmd/tags/abstract-arch-cpu-20220307' into...
Peter Maydell [Mon, 7 Mar 2022 19:07:44 +0000 (19:07 +0000)]
Merge remote-tracking branch 'remotes/philmd/tags/abstract-arch-cpu-20220307' into staging

- Re-org accel/ and softmmu/ to have more target-agnostic objects.

- Use CPUArchState as an abstract type, defined by each target
  (CPUState is our interface with generic code, CPUArchState is
   our interface with target-specific code).

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* remotes/philmd/tags/abstract-arch-cpu-20220307: (33 commits)
  accel/tcg: Remove pointless CPUArchState casts
  target/i386: Remove pointless CPUArchState casts
  target: Use ArchCPU as interface to target CPU
  target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro
  target: Use CPUArchState as interface to target-specific CPU state
  target: Use forward declared type instead of structure type
  target/hexagon: Add missing 'hw/core/cpu.h' include
  target: Include missing 'cpu.h'
  Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE
  target/i386/tcg/sysemu: Include missing 'exec/exec-all.h' header
  cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers
  exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition
  meson: Display libfdt as disabled when system emulation is disabled
  softmmu: Build target-agnostic objects once
  softmmu: Add qemu_init_arch_modules()
  exec/cpu: Make address_space_init/reloading_memory_map target agnostic
  exec/gdbstub: Make gdb_exit() / gdb_set_stop_cpu() target agnostic
  misc: Add missing "sysemu/cpu-timers.h" include
  misc: Remove unnecessary "sysemu/cpu-timers.h" include
  softmmu/cpu-timers: Remove unused 'exec/exec-all.h' header
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoCheck and report for incomplete 'global' option format
Rohit Kumar [Wed, 16 Feb 2022 07:15:08 +0000 (23:15 -0800)]
Check and report for incomplete 'global' option format

Qemu might crash when provided incomplete '-global' option.
For example:
     qemu-system-x86_64 -global driver=isa-fdc
     qemu-system-x86_64: ../../devel/qemu/qapi/string-input-visitor.c:394:
     string_input_visitor_new: Assertion `str' failed.
     Aborted (core dumped)

Fixes: 3751d7c43f795b ("vl: allow full-blown QemuOpts syntax for -global")
Signed-off-by: Rohit Kumar <rohit.kumar3@nutanix.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/604
Message-Id: <20220216071508.412974-1-rohit.kumar3@nutanix.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2 years agotests/vm: Update haiku test vm to R1/Beta3
Thomas Huth [Mon, 7 Mar 2022 09:27:12 +0000 (10:27 +0100)]
tests/vm: Update haiku test vm to R1/Beta3

The old image did not have python3 yet, and thus was not usable
for compiling QEMU anymore.

Suggested-by: Alexander von Gluck IV <kallisti5@unixzen.com>
Message-Id: <20220216154208.2985103-1-kallisti5@unixzen.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2 years agotests/avocado: Cancel BootLinux tests in case there is no free port
Thomas Huth [Mon, 28 Feb 2022 11:43:25 +0000 (12:43 +0100)]
tests/avocado: Cancel BootLinux tests in case there is no free port

The BootLinux tests are currently failing with an ugly python
stack trace on my RHEL8 system since they cannot get a free port
(likely due to the firewall settings on my system). Let's properly
check the return value of find_free_port() instead and cancel the
test gracefully if it cannot get a free port.

Message-Id: <20220228114325.818294-1-thuth@redhat.com>
Reviewed-by: Beraldo Leal <bleal@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2 years agoMerge remote-tracking branch 'remotes/hreitz-gitlab/tags/pull-block-2022-03-07' into...
Peter Maydell [Mon, 7 Mar 2022 17:14:09 +0000 (17:14 +0000)]
Merge remote-tracking branch 'remotes/hreitz-gitlab/tags/pull-block-2022-03-07' into staging

Block patches for 7.0-rc0:
- New fleecing backup scheme
- iotest fixes
- Fixes for the curl block driver
- Fix for the preallocate block driver
- IDE fix for zero-length TRIM requests

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* remotes/hreitz-gitlab/tags/pull-block-2022-03-07: (23 commits)
  iotests/image-fleecing: test push backup with fleecing
  iotests/image-fleecing: add test case with bitmap
  iotests.py: add qemu_io_pipe_and_status()
  iotests/image-fleecing: add test-case for fleecing format node
  block: copy-before-write: realize snapshot-access API
  block: introduce snapshot-access block driver
  block/io: introduce block driver snapshot-access API
  block/reqlist: add reqlist_wait_all()
  block/dirty-bitmap: introduce bdrv_dirty_bitmap_status()
  block/reqlist: reqlist_find_conflict(): use ranges_overlap()
  block: intoduce reqlist
  block/block-copy: add block_copy_reset()
  block/copy-before-write: add bitmap open parameter
  block/block-copy: block_copy_state_new(): add bitmap parameter
  block/dirty-bitmap: bdrv_merge_dirty_bitmap(): add return value
  block/block-copy: move copy_bitmap initialization to block_copy_state_new()
  iotests: Write test output to TEST_DIR
  tests/qemu-iotests/testrunner: Quote "case not run" lines in TAP mode
  tests/qemu-iotests/040: Skip TestCommitWithFilters without 'throttle'
  block: fix preallocate filter: don't do unaligned preallocate requests
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/virt: Disable LPA2 for -machine virt-6.2
Richard Henderson [Tue, 1 Mar 2022 21:59:58 +0000 (11:59 -1000)]
hw/arm/virt: Disable LPA2 for -machine virt-6.2

There is a Linux kernel bug present until v5.12 that prevents
booting with FEAT_LPA2 enabled.  As a workaround for TCG,
disable this feature for machine versions prior to 7.0.

Cc: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Provide cpu property for controling FEAT_LPA2
Richard Henderson [Tue, 1 Mar 2022 21:59:57 +0000 (11:59 -1000)]
target/arm: Provide cpu property for controling FEAT_LPA2

There is a Linux kernel bug present until v5.12 that prevents
booting with FEAT_LPA2 enabled.  As a workaround for TCG, allow
the feature to be disabled from -cpu max.

Since this kernel bug is present in the Fedora 31 image that
we test in avocado, disable lpa2 on the command-line.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoui/cocoa: Use the standard about panel
Akihiko Odaki [Sun, 27 Feb 2022 04:22:41 +0000 (13:22 +0900)]
ui/cocoa: Use the standard about panel

This provides standard look and feel for the about panel and reduces
code.

Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Message-id: 20220227042241.1543-1-akihiko.odaki@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event
Peter Maydell [Thu, 3 Mar 2022 20:23:41 +0000 (20:23 +0000)]
hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace event

The trace_gicv3_icv_hppir_read trace event takes an integer value
which it uses to form the register name, which should be either
ICV_HPPIR0 or ICV_HPPIR1.  We were passing in the 'grp' variable for
this, but that is either GICV3_G0 or GICV3_G1NS, which happen to be 0
and 2, which meant that tracing for the ICV_HPPIR1 register was
incorrectly printed as ICV_HPPIR2.

Use the same approach we do for all the other similar trace events,
and pass in 'ri->crm == 8 ?  0 : 1', deriving the index value
directly from the ARMCPRegInfo struct.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-6-peter.maydell@linaro.org

2 years agohw/intc/arm_gicv3: Fix missing spaces in error log messages
Peter Maydell [Thu, 3 Mar 2022 20:23:40 +0000 (20:23 +0000)]
hw/intc/arm_gicv3: Fix missing spaces in error log messages

We forgot a space in some log messages, so the output ended
up looking like
gicv3_dist_write: invalid guest write at offset 0000000000008000size 8

with a missing space before "size". Add the missing spaces.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-5-peter.maydell@linaro.org

2 years agohw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps
Peter Maydell [Thu, 3 Mar 2022 20:23:39 +0000 (20:23 +0000)]
hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps

The GICv3 has some registers that support byte accesses, and some
that support 8-byte accesses.  Our TCG implementation implements all
of this, switching on the 'size' argument and handling the registers
that must support reads of that size while logging an error for
attempted accesses to registers that do not support that size access.
However we forgot to tell the core memory subsystem about this by
specifying the .impl and .valid fields in the MemoryRegionOps struct,
so the core was happily simulating 8 byte accesses by combining two 4
byte accesses.  This doesn't have much guest-visible effect, since
there aren't many 8 byte registers and they all support being written
in two 4 byte parts.

Set the .impl and .valid fields to say that all sizes from 1 to 8
bytes are both valid and implemented by the device.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-4-peter.maydell@linaro.org

2 years agohw/intc/arm_gicv3_its: Add trace events for table reads and writes
Peter Maydell [Thu, 3 Mar 2022 20:23:38 +0000 (20:23 +0000)]
hw/intc/arm_gicv3_its: Add trace events for table reads and writes

For debugging guest use of the ITS, it can be helpful to trace
when the ITS reads and writes the in-memory tables.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-3-peter.maydell@linaro.org

2 years agohw/intc/arm_gicv3_its: Add trace events for commands
Peter Maydell [Thu, 3 Mar 2022 20:23:37 +0000 (20:23 +0000)]
hw/intc/arm_gicv3_its: Add trace events for commands

When debugging code that's using the ITS, it's helpful to
see tracing of the ITS commands that the guest executes. Add
suitable trace events.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303202341.2232284-2-peter.maydell@linaro.org

2 years agotarget/arm/translate-neon: Simplify align field check for VLD3
Peter Maydell [Thu, 3 Mar 2022 11:37:41 +0000 (11:37 +0000)]
target/arm/translate-neon: Simplify align field check for VLD3

For VLD3 (single 3-element structure to one lane), there is no
alignment specification and the alignment bits in the instruction
must be zero.  This is bit [4] for the size=0 and size=1 cases, and
bits [5:4] for the size=2 case.  We do this check correctly in
VLDST_single(), but we write it a bit oddly: in the 'case 3' code we
check for bit 0 of a->align (bit [4] of the insn), and then we fall
through to the 'case 2' code which checks bit 1 of a->align (bit [5]
of the insn) in the size 2 case.  Replace this with just checking "is
a->align non-zero" for VLD3, which lets us drop the fall-through and
put the cases in this switch in numerical order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303113741.2156877-3-peter.maydell@linaro.org

2 years agotarget/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero
Peter Maydell [Thu, 3 Mar 2022 11:37:40 +0000 (11:37 +0000)]
target/arm/translate-neon: UNDEF if VLD1/VST1 stride bits are non-zero

For VLD1/VST1 (single element to one lane) we are only accessing one
register, and so the 'stride' is meaningless.  The bits that would
specify stride (insn bit [4] for size=1, bit [6] for size=2) are
specified to be zero in the encoding (which would correspond to a
stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are
not.

We failed to make this check, which meant that we would incorrectly
handle some instruction patterns as loads or stores instead of
UNDEFing them. Enforce that stride == 1 for the nregs == 1 case.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/890
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220303113741.2156877-2-peter.maydell@linaro.org

2 years agoosdep: Move memalign-related functions to their own header
Peter Maydell [Sat, 26 Feb 2022 18:07:23 +0000 (18:07 +0000)]
osdep: Move memalign-related functions to their own header

Move the various memalign-related functions out of osdep.h and into
their own header, which we include only where they are used.
While we're doing this, add some brief documentation comments.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220226180723.1706285-10-peter.maydell@linaro.org

2 years agoutil: Put qemu_vfree() in memalign.c
Peter Maydell [Sat, 26 Feb 2022 18:07:22 +0000 (18:07 +0000)]
util: Put qemu_vfree() in memalign.c

qemu_vfree() is the companion free function to qemu_memalign(); put
it in memalign.c so the allocation and free functions are together.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-9-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agoutil: Use meson checks for valloc() and memalign() presence
Peter Maydell [Sat, 26 Feb 2022 18:07:21 +0000 (18:07 +0000)]
util: Use meson checks for valloc() and memalign() presence

Instead of assuming that all CONFIG_BSD have valloc() and anything
else is memalign(), explicitly check for those functions in
meson.build and use the "is the function present" define.  Tests for
specific functionality are better than which-OS checks; this also
lets us give a helpful error message if somehow there's no usable
function present.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220226180723.1706285-8-peter.maydell@linaro.org

2 years agoutil: Share qemu_try_memalign() implementation between POSIX and Windows
Peter Maydell [Sat, 26 Feb 2022 18:07:20 +0000 (18:07 +0000)]
util: Share qemu_try_memalign() implementation between POSIX and Windows

The qemu_try_memalign() functions for POSIX and Windows used to be
significantly different, but these days they are identical except for
the actual allocation function called, and the POSIX version already
has to have ifdeffery for different allocation functions.

Move to a single implementation in memalign.c, which uses the Windows
_aligned_malloc if we detect that function in meson.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-7-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agomeson.build: Don't misdetect posix_memalign() on Windows
Peter Maydell [Sat, 26 Feb 2022 18:07:19 +0000 (18:07 +0000)]
meson.build: Don't misdetect posix_memalign() on Windows

Currently we incorrectly think that posix_memalign() exists on
Windows.  This is because of a combination of:

 * the msys2/mingw toolchain/libc claim to have a
   __builtin_posix_memalign when there isn't a builtin of that name
 * meson will assume that if you have a __builtin_foo that
   counts for has_function('foo')

Specifying a specific include file via prefix: causes meson to not
treat builtins as sufficient and actually look for the function
itself; see this meson pull request which added that as the official
way to get the right answer:
  https://github.com/mesonbuild/meson/pull/1150

Currently this misdectection doesn't cause problems because we only
use CONFIG_POSIX_MEMALIGN in oslib-posix.c; however that will change
in a following commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220226180723.1706285-6-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2 years agoutil: Return valid allocation for qemu_try_memalign() with zero size
Peter Maydell [Sat, 26 Feb 2022 18:07:18 +0000 (18:07 +0000)]
util: Return valid allocation for qemu_try_memalign() with zero size

Currently qemu_try_memalign()'s behaviour if asked to allocate
0 bytes is rather variable:
 * on Windows, we will assert
 * on POSIX platforms, we get the underlying behaviour of
   the posix_memalign() or equivalent function, which may be
   either "return a valid non-NULL pointer" or "return NULL"

Explictly check for 0 byte allocations, so we get consistent
behaviour across platforms.  We handle them by incrementing the size
so that we return a valid non-NULL pointer that can later be passed
to qemu_vfree().  This is permitted behaviour for the
posix_memalign() API and is the most usual way that underlying
malloc() etc implementations handle a zero-sized allocation request,
because it won't trip up calling code that assumes NULL means an
error.  (This includes our own qemu_memalign(), which will abort on
NULL.)

This change is a preparation for sharing the qemu_try_memalign() code
between Windows and POSIX.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>