OSDN Git Service
David Majnemer [Fri, 26 Feb 2016 00:04:25 +0000 (00:04 +0000)]
[WinEH] Don't remove unannotated inline-asm calls
Inline-asm calls aren't annotated with funclet bundle operands because
they don't throw and cannot be inlined through. We shouldn't require
them to bear an funclet bundle operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261942
91177308-0d34-0410-b5e6-
96231b3b80d8
Owen Anderson [Thu, 25 Feb 2016 23:34:21 +0000 (23:34 +0000)]
More internal details of SROA pass to library visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261934
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Thu, 25 Feb 2016 22:05:19 +0000 (22:05 +0000)]
Support: Give ManagedStatic's helper object library visibility
It doesn't make much sense to export these symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261931
91177308-0d34-0410-b5e6-
96231b3b80d8
Hemant Kulkarni [Thu, 25 Feb 2016 20:47:07 +0000 (20:47 +0000)]
Reverts change r261907 and r261918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261927
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 19:16:40 +0000 (19:16 +0000)]
Use regex in testcase, do not fail windows bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261922
91177308-0d34-0410-b5e6-
96231b3b80d8
Hemant Kulkarni [Thu, 25 Feb 2016 18:56:01 +0000 (18:56 +0000)]
Fix endianness issue on BE machines introduced by r261907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261918
91177308-0d34-0410-b5e6-
96231b3b80d8
David L Kreitzer [Thu, 25 Feb 2016 18:50:45 +0000 (18:50 +0000)]
Reformatted a comment to fit the 80 column limit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261916
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 18:24:19 +0000 (18:24 +0000)]
Try to fix windows fail at r261902.
Introduce move constructor and move assignment operator to PostDominatorTree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261910
91177308-0d34-0410-b5e6-
96231b3b80d8
Hemant Kulkarni [Thu, 25 Feb 2016 18:02:00 +0000 (18:02 +0000)]
[llvm-readobj] Enable GNU style sections and relocations printing
http://reviews.llvm.org/D17523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261907
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 17:54:25 +0000 (17:54 +0000)]
Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC
Differential Revision: http://reviews.llvm.org/D17571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261904
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 17:54:15 +0000 (17:54 +0000)]
Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC
Differential Revision: http://reviews.llvm.org/D17570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261903
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 17:54:07 +0000 (17:54 +0000)]
Introduce analysis pass to compute PostDominators in the new pass manager. NFC
Differential Revision: http://reviews.llvm.org/D17537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261902
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Thu, 25 Feb 2016 16:54:52 +0000 (16:54 +0000)]
ARM: disallow pc as a base register in Thumb2 memory ops.
These should all be deferring to the "OP (literal)" variant according to the
ARM ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261895
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 16:45:53 +0000 (16:45 +0000)]
Revert "Introduce analysis pass to compute PostDominators in the new pass manager. NFC"
This reverts commit
a3e5cc6a51ab5ad88d1760c63284294a4e34c018.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261891
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 16:45:46 +0000 (16:45 +0000)]
Revert "Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC"
This reverts commit
109c38b2226a87b0be73fa7a0a8c1a81df20aeb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261890
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 16:45:37 +0000 (16:45 +0000)]
Revert "Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC"
This reverts commit
8228b4d374edeb4cc0c5fddf6e1ab876918ee126.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261889
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 25 Feb 2016 16:44:27 +0000 (16:44 +0000)]
rangify; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261888
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Thu, 25 Feb 2016 16:36:08 +0000 (16:36 +0000)]
[AArch64] Clean up callee-save CFI emission. NFC.
Summary:
Avoid special case for FP, LR CFI emission and just allow general
AArch64FrameLowering::emitCalleeSavedFrameMoves() to handle them. Also,
stop recalculating the stack offsets in emitCalleeSavedFrameMoves()
since we can just reuse the previously calculated offset stored in the
MachineFrameInfo.
Depends on D17000
Reviewers: t.p.northover, rengolin, mcrosier, jmolloy
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D17004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261885
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 16:33:26 +0000 (16:33 +0000)]
Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC
Differential Revision: http://reviews.llvm.org/D17571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261884
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 16:33:15 +0000 (16:33 +0000)]
Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC
Differential Revision: http://reviews.llvm.org/D17570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261883
91177308-0d34-0410-b5e6-
96231b3b80d8
Hongbin Zheng [Thu, 25 Feb 2016 16:33:06 +0000 (16:33 +0000)]
Introduce analysis pass to compute PostDominators in the new pass manager. NFC
Differential Revision: http://reviews.llvm.org/D17537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261882
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolay Haustov [Thu, 25 Feb 2016 16:09:14 +0000 (16:09 +0000)]
[AMDGPU] Disassembler: Support for all VOP1 instructions.
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget:
VGPR_32 and VReg_64 operand register classes
VS_32 and VS_64 operand register classes with inline and literal constants
Tests for VOP1 instructions.
Patch by: skolton
Reviewers: arsenm, tstellarAMD
Review: http://reviews.llvm.org/D17194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261878
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 25 Feb 2016 15:55:28 +0000 (15:55 +0000)]
don't repeat names in documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261877
91177308-0d34-0410-b5e6-
96231b3b80d8
Joerg Sonnenberger [Thu, 25 Feb 2016 15:00:14 +0000 (15:00 +0000)]
GC empty directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261871
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Breger [Thu, 25 Feb 2016 13:30:17 +0000 (13:30 +0000)]
AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.
Differential Revision: http://reviews.llvm.org/D17564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261862
91177308-0d34-0410-b5e6-
96231b3b80d8
Hrvoje Varga [Thu, 25 Feb 2016 12:53:29 +0000 (12:53 +0000)]
[mips][microMIPS] Implement DINSU, DINSM, DINS instructions
Differential Revision: http://reviews.llvm.org/D16181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261860
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolay Haustov [Thu, 25 Feb 2016 10:58:54 +0000 (10:58 +0000)]
[AMDGPU] Assembler: Simplify handling of optional operands
Resubmit with index problem fixed. Verified with valgrind.
Prepare to support DPP encodings.
For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands.
However this means that when parsing instruction which has no mnemonic prefix,
we cannot add both default values for VOP3 and for DPP optional operands
to OperandVector - neither instructions would match. So add default values
for optional operands to MCInst during conversion instead.
Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.
Review: http://reviews.llvm.org/D17445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261856
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Thu, 25 Feb 2016 10:27:39 +0000 (10:27 +0000)]
[PM] Add the IR unit type to the pass manager's logging and make all of
the testing more more explicit.
This will currently fail on platforms without support for getTypeName.
While an assert failure seems too harsh, I'm hoping we're OK with the
regression test failure, and I'd like to find out about what platforms
actually exist in this state if there are any so we can get
implementations in place for them.
But if we just can't fix all the host compilers to have a reasonably
portable variant of getTypeName and are worried about xfailing this test
on those platforms, I can add the horrible regular expression magic to
make the tests support "unknown" here as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261853
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 25 Feb 2016 09:12:12 +0000 (09:12 +0000)]
[X86][SSE3] Added combine support for MOVDDUP/MOVSHDUP/MOVSLDUP target shuffles
Now that PerformShuffleCombine can handle unary shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261843
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 25 Feb 2016 08:50:26 +0000 (08:50 +0000)]
Revert r260064, "Disable llvm/test/tools/llvm-profdata/value-prof.proftext on win32 for now. Investigating."
It seems unreproducible any more for me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261842
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Thu, 25 Feb 2016 08:35:27 +0000 (08:35 +0000)]
Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands"
It brought undefined behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261839
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Thu, 25 Feb 2016 07:23:08 +0000 (07:23 +0000)]
PM: Implement a basic loop pass manager
This creates the new-style LoopPassManager and wires it up with dummy
and print passes.
This version doesn't support modifying the loop nest at all. It will
be far easier to discuss and evaluate the approaches to that with this
in place so that the boilerplate is out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261831
91177308-0d34-0410-b5e6-
96231b3b80d8
Elena Demikhovsky [Thu, 25 Feb 2016 07:05:12 +0000 (07:05 +0000)]
Optimized loading (zextload) of i1 value from memory.
This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793.
Extra "and" causes performance degradation.
We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits.
Differential Revision: http://reviews.llvm.org/D17541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261828
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Thu, 25 Feb 2016 06:13:01 +0000 (06:13 +0000)]
[Support] Don't check for ICC directly and rely on the __GNUC__ check
(which they emulate). This way we don't use that path when compiled with
ICC on Windows where it mimics MSVC's behavior and supports __FUNCSIG__.
Thanks for David Majnemer again for spotting this better pattern!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261827
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Thu, 25 Feb 2016 03:58:21 +0000 (03:58 +0000)]
[Support] Add a fancy helper function to get a static name for a type.
This extracts the type name from __PRETTY_FUNCTION__ for compilers that
support it (I've opted Clang, GCC, and ICC into this as I've tested that
they work) and from __FUNCSIG__ which is very similar on MSVC. The
routine falls back gracefully on a stub "UNKNOWN_TYPE" string with
compilers or formats it doesn't understand.
This should be enough for a lot of common cases in LLVM where the real
goal is just to log or print a type name as a debugging aid, and save
a ton of boilerplate in the process. Notably, I'm planning to use this
to remove all the getName() boiler plate from the new pass manager.
The design and implementation is based on a bunch of advice and
discussion with Richard Smith and experimenting with most versions of
Clang and GCC. David Majnemer also provided excellent advice on how best
to do this with MSVC. Richard also checked that ICC does something
reasonable and I'll watch the build bots for other compilers. It'd be
great if someone could contribute logic for xlC and/or other toolchains.
Differential Revision: http://reviews.llvm.org/D17565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261819
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Thu, 25 Feb 2016 01:02:18 +0000 (01:02 +0000)]
IR: Make the X / undef -> undef fold match the comment
The constant folding for sdiv and udiv has a big discrepancy between the
comments and the code, which looks like a typo. Currently, we're folding
X / undef pretty inconsistently:
0 / undef -> undef
C / undef -> 0
undef / undef -> 0
Whereas the comments state we do X / undef -> undef. The logic that
returns zero is actually commented as doing undef / X -> 0, despite that
the LHS isn't undef in many of the cases that hit it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261813
91177308-0d34-0410-b5e6-
96231b3b80d8
Junmo Park [Thu, 25 Feb 2016 00:23:27 +0000 (00:23 +0000)]
[CodeGenPrepare] Remove load-based heuristic
Summary:
Both the hardware and LLVM have changed since 2012.
Now, load-based heuristic don't show big differences any more on OoO cores.
There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5).
Reviewers: spatel, zansari
Differential Revision: http://reviews.llvm.org/D16836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261809
91177308-0d34-0410-b5e6-
96231b3b80d8
Cong Hou [Thu, 25 Feb 2016 00:12:18 +0000 (00:12 +0000)]
Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261807
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Feb 2016 23:44:19 +0000 (23:44 +0000)]
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261805
91177308-0d34-0410-b5e6-
96231b3b80d8
Cong Hou [Wed, 24 Feb 2016 23:40:36 +0000 (23:40 +0000)]
Detecte vector reduction operations just before instruction selection.
(This is the second attemp to commit this patch, after fixing pr26652 & pr26653).
This patch detects vector reductions before instruction selection. Vector
reductions are vectorized reduction operations, and for such operations we have
freedom to reorganize the elements of the result as long as the reduction of them
stay unchanged. This will enable some reduction pattern recognition during
instruction combine such as SAD/dot-product on X86. A flag is added to
SDNodeFlags to mark those vector reduction nodes to be checked during instruction
combine.
To detect those vector reductions, we search def-use chains starting from the
given instruction, and check if all uses fall into two categories:
1. Reduction with another vector.
2. Reduction on all elements.
in which 2 is detected by recognizing the pattern that the loop vectorizer
generates to reduce all elements in the vector outside of the loop, which
includes several ShuffleVector and one ExtractElement instructions.
Differential revision: http://reviews.llvm.org/D15250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261804
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Feb 2016 22:31:18 +0000 (22:31 +0000)]
add tests to show missing bitcasted logic transform
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261799
91177308-0d34-0410-b5e6-
96231b3b80d8
Amaury Sechet [Wed, 24 Feb 2016 22:25:18 +0000 (22:25 +0000)]
Add capability to push/pop DFI in MCStreamer. NFC
Summary: This is extracted from D17555
Reviewers: davidxl, reames, sanjoy, MatzeB, pete
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261796
91177308-0d34-0410-b5e6-
96231b3b80d8
Anna Zaks [Wed, 24 Feb 2016 22:12:18 +0000 (22:12 +0000)]
[asan] Do not instrument globals in the special "LLVM" sections
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261794
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 24 Feb 2016 19:21:48 +0000 (19:21 +0000)]
MachineInstr: Respect register aliases in clearRegiserKills()
This fixes bugs in copy elimination code in llvm. It slightly changes the
semantics of clearRegisterKills(). This is appropriate because:
- Users in lib/CodeGen/MachineCopyPropagation.cpp and
lib/Target/AArch64RedundantCopyElimination.cpp and
lib/Target/SystemZ/SystemZElimCompare.cpp are incorrect without it
(see included testcase).
- All other users in llvm are unaffected (they pass TRI==nullptr)
- (Kill flags are optional anyway so removing too many shouldn't hurt.)
Differential Revision: http://reviews.llvm.org/D17554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261763
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Wed, 24 Feb 2016 18:10:17 +0000 (18:10 +0000)]
AArch64: remove CRC feature from Cyclone.
Turns out we don't actually support those instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261759
91177308-0d34-0410-b5e6-
96231b3b80d8
Teresa Johnson [Wed, 24 Feb 2016 17:57:28 +0000 (17:57 +0000)]
[ThinLTO] Add missing breaks when parsing summaries (NFC)
This wasn't causing a correctness issue, but was causing extra duplicate
entries to be added to the SummaryMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261757
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Wed, 24 Feb 2016 17:30:48 +0000 (17:30 +0000)]
[SimplifyCFG] Use a more elegant solution than r261731
The cleanupret instruction has an invariant that it's 'from' operand be
a cleanuppad. This invariant was violated when we removed a dead block
which removed a cleanuppad leaving behind a cleanupret with an undef
'from' operand.
This was solved in r261731 by staving off the removal of the dead block
to a later pass.
However, it occured to me that we do not need to do this.
Instead, we can simply avoid processing the cleanupret if it has an
undef 'from' operand because we know that it will be removed soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261754
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Feb 2016 17:08:59 +0000 (17:08 +0000)]
[X86][SSSE3] Added target shuffle combine tests for SSE3/SSSE3 specific shuffles.
Allows us to test SSSE3 PSHUFB intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261753
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Feb 2016 17:08:29 +0000 (17:08 +0000)]
remove fixme comment that was fixed with r261750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261752
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Feb 2016 17:00:34 +0000 (17:00 +0000)]
[InstCombine] enable optimization of casted vector xor instructions
This is part of the payoff for the refactoring in:
http://reviews.llvm.org/rL261649
http://reviews.llvm.org/rL261707
In addition to removing a pile of duplicated code, the xor case was
missing the optimization for vector types because it checked
"SrcTy->isIntegerTy()" rather than "SrcTy->isIntOrIntVectorTy()"
like 'and' and 'or' were already doing.
This solves part of:
https://llvm.org/bugs/show_bug.cgi?id=26702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261750
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 24 Feb 2016 16:34:29 +0000 (16:34 +0000)]
add test to show missing bitcasted vector xor fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261748
91177308-0d34-0410-b5e6-
96231b3b80d8
Anton Korobeynikov [Wed, 24 Feb 2016 15:15:02 +0000 (15:15 +0000)]
`MSP430InstrInfo::loadRegFromStackSlot` forgets to set register def.
Summary:
For instance, compiling the below results in a panic:
```
llc: ../lib/CodeGen/InlineSpiller.cpp:1140: bool (anonymous namespace)::InlineSpiller::foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned int> >, llvm::MachineInstr *): Assertion `MO->isDead() && "Cannot fold physreg def"' failed.
#0 0x00007f50fbcf353e llvm::sys::PrintStackTrace(llvm::raw_ostream&) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:321:15
#1 0x00007f50fbcf3929 PrintStackTraceSignalHandler(void*) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:380:1
#2 0x00007f50fbcf22a3 llvm::sys::RunSignalHandlers() /home/h/3rd/llvm/build/../lib/Support/Signals.cpp:45:5
#3 0x00007f50fbcf3bb4 SignalHandler(int) /home/h/3rd/llvm/build/../lib/Support/Unix/Signals.inc:210:1
#4 0x00007f50fa87a180 (/lib/x86_64-linux-gnu/libc.so.6+0x35180)
#5 0x00007f50fa87a107 gsignal (/lib/x86_64-linux-gnu/libc.so.6+0x35107)
#6 0x00007f50fa87b4e8 abort (/lib/x86_64-linux-gnu/libc.so.6+0x364e8)
#7 0x00007f50fa873226 (/lib/x86_64-linux-gnu/libc.so.6+0x2e226)
#8 0x00007f50fa8732d2 (/lib/x86_64-linux-gnu/libc.so.6+0x2e2d2)
#9 0x00007f50fddd9287 (anonymous namespace)::InlineSpiller::foldMemoryOperand(llvm::ArrayRef<std::pair<llvm::MachineInstr*, unsigned int> >, llvm::MachineInstr*) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1141:21
#10 0x00007f50fddd9ee9 (anonymous namespace)::InlineSpiller::spillAroundUses(unsigned int) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1286:9
#11 0x00007f50fddd388b (anonymous namespace)::InlineSpiller::spillAll() /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1338:21
#12 0x00007f50fddd221d (anonymous namespace)::InlineSpiller::spill(llvm::LiveRangeEdit&) /home/h/3rd/llvm/build/../lib/CodeGen/InlineSpiller.cpp:1391:3
#13 0x00007f50fdfd921b (anonymous namespace)::RAGreedy::selectOrSplitImpl(llvm::LiveInterval&, llvm::SmallVectorImpl<unsigned int>&, llvm::SmallSet<unsigned int, 16u, std::less<unsigned int> >&, unsigned int) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2555:5
#14 0x00007f50fdfd647b (anonymous namespace)::RAGreedy::selectOrSplit(llvm::LiveInterval&, llvm::SmallVectorImpl<unsigned int>&) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2221:12
#15 0x00007f50fdfc89f9 llvm::RegAllocBase::allocatePhysRegs() /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocBase.cpp:110:14
#16 0x00007f50fdfd6337 (anonymous namespace)::RAGreedy::runOnMachineFunction(llvm::MachineFunction&) /home/h/3rd/llvm/build/../lib/CodeGen/RegAllocGreedy.cpp:2611:3
#17 0x00007f50fded33ee llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /home/h/3rd/llvm/build/../lib/CodeGen/MachineFunctionPass.cpp:43:3
#18 0x00007f50fd6cdc6f llvm::FPPassManager::runOnFunction(llvm::Function&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1550:23
#19 0x00007f50fd6cdf85 llvm::FPPassManager::runOnModule(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1571:16
#20 0x00007f50fd6ce71a (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1627:23
#21 0x00007f50fd6ce246 llvm::legacy::PassManagerImpl::run(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1730:16
#22 0x00007f50fd6cec31 llvm::legacy::PassManager::run(llvm::Module&) /home/h/3rd/llvm/build/../lib/IR/LegacyPassManager.cpp:1761:3
#23 0x0000000000415bdc compileModule(char**, llvm::LLVMContext&) /home/h/3rd/llvm/build/../tools/llc/llc.cpp:405:5
#24 0x0000000000414571 main /home/h/3rd/llvm/build/../tools/llc/llc.cpp:211:13
#25 0x00007f50fa866b45 __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x21b45)
#26 0x0000000000414296 _start (/home/h/3rd/llvm/build/bin/llc+0x414296)
Stack dump:
0. Program arguments: ./bin/llc -mtriple msp430 loadstore.ll
1. Running pass 'Function Pass Manager' on module 'loadstore.ll'.
2. Running pass 'Greedy Register Allocator' on function '@inc'
```
Original IR:
```llvm
%struct.VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
; Function Attrs: norecurse nounwind
define void @inc(%struct.VeryLarge* noalias nocapture sret %agg.result, %struct.VeryLarge* byval align 1 %s) #0 {
entry:
%p0 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 0
%0 = load i8, i8* %p0, align 1, !tbaa !1
%p1 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 1
%1 = load i32, i32* %p1, align 1, !tbaa !6
%p2 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 2
%2 = load i32, i32* %p2, align 1, !tbaa !7
%p3 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 3
%3 = load i32, i32* %p3, align 1, !tbaa !8
%p4 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 4
%4 = load i32, i32* %p4, align 1, !tbaa !9
%p5 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 5
%5 = load i32, i32* %p5, align 1, !tbaa !10
%p6 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 6
%6 = load i32, i32* %p6, align 1, !tbaa !11
%p7 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 7
%7 = load i32, i32* %p7, align 1, !tbaa !12
%p8 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 8
%8 = load i32, i32* %p8, align 1, !tbaa !13
%p9 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 9
%9 = load i32, i32* %p9, align 1, !tbaa !14
%p10 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 10
%10 = load i32, i32* %p10, align 1, !tbaa !15
%p11 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 11
%11 = load i32, i32* %p11, align 1, !tbaa !16
%p12 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 12
%12 = load i32, i32* %p12, align 1, !tbaa !17
%p13 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 13
%13 = load i32, i32* %p13, align 1, !tbaa !18
%p14 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 14
%14 = load i32, i32* %p14, align 1, !tbaa !19
%p15 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 15
%15 = load i32, i32* %p15, align 1, !tbaa !20
%p16 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 16
%16 = load i32, i32* %p16, align 1, !tbaa !21
%p17 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 17
%17 = load i32, i32* %p17, align 1, !tbaa !22
%p18 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 18
%18 = load i32, i32* %p18, align 1, !tbaa !23
%p19 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 19
%19 = load i32, i32* %p19, align 1, !tbaa !24
%p20 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 20
%20 = load i32, i32* %p20, align 1, !tbaa !25
%p21 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 21
%21 = load i32, i32* %p21, align 1, !tbaa !26
%p22 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 22
%22 = load i32, i32* %p22, align 1, !tbaa !27
%p23 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 23
%23 = load i32, i32* %p23, align 1, !tbaa !28
%p24 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 24
%24 = load i32, i32* %p24, align 1, !tbaa !29
%p25 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 25
%25 = load i32, i32* %p25, align 1, !tbaa !30
%p26 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 26
%26 = load i32, i32* %p26, align 1, !tbaa !31
%p27 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 27
%27 = load i32, i32* %p27, align 1, !tbaa !32
%p28 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 28
%28 = load i32, i32* %p28, align 1, !tbaa !33
%p29 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 29
%29 = load i32, i32* %p29, align 1, !tbaa !34
%p30 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 30
%30 = load i32, i32* %p30, align 1, !tbaa !35
%p31 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 31
%31 = load i32, i32* %p31, align 1, !tbaa !36
%p32 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %s, i32 0, i32 32
%32 = load i32, i32* %p32, align 1, !tbaa !37
%add = add i8 %0, 1
store i8 %add, i8* %p0, align 1, !tbaa !1
%add2 = add i32 %1, 2
store i32 %add2, i32* %p1, align 1, !tbaa !6
%add3 = add i32 %2, 3
store i32 %add3, i32* %p2, align 1, !tbaa !7
%add4 = add i32 %3, 4
store i32 %add4, i32* %p3, align 1, !tbaa !8
%add5 = add i32 %4, 5
store i32 %add5, i32* %p4, align 1, !tbaa !9
%add6 = add i32 %5, 6
store i32 %add6, i32* %p5, align 1, !tbaa !10
%add7 = add i32 %6, 7
store i32 %add7, i32* %p6, align 1, !tbaa !11
%add8 = add i32 %7, 8
store i32 %add8, i32* %p7, align 1, !tbaa !12
%add9 = add i32 %8, 9
store i32 %add9, i32* %p8, align 1, !tbaa !13
%add10 = add i32 %9, 10
store i32 %add10, i32* %p9, align 1, !tbaa !14
%add11 = add i32 %10, 11
store i32 %add11, i32* %p10, align 1, !tbaa !15
%add12 = add i32 %11, 12
store i32 %add12, i32* %p11, align 1, !tbaa !16
%add13 = add i32 %12, 13
store i32 %add13, i32* %p12, align 1, !tbaa !17
%add14 = add i32 %13, 14
store i32 %add14, i32* %p13, align 1, !tbaa !18
%add15 = add i32 %14, 15
store i32 %add15, i32* %p14, align 1, !tbaa !19
%add16 = add i32 %15, 16
store i32 %add16, i32* %p15, align 1, !tbaa !20
%add17 = add i32 %16, 17
store i32 %add17, i32* %p16, align 1, !tbaa !21
%add18 = add i32 %17, 18
store i32 %add18, i32* %p17, align 1, !tbaa !22
%add19 = add i32 %18, 19
store i32 %add19, i32* %p18, align 1, !tbaa !23
%add20 = add i32 %19, 20
store i32 %add20, i32* %p19, align 1, !tbaa !24
%add21 = add i32 %20, 21
store i32 %add21, i32* %p20, align 1, !tbaa !25
%add22 = add i32 %21, 22
store i32 %add22, i32* %p21, align 1, !tbaa !26
%add23 = add i32 %22, 23
store i32 %add23, i32* %p22, align 1, !tbaa !27
%add24 = add i32 %23, 24
store i32 %add24, i32* %p23, align 1, !tbaa !28
%add25 = add i32 %24, 25
store i32 %add25, i32* %p24, align 1, !tbaa !29
%add26 = add i32 %25, 26
store i32 %add26, i32* %p25, align 1, !tbaa !30
%add27 = add i32 %26, 27
store i32 %add27, i32* %p26, align 1, !tbaa !31
%add28 = add i32 %27, 28
store i32 %add28, i32* %p27, align 1, !tbaa !32
%add29 = add i32 %28, 29
store i32 %add29, i32* %p28, align 1, !tbaa !33
%add30 = add i32 %29, 30
store i32 %add30, i32* %p29, align 1, !tbaa !34
%add31 = add i32 %30, 31
store i32 %add31, i32* %p30, align 1, !tbaa !35
%add32 = add i32 %31, 32
store i32 %add32, i32* %p31, align 1, !tbaa !36
%add33 = add i32 %32, 33
store i32 %add33, i32* %p32, align 1, !tbaa !37
%33 = getelementptr inbounds %struct.VeryLarge, %struct.VeryLarge* %agg.result, i32 0, i32 0
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %p0, i32 129, i32 1, i1 false), !tbaa.struct !38
ret void
}
; Function Attrs: argmemonly nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1
attributes #0 = { norecurse nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nounwind }
!llvm.ident = !{!0}
!0 = !{!"clang version 3.8.0 (git://github.com/llvm-mirror/clang
40ef2b7531472c41212c4719a9294aeb7bddebbc) (git://github.com/llvm-mirror/llvm
c601eaf55606dfb9ad372b514b77aa00d1409be1)"}
!1 = !{!2, !3, i64 0}
!2 = !{!"", !3, i64 0, !5, i64 1, !5, i64 5, !5, i64 9, !5, i64 13, !5, i64 17, !5, i64 21, !5, i64 25, !5, i64 29, !5, i64 33, !5, i64 37, !5, i64 41, !5, i64 45, !5, i64 49, !5, i64 53, !5, i64 57, !5, i64 61, !5, i64 65, !5, i64 69, !5, i64 73, !5, i64 77, !5, i64 81, !5, i64 85, !5, i64 89, !5, i64 93, !5, i64 97, !5, i64 101, !5, i64 105, !5, i64 109, !5, i64 113, !5, i64 117, !5, i64 121, !5, i64 125}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}
!5 = !{!"int", !3, i64 0}
!6 = !{!2, !5, i64 1}
!7 = !{!2, !5, i64 5}
!8 = !{!2, !5, i64 9}
!9 = !{!2, !5, i64 13}
!10 = !{!2, !5, i64 17}
!11 = !{!2, !5, i64 21}
!12 = !{!2, !5, i64 25}
!13 = !{!2, !5, i64 29}
!14 = !{!2, !5, i64 33}
!15 = !{!2, !5, i64 37}
!16 = !{!2, !5, i64 41}
!17 = !{!2, !5, i64 45}
!18 = !{!2, !5, i64 49}
!19 = !{!2, !5, i64 53}
!20 = !{!2, !5, i64 57}
!21 = !{!2, !5, i64 61}
!22 = !{!2, !5, i64 65}
!23 = !{!2, !5, i64 69}
!24 = !{!2, !5, i64 73}
!25 = !{!2, !5, i64 77}
!26 = !{!2, !5, i64 81}
!27 = !{!2, !5, i64 85}
!28 = !{!2, !5, i64 89}
!29 = !{!2, !5, i64 93}
!30 = !{!2, !5, i64 97}
!31 = !{!2, !5, i64 101}
!32 = !{!2, !5, i64 105}
!33 = !{!2, !5, i64 109}
!34 = !{!2, !5, i64 113}
!35 = !{!2, !5, i64 117}
!36 = !{!2, !5, i64 121}
!37 = !{!2, !5, i64 125}
!38 = !{i64 0, i64 1, !39, i64 1, i64 4, !40, i64 5, i64 4, !40, i64 9, i64 4, !40, i64 13, i64 4, !40, i64 17, i64 4, !40, i64 21, i64 4, !40, i64 25, i64 4, !40, i64 29, i64 4, !40, i64 33, i64 4, !40, i64 37, i64 4, !40, i64 41, i64 4, !40, i64 45, i64 4, !40, i64 49, i64 4, !40, i64 53, i64 4, !40, i64 57, i64 4, !40, i64 61, i64 4, !40, i64 65, i64 4, !40, i64 69, i64 4, !40, i64 73, i64 4, !40, i64 77, i64 4, !40, i64 81, i64 4, !40, i64 85, i64 4, !40, i64 89, i64 4, !40, i64 93, i64 4, !40, i64 97, i64 4, !40, i64 101, i64 4, !40, i64 105, i64 4, !40, i64 109, i64 4, !40, i64 113, i64 4, !40, i64 117, i64 4, !40, i64 121, i64 4, !40, i64 125, i64 4, !40}
!39 = !{!3, !3, i64 0}
!40 = !{!5, !5, i64 0}
```
Reviewers: asl
Subscribers: qcolombet
Differential Revision: http://reviews.llvm.org/D17441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261746
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Feb 2016 15:14:21 +0000 (15:14 +0000)]
[X86][SSE41] Combine vector blends with zero
Part 2 of 2
This patch add support for combining target shuffles into blends-with-zero.
Differential Revision: http://reviews.llvm.org/D17483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261745
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Feb 2016 14:53:27 +0000 (14:53 +0000)]
[X86][SSE41] Combine insertion of zero scalars into vector blends with zero
Part 1 of 2
This patch attempts to replace the insertion of zero scalars with a vector blend with zero, avoiding the use of the integer insertion instructions (which are particularly slow on many targets).
(Part 2 will add support for combining multiple blends-with-zero).
Differential Revision: http://reviews.llvm.org/D17483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261743
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolay Haustov [Wed, 24 Feb 2016 14:22:47 +0000 (14:22 +0000)]
[AMDGPU] Assembler: Simplify handling of optional operands
Prepare to support DPP encodings.
For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands. However this means that when parsing instruction which has no mnemonic prefix, we cannot add both default values for VOP3 and for DPP optional operands to OperandVector - neither instructions would match. So add default values for optional operands to MCInst during conversion instead.
Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.
Review: http://reviews.llvm.org/D17445
Reviewers: tstellarAMD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261742
91177308-0d34-0410-b5e6-
96231b3b80d8
Artur Pilipenko [Wed, 24 Feb 2016 12:49:04 +0000 (12:49 +0000)]
NFC. Move isDereferenceable to Loads.h/cpp
This is a part of the refactoring to unify isSafeToLoadUnconditionally and isDereferenceablePointer functions. In subsequent change I'm going to eliminate isDerferenceableAndAlignedPointer from Loads API, leaving isSafeToLoadSpecualtively the only function to check is load instruction can be speculated.
Reviewed By: hfinkel
Differential Revision: http://reviews.llvm.org/D16180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261736
91177308-0d34-0410-b5e6-
96231b3b80d8
Artur Pilipenko [Wed, 24 Feb 2016 12:25:10 +0000 (12:25 +0000)]
NFC. Move getAlignment helper function from ValueTracking to Value class.
Reviewed By: reames, hfinkel
Differential Revision: http://reviews.llvm.org/D16144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261735
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Feb 2016 11:39:13 +0000 (11:39 +0000)]
[X86][SSE] Fixed vector rotation test name typo
Rotation of 16i6 vector not 8i16 vector - copy+paste is not your friend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261733
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolay Haustov [Wed, 24 Feb 2016 10:54:25 +0000 (10:54 +0000)]
[AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields)
lit tests passed before and after because it doesn't test the binary representation of amd_kernel_code_t.
Patch by: Valery Pykhtin (Valery.Pykhtin@amd.com)
Reviewers: arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261732
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Wed, 24 Feb 2016 10:02:16 +0000 (10:02 +0000)]
[SimplifyCFG] Do not blindly remove unreachable blocks
DeleteDeadBlock was called indiscriminately, leading to cleanuprets with
undef cleanuppad references.
Instead, try to drain the BB of most of it's instructions if it is
unreachable. We can then remove the BB if it solely consists of a
terminator (and maybe some phis).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261731
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Wed, 24 Feb 2016 10:01:24 +0000 (10:01 +0000)]
[CodeView] Describe variables live in x87 registers
We didn't have a mapping from LLVM's x87 floating point registers to
CodeView's encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261730
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 24 Feb 2016 09:07:47 +0000 (09:07 +0000)]
[X86][SSE] Don't get target shuffle operands prematurely.
PerformShuffleCombine should be usable by unary and binary target shuffles, but was attempting to get the first two operands whatever the instruction type. Since these are only used for VECTOR_SHUFFLE instructions for one particular combine I've moved them inside the relevant if statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261727
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Zuckerman [Wed, 24 Feb 2016 08:39:05 +0000 (08:39 +0000)]
[LLVM][AVX512][PSHUFHW ][PSHUFLW ] Change imm8 to int
Differential Revision: http://reviews.llvm.org/D17538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261725
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Breger [Wed, 24 Feb 2016 08:15:20 +0000 (08:15 +0000)]
AVX512: Add vpmovzxbw/d/q ,vpmovzxw/d/q ,vpmovzxbdq lowering patterns that support 256bit inputs like AVX patterns ( that are disable in case HasVLX , see SS41I_pmovx_avx2_patterns).
Differential Revision: http://reviews.llvm.org/D17504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261724
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Wed, 24 Feb 2016 07:58:02 +0000 (07:58 +0000)]
X86: Wrap a helper for an assert in #ifndef NDEBUG
This function is used in exactly one place, and only in asserts
builds. Move it a few lines up before the use and only define it when
asserts are enabled. Fixes the release build under -Werror.
Also remove the forward declaration and commentary that was basically
identical to the code itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261722
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 24 Feb 2016 04:55:29 +0000 (04:55 +0000)]
AMDGPU: Check cheaper condition before SignBitIsZero
Don't do an expensive computeKnownBits call when we
can do the cheap check for legal offsets first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261720
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 23 Feb 2016 23:56:23 +0000 (23:56 +0000)]
[InstCombine] refactor visitOr() to use foldCastedBitwiseLogic()
Note: The 'and' case in foldCastedBitwiseLogic() is inheriting one extra
check from the nearly identical 'or' case:
if ((!isa<ICmpInst>(Cast0Src) || !isa<ICmpInst>(Cast1Src))
But I'm not sure how to expose that difference in a regression test.
Without that check, the 'or' path will infinite loop on:
test/Transforms/InstCombine/zext-or-icmp.ll
because the zext-or-icmp fold is attempting a reverse transform.
The refactoring should extend to the 'xor' case next to solve part of
PR26702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261707
91177308-0d34-0410-b5e6-
96231b3b80d8
Jingyue Wu [Tue, 23 Feb 2016 23:34:49 +0000 (23:34 +0000)]
[doc] Obtaining help on LLVM's CUDA support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261706
91177308-0d34-0410-b5e6-
96231b3b80d8
Derek Schuff [Tue, 23 Feb 2016 22:13:21 +0000 (22:13 +0000)]
Revert "[WebAssembly] Stackify code emitted by eliminateFrameIndex"
This reverts r261685 due to wasm test breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261702
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 23 Feb 2016 22:03:44 +0000 (22:03 +0000)]
minimize test and use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261701
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Tue, 23 Feb 2016 21:49:05 +0000 (21:49 +0000)]
AArch64: rename compact unwind forms back to UNWIND_ARM64_*. NFC.
Looks like the global rename last year was a bit over-zealous. These things
really are referred to with ARM64 elsewhere (ld64, libunwind, ...).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261698
91177308-0d34-0410-b5e6-
96231b3b80d8
Derek Schuff [Tue, 23 Feb 2016 21:25:17 +0000 (21:25 +0000)]
[WebAssembly] Stackify code emitted by eliminateFrameIndex
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261685
91177308-0d34-0410-b5e6-
96231b3b80d8
Chris Bieneman [Tue, 23 Feb 2016 20:33:53 +0000 (20:33 +0000)]
[CMake] Create an install-distribution target driven by LLVM_DISTRIBUTION_COMPONENTS
The idea here is to provide a customizable install target that only depends on building the things you actually want to install. It relies on each component being installed having an auto-generated install-${component}, which in turn depends only on the target being installed.
This is fundamentally a workaround for the fact that CMake generates build files which have their "install" target depend on the "all" target. This results in "ninja install" building a bunch of unneeded things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261681
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Tue, 23 Feb 2016 20:20:23 +0000 (20:20 +0000)]
ARM: fix handling of movw/movt relocations with addend.
We were emitting only one half of a the paired relocations needed for these
instructions because we decided that an offset needed a scattered relocation.
In fact, movw/movt relocations can be paired without being scattered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261679
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Tue, 23 Feb 2016 19:34:13 +0000 (19:34 +0000)]
[AArch64] Generate csinv instruction more often
Reviewers: t.p.northover, jmolloy
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D17546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261675
91177308-0d34-0410-b5e6-
96231b3b80d8
Xinliang David Li [Tue, 23 Feb 2016 19:18:21 +0000 (19:18 +0000)]
Fix comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261672
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Tue, 23 Feb 2016 19:17:03 +0000 (19:17 +0000)]
Revert r261633 "Supporting all entities declared in lexical scope in LLVM debug info."
This and the corresponding Clang change caused PR26715.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261671
91177308-0d34-0410-b5e6-
96231b3b80d8
Davide Italiano [Tue, 23 Feb 2016 18:39:38 +0000 (18:39 +0000)]
[X86ISelLowering] Stop typing the same return over and over and over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261666
91177308-0d34-0410-b5e6-
96231b3b80d8
Weiming Zhao [Tue, 23 Feb 2016 18:39:19 +0000 (18:39 +0000)]
Fix PR25339: ARM Constant Island
Summary:
Currently, the ARM Constant Island may not converge (or not converge quickly).
This patch let it move to the closest water after the user if it doesn't converge after 15 iterations.
This address https://llvm.org/bugs/show_bug.cgi?id=25339
Reviewers: t.p.northover, srhines, kristof.beyls, aadg, rengolin
Subscribers: weimingz, aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D16890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261665
91177308-0d34-0410-b5e6-
96231b3b80d8
Derek Schuff [Tue, 23 Feb 2016 18:17:46 +0000 (18:17 +0000)]
[WebAssembly] Add TODO comment to revisit red zone size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261664
91177308-0d34-0410-b5e6-
96231b3b80d8
Derek Schuff [Tue, 23 Feb 2016 18:13:07 +0000 (18:13 +0000)]
[WebAssembly] Implement red zone for user stack
Implements a mostly-conventional redzone for the userspace
stack. Because we have unsigned load/store offsets we continue to use a
local SP subtracted from the incoming SP but do not write it back to
memory.
Differential Revision: http://reviews.llvm.org/D17525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261662
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 23 Feb 2016 17:41:34 +0000 (17:41 +0000)]
[InstCombine] improve readability ; NFCI
Less indenting, named local variables, more descriptive names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261659
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Tue, 23 Feb 2016 17:11:04 +0000 (17:11 +0000)]
[WinEH] Don't inline an 'unwinds to caller' cleanupret into funclets which locally unwind
It is problematic if the inlinee has a cleanupret which unwinds to
caller and we inline it into a call site which doesn't unwind.
If the funclet unwinds anywhere other than to the caller,
then we will give the funclet two unwind destinations.
This will result in a verifier failure.
Seeing as how the caller wasn't an invoke (which would locally unwind)
and that the funclet cannot unwind to caller, we must conclude that an
'unwind to caller' cleanupret is dynamically unreachable.
This fixes PR26698.
Differential Revision: http://reviews.llvm.org/D17536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261656
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 23 Feb 2016 16:59:21 +0000 (16:59 +0000)]
[InstCombine] less indenting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261652
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Tue, 23 Feb 2016 16:54:36 +0000 (16:54 +0000)]
[AArch64] Fix fastcc -tailcallopt epilog code generation.
Summary:
Fix a bug in epilog generation where the incoming stack arguments were
not being popped for fastcc functions when -tailcallopt was passed.
Reviewers: t.p.northover, mcrosier, jmolloy, rengolin
Subscribers: aemerson, rengolin, mcrosier, llvm-commits
Differential Revision: http://reviews.llvm.org/D16894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261650
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 23 Feb 2016 16:36:07 +0000 (16:36 +0000)]
[InstCombine] add helper function to foldCastedBitwiseLogic() ; NFCI
This is a straight cut and paste of the existing code and is intended to
be the first step in solving part of PR26702:
https://llvm.org/bugs/show_bug.cgi?id=26702
We should be able to reuse most of this and delete the nearly identical
existing code in visitOr(). Then, we can enhance visitXor() to use the
same code too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261649
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Tue, 23 Feb 2016 15:02:43 +0000 (15:02 +0000)]
Silencing a signed vs unsigned mismatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261640
91177308-0d34-0410-b5e6-
96231b3b80d8
Chad Rosier [Tue, 23 Feb 2016 14:05:13 +0000 (14:05 +0000)]
[AArch64] Fix comment typo in Cyclone scheduling defs. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261637
91177308-0d34-0410-b5e6-
96231b3b80d8
Amjad Aboud [Tue, 23 Feb 2016 13:36:51 +0000 (13:36 +0000)]
Supporting all entities declared in lexical scope in LLVM debug info.
Differential Revision: http://reviews.llvm.org/D15976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261633
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Kornienko [Tue, 23 Feb 2016 11:19:56 +0000 (11:19 +0000)]
Remove a space after a trailing backslash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261629
91177308-0d34-0410-b5e6-
96231b3b80d8
Sylvestre Ledru [Tue, 23 Feb 2016 11:17:27 +0000 (11:17 +0000)]
fix the indentation of the example
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261628
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 23 Feb 2016 10:47:57 +0000 (10:47 +0000)]
[PM] Remove an overly aggressive assert now that I can actually test the
pattern that triggers it. This essentially requires an immutable
function analysis, as that will survive anything we do to invalidate it.
When we have such patterns, the function analysis manager will not get
cleared between runs of the proxy.
If we actually need an assert about how things are queried, we can add
more elaborate machinery for computing it, but so far I'm not aware of
significant value provided.
Thanks to Justin Lebar for noticing this when he made a (seemingly
innocuous) change to FunctionAttrs that is enough to trigger it in one
test there. Now it is covered by a direct test of the pass manager code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261627
91177308-0d34-0410-b5e6-
96231b3b80d8
Chandler Carruth [Tue, 23 Feb 2016 10:02:02 +0000 (10:02 +0000)]
[PM] Add a unittest for the CGSCC pass manager in the new pass manager
system.
Previously, this was only being tested with larger integration tests.
That makes it hard to isolated specific issues with it, and makes the
APIs themselves less well tested. Add a unittest based around the same
patterns used for testing the general pass manager.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261624
91177308-0d34-0410-b5e6-
96231b3b80d8
Junmo Park [Tue, 23 Feb 2016 09:56:58 +0000 (09:56 +0000)]
[ARM] fix initialization of PredictableSelectIsExpensive
Summary:
If we want classify OoO or not, using getSchedModel().isOutOfOrder()
could be more proper way than using Subtarget->isLikeA9().
Reviewers: jmolloy, rengolin
Differential Revision: http://reviews.llvm.org/D17433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261623
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolay Haustov [Tue, 23 Feb 2016 09:19:14 +0000 (09:19 +0000)]
[AMDGPU] Fix operands of S_BFE_U64 and S_BFM_B64
src1 of s_bfe_u64 is 32-bit (same as s_bfe_i64).
src0 and src1 of s_bfm_b64 are 32-bit.
Update tests.
Review: http://reviews.llvm.org/D17480
Reviewers: arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261621
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Breger [Tue, 23 Feb 2016 08:55:33 +0000 (08:55 +0000)]
AVX512: Fix predicate of AVX pcmpeqw/b , pcmpgtb/w/d instructions . AVX512 version of this instructions return result in kmask register, so AVX patterns should not be disabled.
Differential Revision: http://reviews.llvm.org/D17517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261619
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Tue, 23 Feb 2016 07:18:15 +0000 (07:18 +0000)]
[WinEH] Visit 'unwind to caller' catchswitches nested in catchswitches
We had the right logic for the nested cleanuppad case but omitted it for
catchswitches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261615
91177308-0d34-0410-b5e6-
96231b3b80d8
Yaron Keren [Tue, 23 Feb 2016 07:17:58 +0000 (07:17 +0000)]
Assert when trying to seek un-seekable raw_fd_ostream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261614
91177308-0d34-0410-b5e6-
96231b3b80d8
Dehao Chen [Tue, 23 Feb 2016 03:39:24 +0000 (03:39 +0000)]
Add prefix based function layout when profile is available.
Summary: If a function is hot, put it in text.hot section.
Reviewers: davidxl
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261607
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Tue, 23 Feb 2016 02:46:52 +0000 (02:46 +0000)]
CodeGen: TII: Take MachineInstr& in predicate API, NFC
Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to come back later and get some of the rest). All of these
functions require non-null parameters already, so references are more
clear. As a bonus, this happens to factor away a host of implicit
iterator => pointer conversions.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261605
91177308-0d34-0410-b5e6-
96231b3b80d8