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Alexey Bataev [Mon, 7 Aug 2017 14:51:52 +0000 (14:51 +0000)]
Revert "[SLP] General improvements of SLP vectorization process."
This reverts commit r310255.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310257
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Nirav Dave [Mon, 7 Aug 2017 14:07:49 +0000 (14:07 +0000)]
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.
Relanding after case to insert explicit truncation as necessary.
Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.
Reviewers: efriedma, RKSimon, spatel
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310256
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Alexey Bataev [Mon, 7 Aug 2017 14:03:17 +0000 (14:03 +0000)]
[SLP] General improvements of SLP vectorization process.
Summary:
Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:
1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the array. This array is processed only after the vectorization of the first-after-these instructions key node is finished. Vectorization goes in reverse order to try to vectorize as much code as possible.
Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon
Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits
Differential Revision: https://reviews.llvm.org/D29826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310255
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Nirav Dave [Mon, 7 Aug 2017 13:55:27 +0000 (13:55 +0000)]
[TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true
Relanding after fixing UB issue with DefaultOffsets.
Consider the following instruction: "inst.eq $dst, $src" where ".eq"
is an optional flag operand. The $src and $dst operands are
registers. If we parse the instruction "inst r0, r1", the flag is not
present and it will be marked in the "OptionalOperandsMask" variable.
After the matching is complete we call the "convertToMCInst" method.
The current implementation works only if the optional operands are at
the end of the array. The "Operands" array looks like [token:"inst",
reg:r0, reg:r1]. The first operand that must be added to the MCInst
is the destination, the r0 register. The "OpIdx" (in the Operands
array) for this register is 2. However, since the flag is not present
in the Operands, the actual index for r0 should be 1. The flag is not
present since we rely on the default value.
This patch removes the "NumDefaults" variable and replaces it with an
array (DefaultsOffset). This array contains an index for each operand
(excluding the mnemonic). At each index, the array contains the
number of optional operands that should be subtracted. For the
previous example, this array looks like this: [0, 1, 1]. When we need
to access the r0 register, we compute its index as 2 -
DefaultsOffset[1] = 1.
Patch by Alexandru Guduleasa!
Reviewers: SamWot, nhaustov, niravd
Reviewed By: niravd
Subscribers: vitalybuka, llvm-commits
Differential Revision: https://reviews.llvm.org/D35998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310254
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Simon Dardis [Mon, 7 Aug 2017 13:30:03 +0000 (13:30 +0000)]
[DebugInfo][DWARF] Use PRIx64 explicitly in output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310253
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Michael Zuckerman [Mon, 7 Aug 2017 13:22:39 +0000 (13:22 +0000)]
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF16 stride 4).
This patch expands the support of lowerInterleavedStore to 16x8i stride 4.
LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=16) and we plan to include more patterns in the future.
The patch goal is to optimize the following sequence:
At the end of the computation, we have ymm2, ymm0, ymm12 and ymm3 holding
each 16 chars:
c0, c1, , c16
m0, m1, , m16
y0, y1, , y16
k0, k1, ., k16
And these need to be transposed/interleaved and stored like so:
c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....
Differential Revision: https://reviews.llvm.org/D35829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310252
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Dmitry Preobrazhensky [Mon, 7 Aug 2017 13:14:12 +0000 (13:14 +0000)]
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310251
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Simon Dardis [Mon, 7 Aug 2017 12:29:38 +0000 (12:29 +0000)]
[llvm-objdump] Use PRIx64 for output of ARM64_RELOC_ADDEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310250
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Simon Pilgrim [Mon, 7 Aug 2017 12:24:33 +0000 (12:24 +0000)]
[X86][AVX] Added test for broadcast shuffle with undefs (PR34041)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310249
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Andre Vieira [Mon, 7 Aug 2017 08:41:05 +0000 (08:41 +0000)]
[ARM] Fix assembly and disassembly for VMRS/VMSR
This patch addresses two issues with assembly and disassembly for VMRS/VMSR:
1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
accepted for non ARMv8-A targets.
2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only
ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.
This patch addresses those issues and adds tests for these cases.
Differential Revision: https://reviews.llvm.org/D36306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310243
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Vitaly Buka [Mon, 7 Aug 2017 07:35:33 +0000 (07:35 +0000)]
[asan] Fix asan dynamic shadow check before copyArgsPassedByValToAllocas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310242
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Vitaly Buka [Mon, 7 Aug 2017 07:12:34 +0000 (07:12 +0000)]
[asan] Disable checking of arguments passed by value for --asan-force-dynamic-shadow
Fails with "Instruction does not dominate all uses!"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310241
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Vitaly Buka [Mon, 7 Aug 2017 07:12:33 +0000 (07:12 +0000)]
Add -asan-force-dynamic-shadow test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310240
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Guy Blank [Mon, 7 Aug 2017 05:51:14 +0000 (05:51 +0000)]
[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks
The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types.
But before calling CodeGenAndEmitDAG we build the DAG for the basic block.
So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'.
This patch sets the flag to false before SDAG building each basic block.
Differential Revision:
https://reviews.llvm.org/D33435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310239
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Davide Italiano [Mon, 7 Aug 2017 01:57:21 +0000 (01:57 +0000)]
[Reassociate] Use a range loop for clarity. NFCI.
While here, rename `i` to `Rank` as the latter is more
self-explanatory (and this code also uses `I` two lines below to
identify an Instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310238
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Davide Italiano [Mon, 7 Aug 2017 01:49:09 +0000 (01:49 +0000)]
[Reassociate] Try to bail out early when canonicalizing.
This commit rearranges the checks to avoid calls to getRank()
when not needed (e.g. when RHS == LHS).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310237
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Craig Topper [Sun, 6 Aug 2017 23:30:49 +0000 (23:30 +0000)]
[InstCombine] Remove shift handling from OptAndOp.
Summary: This is all handled by SimplifyDemandedBits.
Reviewers: spatel, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D36382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310234
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Craig Topper [Sun, 6 Aug 2017 23:11:49 +0000 (23:11 +0000)]
[InstCombine] Support (X ^ C1) & C2 --> (X & C2) ^ (C1&C2) for vector splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310233
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Craig Topper [Sun, 6 Aug 2017 22:17:21 +0000 (22:17 +0000)]
[InstCombine] Support '(C - X) ^ signmask -> (C + signmask - X)' and '(X + C) ^ signmask -> (X + C + signmask)' for vector splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310232
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Simon Pilgrim [Sun, 6 Aug 2017 20:50:19 +0000 (20:50 +0000)]
[SLPVectorizer][X86] Cleanup test case. NFCI
Remove excess attributes/metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310227
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Martin Storsjo [Sun, 6 Aug 2017 19:58:13 +0000 (19:58 +0000)]
[llvm-dlltool] Map the "arm64" machine type
Differential Revision: https://reviews.llvm.org/D36365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310223
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Matt Arsenault [Sun, 6 Aug 2017 18:13:23 +0000 (18:13 +0000)]
AMDGPU: Fix typo in feature description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310217
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Sanjay Patel [Sun, 6 Aug 2017 16:27:07 +0000 (16:27 +0000)]
[x86] use more shift or LEA for select-of-constants
We can convert any select-of-constants to math ops:
http://rise4fun.com/Alive/d7d
For this patch, I'm enhancing an existing x86 transform that uses fake multiplies
(they always become shl/lea) to avoid cmov or branching. The current code misses
cases where we have a negative constant and a positive constant, so this is just
trying to plug that hole.
The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start
with a select in IR, create a select DAG node, convert it into a sext, convert it
back into a select, and then lower it to sext machine code.
Some notes about the test diffs:
1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR.
2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. I
think we could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on
a different reg? That's a post-DAG problem though.
3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if
that's a regression, but I think those would always be nearly equivalent.
4. pr22338.ll and sext-i1.ll - These tests have undef operands, so I don't think we actually care about these diffs.
5. sbb.ll - This shows a win for what I think is a common case: choose -1 or 0.
6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again.
7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops.
Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass.
Differential Revision: https://reviews.llvm.org/D35340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310208
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Simon Pilgrim [Sun, 6 Aug 2017 13:21:09 +0000 (13:21 +0000)]
[X86] Add comment to match closing Defs = [FPSW]. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310202
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Simon Pilgrim [Sun, 6 Aug 2017 12:17:10 +0000 (12:17 +0000)]
[X86][X87] Regenerate inline-asm tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310201
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Meador Inge [Sun, 6 Aug 2017 12:02:17 +0000 (12:02 +0000)]
[AVR] Compute code model if one is not provided
The patch from r310028 fixed things to work with the new
`LLVMTargetMachine` constructor that came in on r309911.
However, the fix was partial since an object of type
`CodeModel::Model` must be passed to `LLVMTargetMachine`
(not one of `Optional<CodeModel::Model>`).
This patch fixes the problem in the same fashion that r309911
did for other machines: by checking if the passed optional
code model has a value and using `CodeModel::Small` if not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310200
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Simon Pilgrim [Sun, 6 Aug 2017 11:22:33 +0000 (11:22 +0000)]
[X86][X87] Add test case for PR34080
Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets.
pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310198
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Craig Topper [Sun, 6 Aug 2017 06:28:41 +0000 (06:28 +0000)]
[InstCombine] Support ~(c-X) --> X+(-c-1) and ~(X-c) --> (-c-1)-X for splat vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310195
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Craig Topper [Sat, 5 Aug 2017 23:34:44 +0000 (23:34 +0000)]
[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled
Summary:
On older processors this instruction encoding is treated as a NOP.
MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.
This change also seems to also be consistent with gcc behavior.
Fixes PR34079
Reviewers: RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310190
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Chandler Carruth [Sat, 5 Aug 2017 22:48:37 +0000 (22:48 +0000)]
[ADT] Add a much simpler loop to DenseMap::clear when the types are
POD-like and we can just splat the empty key across memory.
Sadly we can't optimize the normal loop well enough because we can't
turn the conditional store into an unconditional store according to the
memory model.
This loop actually showed up in a profile of code that was calling clear
as a serious source of time. =[
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310189
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Craig Topper [Sat, 5 Aug 2017 22:44:38 +0000 (22:44 +0000)]
[InstCombine] Regenerate test28_sub test case in xor.ll that I forgot to commit after fixing a typo in r310186.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310188
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Craig Topper [Sat, 5 Aug 2017 20:00:44 +0000 (20:00 +0000)]
[InstCombine] Fold (C - X) ^ signmask -> (C + signmask - X).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310186
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Craig Topper [Sat, 5 Aug 2017 20:00:42 +0000 (20:00 +0000)]
[InstCombine] Teach the code that pulls logical operators through constant shifts to handle vector splats too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310185
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Craig Topper [Sat, 5 Aug 2017 20:00:41 +0000 (20:00 +0000)]
[InstCombine] Support vector splats in foldSelectICmpAnd.
Unfortunately, it looks like there's some other missed optimizations in the generated code for some of these cases. I'll try to look at some of those next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310184
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Dinar Temirbulatov [Sat, 5 Aug 2017 18:43:52 +0000 (18:43 +0000)]
[SLPVectorizer] Add extra parameter to setInsertPointAfterBundle to handle different opcodes, NFCI.
Differential Revision: https://reviews.llvm.org/D35769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310183
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Sanjay Patel [Sat, 5 Aug 2017 15:19:18 +0000 (15:19 +0000)]
[InstCombine] refactor trunc(binop) transforms; NFCI
In addition to moving the shift transforms over, we may want to
detect too-wide rotate patterns here (PR34046).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310181
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Florian Hahn [Sat, 5 Aug 2017 15:14:06 +0000 (15:14 +0000)]
[ARM] The ARM backend is MachineVerifier clean now.
Summary: Thanks everyone involved in fixing the outstanding issues.
Reviewers: rovka, MatzeB, efriedma
Reviewed By: MatzeB
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310180
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Florian Hahn [Sat, 5 Aug 2017 12:13:13 +0000 (12:13 +0000)]
[ARM] Add registers to debuginfo MIR test cases.
Summary:
MIRParserImpl::computeFunctionProperties uses MRI.getNumVirtRegs() to
set the NoVReg property. By adding a bunch of registers to the MIR test
cases, the NoVReg property is not set when importing the MIR. Otherwise
NoVReg is set after instruction selection while the machine instructions
still contain virtual registers, causing expensive checks to fail.
Reviewers: efriedma, MatzeB, aprantl
Reviewed By: MatzeB, aprantl
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D36152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310178
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Chandler Carruth [Sat, 5 Aug 2017 08:33:16 +0000 (08:33 +0000)]
[LCG] Remove yet another variable only used inside of asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310174
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Benjamin Kramer [Sat, 5 Aug 2017 08:28:48 +0000 (08:28 +0000)]
[LCG] Fold otherwise unused variable into assert.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310173
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Matt Arsenault [Sat, 5 Aug 2017 07:50:18 +0000 (07:50 +0000)]
IPRA: Don't crash on null getCallPreservedMask
Kernels aren't callable, so they don't have a call preserved mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310172
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Chandler Carruth [Sat, 5 Aug 2017 07:37:00 +0000 (07:37 +0000)]
[LCG] Completely remove the parent set and leaf tracking for RefSCCs.
After the previous series of patches, this is now trivial and deletes
a pretty astonishing amount of complexity. This has been a long time
coming, as the move toward a PO sequence of RefSCCs started eroding the
underlying use cases for this half of the data structure.
Among the biggest advantages here is that now there aren't two
independent data structures that need to stay in sync.
Some of my profiling has also indicated that updating the parent sets
was among the most expensive parts of the lazy call graph. Eliminating
it whole sale is likely to be a nice win in terms of compile time.
Last but not least, I had discussed with some folks previously keeping
it around for asserts and other correctness checking, but once the
fundamentals of the parent and child checking were implemented without
the parent sets their value in correctness checking was tiny and no
where near worth the cost of the complexity required to keep everything
up-to-date.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310171
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Chandler Carruth [Sat, 5 Aug 2017 06:24:09 +0000 (06:24 +0000)]
[LCG] Re-implement the basic isParentOf, isAncestorOf, isChildOf, and
isDescendantOf methods on RefSCCs in terms of the forward edges rather
than the parent sets.
This is technically slower, but probably not interestingly slower, and
all of these routines were already so expensive that they're guarded
behind both !NDEBUG and EXPENSIVE_CHECKS.
This removes another non-critical usage of parent sets.
I've also added some comments to try and help clarify to any potential
users the costs of these routines. They're mostly useful for debugging,
asserts, or other queries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310170
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Chandler Carruth [Sat, 5 Aug 2017 05:47:37 +0000 (05:47 +0000)]
[LCG] Add the concept of a "dead" node and use it to avoid a complex
walk over the parent set.
When removing a single function from the call graph, we previously would
walk the entire RefSCC's parent set and then walk every outgoing edge
just to find the ones to remove. In addition to this being quite high
complexity in theory, it is also the last fundamental use of the parent
sets.
With this change, when we remove a function we transform the node
containing it to be recognizably "dead" and then teach the edge
iterators to recognize edges to such nodes and skip them the same way
they skip null edges.
We can't move fully to using "dead" nodes -- when disconnecting two live
nodes we need to null out the edge. But the complexity this adds to the
edge sequence isn't too bad and the simplification of lazily handling
this seems like a significant win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310169
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Joel Jones [Sat, 5 Aug 2017 04:30:55 +0000 (04:30 +0000)]
[AArch64] LSE Atomics reorg - part 1
Add memory synchronization semantics to LSE Atomics.
The memory semantics feature will be added in a subsequent patch.
In this patch, several corrections were added to the existing LSE Atomics
implementation, based on the ARM Errata D11904 from 05/12/2017.
Patch by: steleman
Differential Revision: https://reviews.llvm.org/D35319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310167
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Chandler Carruth [Sat, 5 Aug 2017 04:04:06 +0000 (04:04 +0000)]
[LCG] Replace an implicit bool operator with a named function. (NFC)
The definition of 'false' here was already pretty vague and debatable,
and I'm about to add another potential 'false' that would actually make
much more sense in a bool operator. Especially given how rarely this is
used, a nicely named method seems better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310165
91177308-0d34-0410-b5e6-
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Chandler Carruth [Sat, 5 Aug 2017 03:37:39 +0000 (03:37 +0000)]
[LCG] When removing a dead function and clearing out the data
structures, actually null out the graph pointers as well. We won't ever
update these, and we certainly shouldn't be calling any methods on them,
so it seems good to defensively nuke them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310164
91177308-0d34-0410-b5e6-
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Chandler Carruth [Sat, 5 Aug 2017 03:37:39 +0000 (03:37 +0000)]
[LCG] Rather than walking the directed graph structure to update graph
pointers in node objects, just walk the map from function to node.
It doesn't have stable ordering, but works just as well and is much
simpler. We don't need ordering when just updating internal pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310163
91177308-0d34-0410-b5e6-
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Chandler Carruth [Sat, 5 Aug 2017 03:37:38 +0000 (03:37 +0000)]
[LCG] Remove the complex walk of the parent sets to update graph
pointers.
This is completely unnecessary as we have a trivial list of RefSCCs now
that we can walk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310162
91177308-0d34-0410-b5e6-
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Chandler Carruth [Sat, 5 Aug 2017 03:37:37 +0000 (03:37 +0000)]
[LCG] Remove the use of the parent sets to compute connectivity when
merging RefSCCs.
The logic to directly use the reference edges is simpler and not
substantially slower (despite the comments to the contrary) because this
is not actually an especially hot part of LCG in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310161
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 5 Aug 2017 01:45:17 +0000 (01:45 +0000)]
[InstCombine] In foldSelectICmpAnd, if we need to to truncate from the 'and' type to the 'select' type, do it after shifting right instead of just bailing.
Previously we were always trying to emit the zext or truncate before any shift. This meant if the 'and' mask was larger than the size of the truncate we would skip the transformation.
Now we shift the result of the and right first leaving the bit within the range of the truncate.
This matches what we are doing in foldSelectICmpAndOr for the same problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310159
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Reid Kleckner [Sat, 5 Aug 2017 00:15:40 +0000 (00:15 +0000)]
Commit the local change I had to make my test pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310153
91177308-0d34-0410-b5e6-
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Reid Kleckner [Sat, 5 Aug 2017 00:10:43 +0000 (00:10 +0000)]
[X86] Teach fastisel to select calls to dllimport functions
Summary:
Direct calls to dllimport functions are very common Windows. We should
add them to the -O0 fast path.
Reviewers: rafael
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D36197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310152
91177308-0d34-0410-b5e6-
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Kostya Serebryany [Fri, 4 Aug 2017 23:49:53 +0000 (23:49 +0000)]
[libFuzzer] use the in-binary pc table (instead of PCs captured at run-time) to implement -exit_on_src_pos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310151
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 4 Aug 2017 23:36:03 +0000 (23:36 +0000)]
[X86] Regenerate the fsin/fcos instruction test using update_llc_test_checks.py. NFC
This looks to have been converted from a grep based test at some point in a really strange way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310150
91177308-0d34-0410-b5e6-
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Petr Hosek [Fri, 4 Aug 2017 23:18:18 +0000 (23:18 +0000)]
[llvm][llvm-objcopy] When outputting to binary don't output segments that cover no sections
Sometimes LLD will produce a PT_LOAD segment that only covers the
headers (and covers no sections). GNU objcopy does not output the
segment contents for these sections. In particular this is an issue in
building magenta because the final link step for the kernel would
produce just such a PT_LOAD segment. This change is to support this case
and to match what GNU objcopy does in this case.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310149
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Kostya Serebryany [Fri, 4 Aug 2017 23:13:58 +0000 (23:13 +0000)]
[libFuzzer] print PCs using the in-binary PC-table instead of relying on PCs captured at run-time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310148
91177308-0d34-0410-b5e6-
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Adrian McCarthy [Fri, 4 Aug 2017 22:37:58 +0000 (22:37 +0000)]
Enable llvm-pdbutil to list enumerations using native PDB reader
This extends the native reader to enable llvm-pdbutil to list the enums in a
PDB and it includes a simple test. It does not yet list the values in the
enumerations, which requires an actual implementation of
NativeEnumSymbol::FindChildren.
To exercise this code, use a command like:
llvm-pdbutil pretty -native -enums foo.pdb
Differential Revision: https://reviews.llvm.org/D35738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310144
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Sanjay Patel [Fri, 4 Aug 2017 22:30:34 +0000 (22:30 +0000)]
[InstCombine] narrow truncated add/sub/mul with constant
Name: narrow_sub
%sub = sub i32 C1, %x
%r = trunc i32 %sub to i8
=>
%xn = trunc i32 %x to i8
%narrowC = trunc i32 C1 to i8
%r = sub i8 %narrowC, %xn
Name: narrow_add
%add = add i32 %x, C1
%r = trunc i32 %add to i8
=>
%xn = trunc i32 %x to i8
%narrowC = trunc i32 C1 to i8
%r = add i8 %xn, %narrowC
Name: narrow_mul
%mul = mul i32 %x, C1
%r = trunc i32 %mul to i8
=>
%xn = trunc i32 %x to i8
%narrowC = trunc i32 C1 to i8
%r = mul i8 %xn, %narrowC
http://rise4fun.com/Alive/QpS
This doesn't solve PR34046 (failure to recognize rotate):
https://bugs.llvm.org/show_bug.cgi?id=34046
...but it reduces an extra complication in the description examples
to a form that we can more easily match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310141
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Reid Kleckner [Fri, 4 Aug 2017 21:52:00 +0000 (21:52 +0000)]
[Support] Use FILE_SHARE_DELETE to fix RemoveFileOnSignal on Windows
Summary:
Tools like clang that use RemoveFileOnSignal on their output files
weren't actually able to clean up their outputs before this change. Now
the call to llvm::sys::fs::remove succeeds and the temporary file is
deleted. This is a stop-gap to fix clang before implementing the
solution outlined in PR34070.
Reviewers: davide
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D36337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310137
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Zachary Turner [Fri, 4 Aug 2017 21:15:12 +0000 (21:15 +0000)]
Fix broken PDB tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310130
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Kyle Butt [Fri, 4 Aug 2017 21:13:41 +0000 (21:13 +0000)]
BlockPlacement: add a flag to force cold block outlining w/o a profile.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310129
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Zachary Turner [Fri, 4 Aug 2017 21:10:04 +0000 (21:10 +0000)]
[pdbutil] When dumping section contribs, show the section name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310128
91177308-0d34-0410-b5e6-
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Petr Hosek [Fri, 4 Aug 2017 21:09:26 +0000 (21:09 +0000)]
Reland "[llvm][llvm-objcopy] Added support for outputting to binary in llvm-objcopy"
This change adds the "-O binary" flag which directs llvm-objcopy to
output the object file to the same format as GNU objcopy does when given
the flag "-O binary". This was done by splitting the Object class into
two subclasses ObjectELF and ObjectBianry which each output a different
format but relay on the same code to read in the Object in Object.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D34480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310127
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Kostya Serebryany [Fri, 4 Aug 2017 20:47:22 +0000 (20:47 +0000)]
[libFuzzer] re-enable fuzzer-printcovpcs.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310126
91177308-0d34-0410-b5e6-
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Adrian Prantl [Fri, 4 Aug 2017 20:41:37 +0000 (20:41 +0000)]
Remove unused include directive and un-break the module build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310124
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Nico Weber [Fri, 4 Aug 2017 20:40:38 +0000 (20:40 +0000)]
Revert r310055, it caused PR34074.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310123
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Sanjay Patel [Fri, 4 Aug 2017 20:38:33 +0000 (20:38 +0000)]
[InstCombine] add vector tests for truncated math; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310122
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Nico Weber [Fri, 4 Aug 2017 20:24:13 +0000 (20:24 +0000)]
Revert r310058, it caused PR34073.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310118
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Amara Emerson [Fri, 4 Aug 2017 20:19:46 +0000 (20:19 +0000)]
[SCEV] Preserve NSW information for sext(subtract).
Pushes the sext onto the operands of a Sub if NSW is present.
Also adds support for propagating the nowrap flags of the
llvm.ssub.with.overflow intrinsic during analysis.
Differential Revision: https://reviews.llvm.org/D35256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310117
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Quentin Colombet [Fri, 4 Aug 2017 20:15:46 +0000 (20:15 +0000)]
[GlobalISel] Remove the GISelAccessor API.
Its sole purpose was to avoid spreading around ifdefs related to
building global-isel. Since r309990, GlobalISel is not optional anymore,
thus, we can get rid of this mechanism all together.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310115
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Quentin Colombet [Fri, 4 Aug 2017 20:15:41 +0000 (20:15 +0000)]
[GlobalISel] Remove a stall comment in CMake.
Thanks to Diana Picus <diana.picus@linaro.org> for noticing.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310114
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Kostya Serebryany [Fri, 4 Aug 2017 20:09:15 +0000 (20:09 +0000)]
[libFuzzer] make a test more robust
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310113
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Kostya Serebryany [Fri, 4 Aug 2017 20:05:25 +0000 (20:05 +0000)]
[libFuzzer] remove the now redundant 'LLVMFuzzer-' prefix from libFuzzer tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310110
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Zachary Turner [Fri, 4 Aug 2017 20:02:38 +0000 (20:02 +0000)]
[llvm-pdbutil] Dump image section headers.
Image section headers are stored in the DBI stream, but we
had no way to dump them. This patch adds dumping support,
along with some tests that LLD actually dumps them correctly.
Differential Revision: https://reviews.llvm.org/D36332
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310107
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Kostya Serebryany [Fri, 4 Aug 2017 20:01:04 +0000 (20:01 +0000)]
[libFuzzer] split one test into several
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310106
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Sanjay Patel [Fri, 4 Aug 2017 19:29:32 +0000 (19:29 +0000)]
[InstCombine] auto-generate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310101
91177308-0d34-0410-b5e6-
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George Karpenkov [Fri, 4 Aug 2017 19:29:16 +0000 (19:29 +0000)]
[libFuzzer tests] Only enable libFuzzer tests if
-DLIBFUZZER_ENABLE_TESTS=ON is set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310100
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Ulrich Weigand [Fri, 4 Aug 2017 18:57:58 +0000 (18:57 +0000)]
[SystemZ] Add support for 128-bit atomic load/store/cmpxchg
This adds support for the main 128-bit atomic operations,
using the SystemZ instructions LPQ, STPQ, and CDSG.
Generating these instructions is a bit more complex than usual
since the i128 type is not legal for the back-end. Therefore,
we have to hook the LowerOperationWrapper and ReplaceNodeResults
TargetLowering callbacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310094
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Ulrich Weigand [Fri, 4 Aug 2017 18:53:35 +0000 (18:53 +0000)]
[SystemZ] Eliminate unnecessary serialization operations
We currently emit a serialization operation (bcr 14, 0) before every
atomic load and after every atomic store. This is overly conservative.
The SystemZ architecture actually does not require any serialization
for atomic loads, and a serialization after an atomic store only if
we need to enforce sequential consistency. This is what other compilers
for the platform implement as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310093
91177308-0d34-0410-b5e6-
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Evgeny Stupachenko [Fri, 4 Aug 2017 18:46:13 +0000 (18:46 +0000)]
Fix PR33514
Summary:
The bug was uncovered after fix of PR23384 (part 3 of 3).
The patch restricts pointer multiplication in SCEV computaion for ICmpZero.
Reviewers: qcolombet
Differential Revision: http://reviews.llvm.org/D36170
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310092
91177308-0d34-0410-b5e6-
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Kostya Serebryany [Fri, 4 Aug 2017 18:43:39 +0000 (18:43 +0000)]
[libFuzzer] make trace-pc.test more reliable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310091
91177308-0d34-0410-b5e6-
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Connor Abbott [Fri, 4 Aug 2017 18:36:54 +0000 (18:36 +0000)]
[AMDGPU] Implement llvm.amdgcn.set.inactive intrinsic
Summary:
This intrinsic lets us set inactive lanes to an identity value when
implementing wavefront reductions. In combination with Whole Wavefront
Mode, it lets inactive lanes be skipped over as required by GLSL/Vulkan.
Lowering the intrinsic needs to happen post-RA so that RA knows that the
destination isn't completely overwritten due to the EXEC shenanigans, so
we need another pseudo-instruction to represent the un-lowered
intrinsic.
Reviewers: tstellar, arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D34719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310088
91177308-0d34-0410-b5e6-
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Connor Abbott [Fri, 4 Aug 2017 18:36:52 +0000 (18:36 +0000)]
[AMDGPU] Add support for Whole Wavefront Mode
Summary:
Whole Wavefront Wode (WWM) is similar to WQM, except that all of the
lanes are always enabled, regardless of control flow. This is required
for implementing wavefront reductions in non-uniform control flow, where
we need to use the inactive lanes to propagate intermediate results, so
they need to be enabled. We need to propagate WWM to uses (unless
they're explicitly marked as exact) so that they also propagate
intermediate results correctly. We do the analysis and exec mask munging
during the WQM pass, since there are interactions with WQM for things
that require both WQM and WWM. For simplicity, WWM is entirely
block-local -- blocks are never WWM on entry or exit of a block, and WWM
is not propagated to the block level. This means that computations
involving WWM cannot involve control flow, but we only ever plan to use
WWM for a few limited purposes (none of which involve control flow)
anyways.
Shaders can ask for WWM using the @llvm.amdgcn.wwm intrinsic. There
isn't yet a way to turn WWM off -- that will be added in a future
change.
Finally, it turns out that turning on inactive lanes causes a number of
problems with register allocation. While the best long-term solution
seems like teaching LLVM's register allocator about predication, for now
we need to add some hacks to prevent ourselves from getting into trouble
due to constraints that aren't currently expressed in LLVM. For the gory
details, see the comments at the top of SIFixWWMLiveness.cpp.
Reviewers: arsenm, nhaehnle, tpr
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D35524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310087
91177308-0d34-0410-b5e6-
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Connor Abbott [Fri, 4 Aug 2017 18:36:50 +0000 (18:36 +0000)]
[AMDGPU] refactor WQM pass in preparation for WWM (NFCI)
Summary:
Right now, the WQM pass conflates two different things when tracking the
Needs of an instruction:
1. Needs can be StateWQM, which is propagated to other instructions, and
means that this instruction (and everything it depends on) must be
calculated in WQM.
2. Needs can be StateExact, which is not propagated to other
instructions, and means that this instruction must not be calculated in
WQM and WQM-ness must not be propagated past this instruction.
This works now because there are only two different states, but in the
future we want to be able to express things like "calculate this in WQM,
but please disable WWM and don't propagate it" (to implement
@llvm.amdgcn.set.inactive). In order to do this, we need to split the
per-instruction Needs field in two: a new Needs field, which can only
contain StateWQM (and in the future, StateWWM) and is propagated to
sources, and a Disables field, which can also contain just StateWQM or
nothing for now.
We keep the per-block tracking the same for now, by translating
Needs/Disables to the old representation with only StateWQM or
StateExact. The other place that needs special handling is when we
emit the state transitions. We could just translate back to the old
representation there as well, which we almost do, but instead of 0 as a
placeholder value for "any state," we explicitly or together all the
states an instruction is allowed to be in. This lets us refactor the
code in preparation for WWM, where we'll need to be able to handle
things like "this instruction must be in Exact or WQM, but not WWM."
Reviewers: arsenm, nhaehnle, tpr
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D35523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310086
91177308-0d34-0410-b5e6-
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Connor Abbott [Fri, 4 Aug 2017 18:36:49 +0000 (18:36 +0000)]
[AMDGPU] Add an llvm.amdgcn.wqm intrinsic for WQM
Summary:
Previously, we assumed that certain types of instructions needed WQM in
pixel shaders, particularly DS instructions and image sampling
instructions. This was ok because with OpenGL, the assumption was
correct. But we want to start using DPP instructions for derivatives as
well as other things, so the assumption that we can infer whether to use
WQM based on the instruction won't continue to hold. This intrinsic lets
frontends like Mesa indicate what things need WQM based on their
knowledge of the API, rather than second-guessing them in the backend.
We need to keep around the old method of enabling WQM, but eventually we
should remove it once Mesa catches up. For now, this will let us use DPP
instructions for computing derivatives correctly.
Reviewers: arsenm, tpr, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D35167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310085
91177308-0d34-0410-b5e6-
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Marcello Maggioni [Fri, 4 Aug 2017 18:24:09 +0000 (18:24 +0000)]
[MachineOperand] Add ChangeToTargetIndex method. NFC
Differential Revision: https://reviews.llvm.org/D36301
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310083
91177308-0d34-0410-b5e6-
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Reid Kleckner [Fri, 4 Aug 2017 17:43:49 +0000 (17:43 +0000)]
[Support] Remove getPathFromOpenFD, it was unused
Summary:
It was added to support clang warnings about includes with case
mismatches, but it ended up not being necessary.
Reviewers: twoh, rafael
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D36328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310078
91177308-0d34-0410-b5e6-
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George Karpenkov [Fri, 4 Aug 2017 17:43:29 +0000 (17:43 +0000)]
Fixing buildbots: do not register check-fuzzer if clang or asan are not
present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310077
91177308-0d34-0410-b5e6-
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George Karpenkov [Fri, 4 Aug 2017 17:43:28 +0000 (17:43 +0000)]
Drop Windows support from libFuzzer tests.
Differential Revision: https://reviews.llvm.org/D36205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310076
91177308-0d34-0410-b5e6-
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George Karpenkov [Fri, 4 Aug 2017 17:19:45 +0000 (17:19 +0000)]
Port libFuzzer tests to LIT. Do not require two-stage build for check-fuzzer.
This revision ports all libFuzzer tests apart from the unittest to LIT.
The advantages of doing so include:
- Tests being self-contained
- Much easier debugging of a single test
- No need for using a two-stage compilation
The unit-test is still compiled using CMake, but it does not need a
freshly built compiler.
NOTE: The previous two-stage bot configuration will NOT work, as in the
second stage build LLVM_USE_SANITIZER is set, which disables ASAN from
being built.
Thus bots will be reconfigured in the next few commits.
Differential Revision: https://reviews.llvm.org/D36295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310075
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Easwaran Raman [Fri, 4 Aug 2017 17:15:17 +0000 (17:15 +0000)]
[Inliner] Fix a typo in option description. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310073
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Javed Absar [Fri, 4 Aug 2017 17:10:11 +0000 (17:10 +0000)]
[ARM] Use searchable-table for banked registers
This is a continuation of https://reviews.llvm.org/D36219
This patch uses reverse mapping (encoding->name) in
ARMInstPrinter::printBankedRegOperand to get rid of
hard-coded values (as pointed out by @olista01).
Reviewed by: @fhahn, @rovka, @olista01
Differential Revision: https://reviews.llvm.org/D36260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310072
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Reid Kleckner [Fri, 4 Aug 2017 17:09:11 +0000 (17:09 +0000)]
[ArgPromotion] Preserve alignment of byval argument in new alloca
The frontend may have requested a higher alignment for any reason, and
downstream optimizations may already have taken advantage of it. We
should keep the same alignment when moving the allocation from the
parameter area to the local variable area.
Fixes PR34038
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310071
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Craig Topper [Fri, 4 Aug 2017 16:59:29 +0000 (16:59 +0000)]
[ConstantInt] Use ConstantInt::getValue instead of Constant::getUniqueInteger in a few places where we obviously have a ConstantInt. NFC
getUniqueInteger will ultimately call ConstantInt::getValue, but calling ConstantInt::getValue should be inlined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310069
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Chad Rosier [Fri, 4 Aug 2017 16:44:06 +0000 (16:44 +0000)]
[AArch64] Fix an assertion for pre-index generation with unscaled loads/stores.
Differential Revision: https://reviews.llvm.org/D36248
PR34035
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310066
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Dehao Chen [Fri, 4 Aug 2017 16:20:54 +0000 (16:20 +0000)]
Adjust the hotness threshold from 99.9% to 99%.
Summary: We originally set the hotness threshold as 99.9% to be consistent with gcc FDO. But because the inline heuristic is different between 2 compilers: llvm uses bottom-up algorithm while gcc uses priority based. The LLVM algorithm tends to inline too much early that prevents hot callsites from further inlined into its caller. Due to this restriction, we think it is reasonable to lower the hotness threshold to give priority to those that are really hot. Our experiments show that this change would improve performance on large applications. Note that the inline heuristic has great room for further tuning. Once the inline heuristics are refined, we could adjust this threshold to allow inlining for less hot callsites.
Reviewers: davidxl, tejohnson, eraman
Reviewed By: tejohnson
Subscribers: sanjoy, llvm-commits
Differential Revision: https://reviews.llvm.org/D36317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310065
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Benjamin Kramer [Fri, 4 Aug 2017 16:08:41 +0000 (16:08 +0000)]
[InstCombine] Fold single-use variable into assert.
Avoids unused variable warnings in Release builds. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310064
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Craig Topper [Fri, 4 Aug 2017 16:07:20 +0000 (16:07 +0000)]
[InstCombine] Remove the (not (sext)) case from foldBoolSextMaskToSelect and inline the remaining code to match visitOr
Summary:
The (not (sext)) case is really (xor (sext), -1) which should have been simplified to (sext (xor, 1)) before we got here. So we shouldn't need to handle it.
With that taken care of we only need to two cases so don't need the swap anymore. This makes us in sync with the equivalent code in visitOr so inline this to match.
Reviewers: spatel, eli.friedman, majnemer
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310063
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Craig Topper [Fri, 4 Aug 2017 16:07:18 +0000 (16:07 +0000)]
[InstCombine] Use ConstantInt::getFalse to reduce some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310062
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