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Alexander Shaposhnikov [Fri, 18 May 2018 04:18:41 +0000 (04:18 +0000)]
[llvm-objcopy] Fix formatting
Apply clang-format -i -style=llvm to llvm-objcopy.cpp
NFC.
Test plan: make check-all
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332693
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Walter Lee [Fri, 18 May 2018 04:10:38 +0000 (04:10 +0000)]
[asan] Add instrumentation support for Myriad
1. Define Myriad-specific ASan constants.
2. Add code to generate an outer loop that checks that the address is
in DRAM range, and strip the cache bit from the address. The
former is required because Myriad has no memory protection, and it
is up to the instrumentation to range-check before using it to
index into the shadow memory.
3. Do not add an unreachable instruction after the error reporting
function; on Myriad such function may return if the run-time has
not been initialized.
4. Add a test.
Differential Revision: https://reviews.llvm.org/D46451
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332692
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Eric Christopher [Fri, 18 May 2018 03:13:08 +0000 (03:13 +0000)]
Revert "Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug info emission.""
This reapplies commits: r330271, r330592, r330779.
[DEBUG] Initial adaptation of NVPTX target for debug info emission.
Summary:
Patch adds initial emission of the debug info for NVPTX target.
Currently, only .file and .loc directives are emitted, everything else is
commented out to not break the compilation of Cuda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332689
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Eric Christopher [Fri, 18 May 2018 02:39:57 +0000 (02:39 +0000)]
Tidy comment up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332687
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Eli Friedman [Fri, 18 May 2018 02:11:25 +0000 (02:11 +0000)]
Fix unused lambda capture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332686
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Eli Friedman [Fri, 18 May 2018 01:52:16 +0000 (01:52 +0000)]
[MachineOutliner] Count savings from outlining in bytes.
Counting the number of instructions is both unintuitive and inaccurate.
On AArch64, this only affects the generated remarks and certain rare
pseudo-instructions, but it will have a bigger impact on other targets.
Differential Revision: https://reviews.llvm.org/D46921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332685
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Keno Fischer [Fri, 18 May 2018 01:03:01 +0000 (01:03 +0000)]
[X86DomainReassignment] Don't compare stack-allocated values by address
Summary:
The Closure allocated in the main loop is allocated on the stack. However,
later in the code its address is taken (and used for comparisons). This
obviously doesn't work. In fact, the Closure will get the same stack address
during every loop iteration, rendering the check that intended to identify
Closure conflicts entirely ineffective. Fix this bug by giving every Closure
a unique ID and using that for comparison. Alternatively, we could heap
allocate the closure object.
Fixes PR37396
Fixes JuliaLang/julia#27032
Reviewers: craig.topper, guyblank
Reviewed By: craig.topper
Subscribers: vchuravy, llvm-commits
Differential Revision: https://reviews.llvm.org/D46800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332682
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Keno Fischer [Fri, 18 May 2018 00:40:52 +0000 (00:40 +0000)]
[X86DomainReassignment] Don't delete IMPLICIT_DEF nodes
Summary:
We cannot simply delete IMPLICIT_DEF nodes. They may be used
later (e.g. by a PHI) and deleting them will cause later passes (e.g.
LiveVariables) to crash. However, it seems fine to ignore them for
purposes of the domain reassignment (as we do with PHI).
Fixes PR37430
Fixes JuliaLang/julia#27080
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332680
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Zachary Turner [Thu, 17 May 2018 22:55:15 +0000 (22:55 +0000)]
Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes."
This fixes the remaining failing tests, so resubmitting with no
functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332676
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Peter Collingbourne [Thu, 17 May 2018 22:11:43 +0000 (22:11 +0000)]
Support: Add a raw_ostream::write_zeros() function. NFCI.
This will eventually replace MCObjectWriter::WriteZeros.
Part of PR37466.
Differential Revision: https://reviews.llvm.org/D47033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332675
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George Burgess IV [Thu, 17 May 2018 21:56:39 +0000 (21:56 +0000)]
Revert r332657: "[AA] cfl-anders-aa with field sensitivity"
I don't believe the person who LGTMed this review has appropriate
context on this code. I apologize if I'm wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332674
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Changpeng Fang [Thu, 17 May 2018 21:49:44 +0000 (21:49 +0000)]
AMDGPU/SI: Don't promote alloca to vector for atomic load/store
Summary:
Don't promote alloca to vector for atomic load/store
Reviewer:
arsenm
Differential Revision:
https://reviews.llvm.org/D46085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332673
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Zachary Turner [Thu, 17 May 2018 21:49:25 +0000 (21:49 +0000)]
Revert "[pdb] Change /DEBUG:GHASH to emit 8 byte hashes."
A few tests haven't been properly updated, so reverting while
I have time to investigate proper fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332672
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Zachary Turner [Thu, 17 May 2018 21:22:48 +0000 (21:22 +0000)]
[pdb] Change /DEBUG:GHASH to emit 8 byte hashes.
Previously we emitted 20-byte SHA1 hashes. This is overkill
for identifying debug info records, and has the negative side
effect of making object files bigger and links slower. By
using only the last 8 bytes of a SHA1, we get smaller object
files and ~10% faster links.
This modifies the format of the .debug$H section by adding a new
value for the hash algorithm field, so that the linker will still
work when its object files have an old format.
Differential Revision: https://reviews.llvm.org/D46855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332669
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Heejin Ahn [Thu, 17 May 2018 20:52:03 +0000 (20:52 +0000)]
[WebAssembly] Add Wasm personality and isScopedEHPersonality()
Summary:
- Add wasm personality function
- Re-categorize the existing `isFuncletEHPersonality()` function into
two different functions: `isFuncletEHPersonality()` and
`isScopedEHPersonality(). This becomes necessary as wasm EH uses scoped
EH instructions (catchswitch, catchpad/ret, and cleanuppad/ret) but not
outlined funclets.
- Changed some callsites of `isFuncletEHPersonality()` to
`isScopedEHPersonality()` if they are related to scoped EH IR-level
stuff.
Reviewers: majnemer, dschuff, rnk
Subscribers: jfb, sbc100, jgravelle-google, eraman, JDevlieghere, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D45559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332667
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Lang Hames [Thu, 17 May 2018 20:48:58 +0000 (20:48 +0000)]
[ORC] Consolidate materialization errors, and generate them in VSO's
notifyFailed method rather than passing in an error generator.
VSO::notifyFailed is responsible for notifying queries that they will not
succeed due to error. In practice the queries don't care about the details
of the failure, just the fact that a failure occurred for some symbols.
Having VSO::notifyFailed take care of this simplifies the interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332666
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Lang Hames [Thu, 17 May 2018 20:48:50 +0000 (20:48 +0000)]
[ORC] Make MaterializationResponsibility's constructor private.
MaterializationResponsibility instances should be created by
MaterializationUnits only. Making the constructor private enforces this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332665
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Reid Kleckner [Thu, 17 May 2018 20:47:22 +0000 (20:47 +0000)]
[codeview] Include record prefix in global type hashing
The prefix includes type kind, which is important to preserve. Two
different type leafs can easily have the same interior record contents
as another type.
We ran into this issue in PR37492 where a bitfield type record collided
with a const modifier record. Their contents were bitwise identical, but
their kinds were different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332664
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Peter Collingbourne [Thu, 17 May 2018 20:46:01 +0000 (20:46 +0000)]
ARC, Nios2: Silence build warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332663
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David Bolvansky [Thu, 17 May 2018 20:23:33 +0000 (20:23 +0000)]
[AA] cfl-anders-aa with field sensitivity
Summary:
There was some unfinished work started for offset tracking in CFLGraph by the author of implementation of Andersen algorithm. This work was completed and support for field sensitivity was added to the core of Andersen algorithm.
The performance results seem promising.
SPEC2006 int_base score was increased by 1.1 % (I compared clang 6.0 with clang 6.0 with this patch). The avergae compile time was increased by +- 1 % according my measures with small and medium C/C++ projects (I did not tested it on the large projects with milions of lines of code)
Reviewers: chandlerc, george.burgess.iv, rja
Reviewed By: rja
Subscribers: rja, llvm-commits
Differential Revision: https://reviews.llvm.org/D46282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332657
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Diego Caballero [Thu, 17 May 2018 19:24:47 +0000 (19:24 +0000)]
[LV][VPlan] Build plain CFG with simple VPInstructions for outer loops.
Patch #3 from VPlan Outer Loop Vectorization Patch Series #1
(RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).
Expected to be NFC for the current inner loop vectorization path. It
introduces the basic algorithm to build the VPlan plain CFG (single-level
CFG, no hierarchical CFG (H-CFG), yet) in the VPlan-native vectorization
path using VPInstructions. It includes:
- VPlanHCFGBuilder: Main class to build the VPlan H-CFG (plain CFG without nested regions, for now).
- VPlanVerifier: Main class with utilities to check the consistency of a H-CFG.
- VPlanBlockUtils: Main class with utilities to manipulate VPBlockBases in VPlan.
Reviewers: rengolin, fhahn, mkuper, mssimpso, a.elovikov, hfinkel, aprantl.
Differential Revision: https://reviews.llvm.org/D44338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332654
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Xinliang David Li [Thu, 17 May 2018 19:24:03 +0000 (19:24 +0000)]
Add a limit for phi folding instcombine
Differential Revision: http://reviews.llvm.org/D47023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332653
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Matt Davis [Thu, 17 May 2018 19:22:29 +0000 (19:22 +0000)]
[llvm-mca] Make Dispatch a subclass of Stage.
Summary:
The logic of dispatch remains the same, but now DispatchUnit is a Stage (DispatchStage).
This change has the benefit of simplifying the backend runCycle() code.
The same logic applies, but it belongs to different components now. This is just a start,
eventually we will need to remove the call to the DispatchStage in Scheduler.cpp, but
that will be a separate patch. This change is mostly a renaming and moving of existing logic.
This change also encouraged me to remove the Subtarget (STI) member from the
Backend class. That member was used to initialize the other members of Backend
and to eventually call DispatchUnit::dispatch(). Now that we have Stages, we
can eliminate this by instantiating the DispatchStage with everything it needs
at the time of construction (e.g., Subtarget). That change allows us to call
DispatchStage::execute(IR) as we expect to call execute() for all other stages.
Once we add the Stage list (D46907) we can more cleanly call preExecute() on
all of the stages, DispatchStage, will probably wrap cycleEvent() in that
case.
Made some formatting and minor cleanups to README.txt. Some of the text
was re-flowed to stay within 80 cols.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb, courbet
Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332652
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Sanjay Patel [Thu, 17 May 2018 18:43:44 +0000 (18:43 +0000)]
[x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332648
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Reid Kleckner [Thu, 17 May 2018 18:33:42 +0000 (18:33 +0000)]
[llvm-pdbutil] Dump struct/class/union sizes in the minimal dump format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332645
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Anastasis Grammenos [Thu, 17 May 2018 18:19:58 +0000 (18:19 +0000)]
[Debugify] Print the output to stderr
Currently debugify prints it's output to stdout,
with this patch all the output generated goes to stderr.
This change lets us use debugify without taking away
the ability to pipe the output to other llvm tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332642
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Sameer AbuAsal [Thu, 17 May 2018 18:14:53 +0000 (18:14 +0000)]
[RISCV] Separate base from offset in lowerGlobalAddress
Summary:
When lowering global address, lower the base as a TargetGlobal first then
create an SDNode for the offset separately and chain it to the address calculation
This optimization will create a DAG where the base address of a global access will
be reused between different access. The offset can later be folded into the immediate
part of the memory access instruction.
With this optimization we generate:
lui a0, %hi(s)
addi a0, a0, %lo(s) ; shared base address.
addi a1, zero, 20 ; 2 instructions per access.
sw a1, 44(a0)
addi a1, zero, 10
sw a1, 8(a0)
addi a1, zero, 30
sw a1, 80(a0)
Instead of:
lui a0, %hi(s+44) ; 3 instructions per access.
addi a1, zero, 20
sw a1, %lo(s+44)(a0)
lui a0, %hi(s+8)
addi a1, zero, 10
sw a1, %lo(s+8)(a0)
lui a0, %hi(s+80)
addi a1, zero, 30
sw a1, %lo(s+80)(a0)
Which will save one instruction per access.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits
Differential Revision: https://reviews.llvm.org/D46989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332641
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Sanjay Patel [Thu, 17 May 2018 18:13:58 +0000 (18:13 +0000)]
[x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332640
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Sanjay Patel [Thu, 17 May 2018 18:09:56 +0000 (18:09 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332638
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Sanjay Patel [Thu, 17 May 2018 18:08:27 +0000 (18:08 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
Follow-up to:
https://reviews.llvm.org/rL332538
...because that change wasn't enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332637
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Sanjay Patel [Thu, 17 May 2018 18:07:02 +0000 (18:07 +0000)]
[AArch64] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
Follow-up to:
https://reviews.llvm.org/rL332534
...because that change wasn't enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332636
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Mandeep Singh Grang [Thu, 17 May 2018 17:31:27 +0000 (17:31 +0000)]
[RISCV] Implement MC layer support for the tail pseudoinstruction
Summary:
This patch implements MC support for tail psuedo instruction.
A follow-up patch implements the codegen support as well as handling of the indirect tail pseudo instruction.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, llvm-commits
Differential Revision: https://reviews.llvm.org/D46221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332634
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Sam Clegg [Thu, 17 May 2018 17:15:15 +0000 (17:15 +0000)]
[WebAssembly] MC: Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332632
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Chris Bieneman [Thu, 17 May 2018 16:58:44 +0000 (16:58 +0000)]
[CMake] Support runtimes in distributions
Summary:
This patch adds a new internal variable
LLVM_RUNTIME_DISTRIBUTION_COMPONENTS which specifies distribution
components that are part of runtime projects, and thus should be exposed
from runtime configuraitons up into the top-level CMake configurations.
This is required for allowing runtime components to be included in
LLVM_DISTRIBUTION_COMPONENTS because we verify that the build and
install targets exist for every component specified for the
distribution.
Without this patch runtimes and builtins can only be included in
distributions in whole, not by component.
Reviewers: phosek
Reviewed By: phosek
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D46705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332631
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Simon Pilgrim [Thu, 17 May 2018 16:58:42 +0000 (16:58 +0000)]
Fix typo in declaring code-block snippet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332630
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Chris Bieneman [Thu, 17 May 2018 16:55:29 +0000 (16:55 +0000)]
[CMake] Make optimizing sanitizer builds optional
This behavior has been the default for a long time, so the default value is On, however this can make it difficult to debug sanitizer failures, so we should have an option to turn it off.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332628
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Andrea Di Biagio [Thu, 17 May 2018 16:48:53 +0000 (16:48 +0000)]
[llvm-mca] Add an example showing how to get Intel assembly syntax
Patch by Jeff Muizelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332627
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Simon Pilgrim [Thu, 17 May 2018 16:47:30 +0000 (16:47 +0000)]
[X86] Split WriteCMOV + WriteCMOV2 scheduler classes
Handle SNB+ targets which treat CMOVA/CMOVBE specially due to partial EFLAGS handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332626
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Changpeng Fang [Thu, 17 May 2018 16:45:01 +0000 (16:45 +0000)]
AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.
Summary:
The current StructurizeCFG pass only works for CFG with one exit. AMDGPUUnifyDivergentExitNodes combines multiple "return" blocks and/or "unreachable" blocks
to one exit block for the Structurizer to work. However, infinite loop is another kind of special "exit", and if we don't handle it, the case of multiple exits will prevent the structurizer from working.
In this work, for each infinite loop, we add a dummy edge to the "return" block, and thus the AMDGPUUnifyDivergentExitNodes pass will work with infinite loops.
This will make CFG with infinite loops be structurized.
Reviewer:
nhaehnle
Differential Revision:
https://reviews.llvm.org/D46340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332625
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Petar Jovanovic [Thu, 17 May 2018 16:30:32 +0000 (16:30 +0000)]
[mips] Add support for Global INValidate ASE
This includes
Instructions: ginvi, ginvt,
Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv
Attribute: ginv
.MIPS.abiflags: GINV (0x20000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D46268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332624
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Craig Topper [Thu, 17 May 2018 16:29:52 +0000 (16:29 +0000)]
[InstCombine] Propagate the nsw/nuw flags from the add in the 'shifty' abs pattern to the sub in the select version.
According to alive this is valid. I'm hoping to use this to make an assumption that the sign bit is zero after this sequence. The only way it wouldn't be is if the input was INT__MIN, but by preserving the flags we can make doing this to INT_MIN UB.
The nuw flags is weird because it creates such a contradiction that the original number would have to be positive meaning we could remove the select entirely, but we don't get that far.
Differential Revision: https://reviews.llvm.org/D46988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332623
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Simon Pilgrim [Thu, 17 May 2018 16:29:12 +0000 (16:29 +0000)]
[llvm-mca][X86] Add CMOV test files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332622
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Alex Bradbury [Thu, 17 May 2018 15:51:37 +0000 (15:51 +0000)]
[RISCV] Set isReMaterializable on ADDI and LUI instructions
The isReMaterlizable flag is somewhat confusing, unlike most other instruction
flags it is currently interpreted as a hint (mightBeRematerializable would be
a better name). While LUI is always rematerialisable, for an instruction like
ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable
will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn
calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on
the logic in the latter to pick out instances of ADDI that really are
rematerializable.
The isReMaterializable flag does make a difference on a variety of test
programs. The recently committed remat.ll test case demonstrates how stack
usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the
Proc0 function in dhrystone reduces from 192 bytes to 112 bytes.
For the sake of completeness, this patch also implements
RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of
places, it doesn't seem to result in different codegen for any programs I've
thrown at it. However, it is called in the rematerialisation codepath and it
seems sensible to implement something correct here.
Differential Revision: https://reviews.llvm.org/D46182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332617
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 17 May 2018 15:43:23 +0000 (15:43 +0000)]
[X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332616
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 17 May 2018 15:35:14 +0000 (15:35 +0000)]
[llvm-mca] Hide unrelated flags from the -help output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332615
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 17 May 2018 14:37:31 +0000 (14:37 +0000)]
[llvm-exegesis] Remove redudant explicit template instantiations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332611
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Mikulin [Thu, 17 May 2018 14:29:07 +0000 (14:29 +0000)]
In thin and full LTO + CFI, direct function calls may go through jump table
entries to reach the target. Since these calls don't require type checks,
we can short-circuit them to their real targets.
Differential Revision: https://reviews.llvm.org/D46326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332610
91177308-0d34-0410-b5e6-
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Clement Courbet [Thu, 17 May 2018 13:41:28 +0000 (13:41 +0000)]
[llvm-exegesis] Write out inconsistencies to a file.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332608
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Thu, 17 May 2018 13:21:18 +0000 (13:21 +0000)]
[Hexagon] Use addAliasForDirective for data directives
Data directives such as .word, .half, .hword are currently parsed using
HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from
AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in
favour of using addAliasForDirective.
Differential Revision: https://reviews.llvm.org/D46999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332607
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 17 May 2018 12:43:42 +0000 (12:43 +0000)]
[X86] Split WriteADC/WriteADCRMW scheduler classes
For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332605
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 17 May 2018 12:41:56 +0000 (12:41 +0000)]
[llvm-exegesis] Disable failing ARM assembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332604
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 17 May 2018 12:27:03 +0000 (12:27 +0000)]
[llvm-mca] add flag -all-views and flag -all-stats.
Flag -all-views enables all the views.
Flag -all-stats enables all the views that print hardware statistics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332602
91177308-0d34-0410-b5e6-
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Clement Courbet [Thu, 17 May 2018 12:25:18 +0000 (12:25 +0000)]
[llvm-exegesis] Analysis: detect clustering inconsistencies.
Summary:
Warn on instructions that should have the same performance
characteristics according to the sched model but actually
differ in their benchmarks.
Next step: Make the display nicer to browse, I was thinking maybe html.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D46945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332601
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 17 May 2018 11:55:08 +0000 (11:55 +0000)]
[llvm-exegesis] Disable the tests failing on buildbots while we investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332600
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Paulsson [Thu, 17 May 2018 11:53:56 +0000 (11:53 +0000)]
[SystemZ] Commenting (NFC)
Some minor commenting in scheduler files.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332599
91177308-0d34-0410-b5e6-
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Clement Courbet [Thu, 17 May 2018 11:51:49 +0000 (11:51 +0000)]
[llvm-exegesis][NFC] Remove dead function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332597
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 17 May 2018 11:32:38 +0000 (11:32 +0000)]
[llvm-mca][X86] Add ADX test files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332595
91177308-0d34-0410-b5e6-
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Clement Courbet [Thu, 17 May 2018 11:31:24 +0000 (11:31 +0000)]
Fix r332592 : X86 tests should use the X86 target, not the native targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332594
91177308-0d34-0410-b5e6-
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Clement Courbet [Thu, 17 May 2018 10:52:18 +0000 (10:52 +0000)]
reland r332579: [llvm-exegesis] Update to cover latency through another opcode.
Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.
https://reviews.llvm.org/D46821
(with fixed ARM tests)
Authored by Guillaume Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332592
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 17 May 2018 10:36:29 +0000 (10:36 +0000)]
[X86][SNB] Minor scheduler cleanup
Merge 2 instregex and explain the VMOVDQArr/MOVDQArr difference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332591
91177308-0d34-0410-b5e6-
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Sander de Smalen [Thu, 17 May 2018 09:05:41 +0000 (09:05 +0000)]
[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) store instructions.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332584
91177308-0d34-0410-b5e6-
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Mikael Holmen [Thu, 17 May 2018 09:05:40 +0000 (09:05 +0000)]
Require DominatorTree when requiring/preserving LoopInfo in the old pass manager
Summary:
Require DominatorTree when requiring/preserving LoopInfo in the old pass manager
BreakCriticalEdges tries to keep LoopInfo and DominatorTree updated if they
exist. However, since commit r321653 and r321805, to update LoopInfo we
must have a DominatorTree, or we will hit an assert.
To fix this we now make a couple of passes that only required/preserved
LoopInfo also require DominatorTree.
This solves PR37334.
Reviewers: eli.friedman, efriedma
Reviewed By: efriedma
Subscribers: efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D46829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332583
91177308-0d34-0410-b5e6-
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Martin Storsjo [Thu, 17 May 2018 08:16:08 +0000 (08:16 +0000)]
[Analysis] Only use _unlocked stdio functions on linux
The existing comment said that the functions were available only
on GNU/Linux (and on certain Android versions), but only checked
T.isGNUEnvironment() which also is true on MinGW (for arch-windows-gnu
triplets), which doesn't have such functions.
Existing checks in the initialize function in TargetLibraryInfo.cpp
also use only T.isOSLinux() to check for glibc features.
This fixes use of stdio on MinGW.
Differential Revision: https://reviews.llvm.org/D47002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332581
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 17 May 2018 08:12:29 +0000 (08:12 +0000)]
Revert r332579 "[llvm-exegesis] Update to cover latency through another opcode."
The revision failed to update the ARM tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332580
91177308-0d34-0410-b5e6-
96231b3b80d8
Clement Courbet [Thu, 17 May 2018 07:38:21 +0000 (07:38 +0000)]
[llvm-exegesis] Update to cover latency through another opcode.
Restructuring the code to measure latency and uops.
The end goal is to have this program spawn another process to deal with SIGILL and other malformed programs. It is not yet the case in this redesign, it is still the main program that runs the code (and may crash).
It now uses BitVector instead of Graph for performance reasons.
https://reviews.llvm.org/D46821
Authored by Guillaume Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332579
91177308-0d34-0410-b5e6-
96231b3b80d8
Bjorn Pettersson [Thu, 17 May 2018 07:21:41 +0000 (07:21 +0000)]
[SROA] Handle PHI with multiple duplicate predecessors
Summary:
The verifier accepts PHI nodes with multiple entries for the
same basic block, as long as the value is the same.
As seen in PR37203, SROA did not handle such PHI nodes properly
when speculating loads over the PHI, since it inserted multiple
loads in the predecessor block and changed the PHI into having
multiple entries for the same basic block, but with different
values.
This patch teaches SROA to reuse the same speculated load for
each PHI duplicate entry in such situations.
Resolves: https://bugs.llvm.org/show_bug.cgi?id=37203
Reviewers: uabelho, chandlerc, hfinkel, bkramer, efriedma
Reviewed By: efriedma
Subscribers: dberlin, efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D46426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332577
91177308-0d34-0410-b5e6-
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Hiroshi Inoue [Thu, 17 May 2018 06:32:17 +0000 (06:32 +0000)]
[SROA] pr37267: fix assertion failure in integer widening
The current integer widening does not support rewriting partial split slices in rewriteIntegerStore (and rewriteIntegerLoad).
This patch adds explicit checks for this case in isIntegerWideningViableForSlice.
Before r322533, splitting is allowed only for the whole-alloca slice and hence the above case is implicitly rejected by another check `if (DL.getTypeStoreSize(ValueTy) > Size)` because whole-alloca slice is larger than the partition.
Differential Revision: https://reviews.llvm.org/D46750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332575
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Thu, 17 May 2018 05:58:08 +0000 (05:58 +0000)]
[RISCV] Add support for .half, .hword, .word, .dword directives
These directives are recognised by gas. Support is added through the use of
addAliasForDirective.
Also match RISC-V gcc in preferring .half and .word for 16-bit and 32-bit data
directives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332574
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 17 May 2018 05:41:11 +0000 (05:41 +0000)]
[X86] Add OptForSize to a couple load folding patterns. Remove some bad FIXME comments.
The FIXME comments were about preventing load folding to avoid a partial xmm update. But these instructions use GPR as input when the load isn't folded. This won't help prevent a partial xmm update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332573
91177308-0d34-0410-b5e6-
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Petr Hosek [Thu, 17 May 2018 03:39:03 +0000 (03:39 +0000)]
[CMake] Support building shared library for Fuchsia
Fuchsia uses ELF as a file format and LLD as the linker so we can
use the same implementation as other ELF based platforms.
Differential Revision: https://reviews.llvm.org/D46991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332570
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 17 May 2018 03:24:25 +0000 (03:24 +0000)]
[Thumb2] fix typo in test from r332548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332569
91177308-0d34-0410-b5e6-
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Douglas Yung [Thu, 17 May 2018 01:36:25 +0000 (01:36 +0000)]
Mark test with "REQUIRES: shell" since it directly invokes "sh" and was failing on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332563
91177308-0d34-0410-b5e6-
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Stanislav Mekhanoshin [Thu, 17 May 2018 01:30:51 +0000 (01:30 +0000)]
[AMDGPU] Move lsr test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332562
91177308-0d34-0410-b5e6-
96231b3b80d8
Dan Gohman [Thu, 17 May 2018 00:14:13 +0000 (00:14 +0000)]
[WebAssembly] Fix the opcode number for i64.load16_u.
Fixes PR37488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332561
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 16 May 2018 23:39:27 +0000 (23:39 +0000)]
[CodeGen] Use MachineInstr::getOperand(0) instead of gets the defs iterator_range and calling begin. NFC
Defs are well defined to come first in MachineInstr operand list. No need for a more complex indirection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332559
91177308-0d34-0410-b5e6-
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Greg Clayton [Wed, 16 May 2018 23:29:36 +0000 (23:29 +0000)]
Revert 332508 as it caused problems in the clang test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332555
91177308-0d34-0410-b5e6-
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Vedant Kumar [Wed, 16 May 2018 23:20:42 +0000 (23:20 +0000)]
[STLExtras] Add size() for ranges, and remove distance()
r332057 introduced distance() for ranges. Based on post-commit feedback,
this renames distance() to size(). The new size() is also only enabled
when the operation is O(1).
Differential Revision: https://reviews.llvm.org/D46976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332551
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:49:08 +0000 (22:49 +0000)]
[Hexagon] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332550
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:48:48 +0000 (22:48 +0000)]
[PowerPC] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332549
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:47:51 +0000 (22:47 +0000)]
[Thumb] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332548
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:47:42 +0000 (22:47 +0000)]
[Thumb] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332547
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 16 May 2018 22:31:42 +0000 (22:31 +0000)]
[NFC] WebAssembly build break #2
Summary:
Same as r332530, move WasmSymbol::dump to an implementation file to avoid linker
issues when the dump function is seen in the header, doesn't get eliminated, and
then linking fails because of the missing dependency.
<rdar://problem/
40258137>
Reviewers: sbc100, ncw, paquette, vsk, dschuff
Subscribers: jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D46985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332542
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Wed, 16 May 2018 22:24:30 +0000 (22:24 +0000)]
[ORC] Rewrite the VSO symbol table yet again. Update related utilities.
VSOs now track dependencies for materializing symbols. Each symbol must have its
dependencies registered with the VSO prior to finalization. Usually this will
involve registering the dependencies returned in
AsynchronousSymbolQuery::ResolutionResults for queries made while linking the
symbols being materialized.
Queries against symbols are notified that a symbol is ready once it and all of
its transitive dependencies are finalized, allowing compilation work to be
broken up and moved between threads without queries returning until their
symbols fully safe to access / execute.
Related utilities (VSO, MaterializationUnit, MaterializationResponsibility) are
updated to support dependence tracking and more explicitly track responsibility
for symbols from the point of definition until they are finalized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332541
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 22:24:22 +0000 (22:24 +0000)]
[X86] Update SNB/generic scheduler tests missed from rL332536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332540
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:20:33 +0000 (22:20 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332539
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:20:26 +0000 (22:20 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332538
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 22:20:11 +0000 (22:20 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332537
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 16 May 2018 22:14:29 +0000 (22:14 +0000)]
[X86][SNB] Remove unnecessary CVT InstRW overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332536
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Wed, 16 May 2018 22:13:18 +0000 (22:13 +0000)]
[WebAssembly] Remove unused headers in MCWasmObjectWriter
Differential Revision: https://reviews.llvm.org/D46969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332535
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 21:57:57 +0000 (21:57 +0000)]
[AArch64] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332534
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 21:57:19 +0000 (21:57 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332533
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 16 May 2018 21:57:00 +0000 (21:57 +0000)]
[ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.
And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332532
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Wed, 16 May 2018 21:45:39 +0000 (21:45 +0000)]
[InstCombine] Fix the signature of fgets_unlocked.
It returns a pointer, not an int. This miscompiles all code that uses
the return value of fgets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332531
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 16 May 2018 21:24:03 +0000 (21:24 +0000)]
[NFC] WebAssembly build fix
Summary:
r332305 added a use of llvm::wasm::toString in llvm::object::WasmSymbol::print,
which is in a header file. It also moves toString to BinaryFormat. This has the
unintended side-effect that any inclusion of Object/Wasm.h now relies on
toString, and needs to required_libraries = BinaryFormat. Thankfully most builds
don't fail with this because print just isn't used and gets eliminated, dropping
the required dependency in the process. Not all builds are so lucky.
Fix this issue by moving print to the corresponding .cpp file.
<rdar://problem/
40258137>
Reviewers: sbc100, ncw, paquette
Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D46977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332530
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Eli Friedman [Wed, 16 May 2018 21:20:16 +0000 (21:20 +0000)]
[MachineOutliner] Don't outline instructions that modify SP.
This breaks the code which saves and restores LR, so we can't outline
without doing something more complicated for stack adjustment.
Found by inspection; we get lucky in most cases because getMemOpInfo
only handles STRWpost, not any other pre/post-increment forms. But it
hits a couple of artificial testcases in the tree.
Differential Revision: https://reviews.llvm.org/D46920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332529
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Nico Weber [Wed, 16 May 2018 21:13:56 +0000 (21:13 +0000)]
_WIN32 straggler I missed in r331127; no-op in practice
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332528
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Krzysztof Parzyszek [Wed, 16 May 2018 21:02:43 +0000 (21:02 +0000)]
[Hexagon] Fix the order of operands when selecting QCAT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332526
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Krzysztof Parzyszek [Wed, 16 May 2018 21:00:24 +0000 (21:00 +0000)]
[Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332525
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Simon Pilgrim [Wed, 16 May 2018 20:52:52 +0000 (20:52 +0000)]
[X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)
As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure.
Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs.
Differential Revision: https://reviews.llvm.org/D46959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332524
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Konstantin Zhuravlyov [Wed, 16 May 2018 20:47:48 +0000 (20:47 +0000)]
AMDGPU : Recalculate SGPRs when trap handler is supported
Differential Revision: https://reviews.llvm.org/D29911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332523
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