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Bjorn Steinbrink [Sun, 17 Dec 2017 01:54:25 +0000 (01:54 +0000)]
Properly handle multi-element and dynamically sized allocas in getPointerDereferenceableBytes()
Reviewers: hfinkel, rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320938
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Craig Topper [Sun, 17 Dec 2017 01:35:48 +0000 (01:35 +0000)]
[X86] Use extract_vector_elt instead of X86ISD::VEXTRACT for isel of vXi1 extractions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320937
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Craig Topper [Sun, 17 Dec 2017 01:35:47 +0000 (01:35 +0000)]
[X86] Canonicalize extract_vector_elt from vXi1 to always return MVT::i32.
This allows us to remove some isel patterns that allowed MVT::i8 result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320936
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Craig Topper [Sun, 17 Dec 2017 01:35:44 +0000 (01:35 +0000)]
[X86] Don't create X86ISD::VEXTRACT nodes directly. Use EXTRACT_VECTOR_ELT and allow that to be legaized to VEXTRACT.
I think we can remove the VEXTRACT node completely and use a canonicalized EXTRACT_VECTOR_ELT instead. This is a first step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320935
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Simon Pilgrim [Sat, 16 Dec 2017 23:37:51 +0000 (23:37 +0000)]
Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320934
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Simon Pilgrim [Sat, 16 Dec 2017 23:32:18 +0000 (23:32 +0000)]
[X86][AVX] lowerVectorShuffleAsBroadcast - aggressively peek through BITCASTs
Assuming we can safely adjust the broadcast index for the new type to keep it suitably aligned, then peek through BITCASTs when looking for the broadcast source.
Fixes PR32007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320933
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Simon Pilgrim [Sat, 16 Dec 2017 23:09:57 +0000 (23:09 +0000)]
[X86][AVX] Use extract128BitVector helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320932
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Simon Pilgrim [Sat, 16 Dec 2017 22:57:17 +0000 (22:57 +0000)]
[X86][AVX] Fix failed broadcast fold
Strip excess BITCASTs from EXTRACT_SUBVECTOR input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320930
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Sean Fertile [Sat, 16 Dec 2017 22:41:39 +0000 (22:41 +0000)]
[Memcpy Loop Lowering] Only calculate residual size/bytes copied when needed.
If the loop operand type is int8 then there will be no residual loop for the
unknown size expansion. Dont create the residual-size and bytes-copied values
when they are not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320929
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Craig Topper [Sat, 16 Dec 2017 21:12:24 +0000 (21:12 +0000)]
[X86] Don't pass a zero input to the passthru operand of getVectorMaskingNode/getScalarMaskingNode when its going to emit an ISD::OR/ISD::AND. NFCI
In those cases, the pass thru operand of the methods isn't used. The calls to the scalar version were passing a MVT::i1 zero, which is an illegal type at the stage this code runs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320928
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Craig Topper [Sat, 16 Dec 2017 21:12:23 +0000 (21:12 +0000)]
[X86] Have getVectorMaskingNode return an ISD::AND for X86ISD::VPSHUFBITQMB instead of creating a select with one input being 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320927
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Craig Topper [Sat, 16 Dec 2017 19:31:36 +0000 (19:31 +0000)]
[X86] When using vpopcntdq for ctpop of v8i16 vectors, only promote to v8i32.
Previously we promoted to v8i64, but we don't need to go all the way to 512-bits. If we have VLX we can use the 256-bit instruction. And even if we don't have VLX we can widen v8i32 to v16i32 and drop the upper half.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320926
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Craig Topper [Sat, 16 Dec 2017 18:35:31 +0000 (18:35 +0000)]
[X86] Combine some more scheduler model entries using regular expressions.
We had a lot of separate 32 and 64 instructions that had the same scheduling data. This merges them into the same regular expression. This is pretty consistent with a lot of other instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320924
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Craig Topper [Sat, 16 Dec 2017 18:35:29 +0000 (18:35 +0000)]
[X86] Use instrs instead of instregex for gather/scatter instructions in the scheduler models. Combine into single InstrRW entries.
The reduces the number of scheduler groups in subtarget info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320923
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Simon Pilgrim [Sat, 16 Dec 2017 17:18:15 +0000 (17:18 +0000)]
[InstCombine] Regenerate FMUL/FMA combine tests with update_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320922
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Sanjay Patel [Sat, 16 Dec 2017 16:41:17 +0000 (16:41 +0000)]
[InstCombine] canonicalize shifty abs(): ashr+add+xor --> cmp+neg+sel
We want to do this for 2 reasons:
1. Value tracking does not recognize the ashr variant, so it would fail to match for cases like D39766.
2. DAGCombiner does better at producing optimal codegen when we have the cmp+sel pattern.
More detail about what happens in the backend:
1. DAGCombiner has a generic transform for all targets to convert the scalar cmp+sel variant of abs
into the shift variant. That is the opposite of this IR canonicalization.
2. DAGCombiner has a generic transform for all targets to convert the vector cmp+sel variant of abs
into either an ABS node or the shift variant. That is again the opposite of this IR canonicalization.
3. DAGCombiner has a generic transform for all targets to convert the exact shift variants produced by #1 or #2
into an ISD::ABS node. Note: It would be an efficiency improvement if we had #1 go directly to an ABS node
when that's legal/custom.
4. The pattern matching above is incomplete, so it is possible to escape the intended/optimal codegen in a
variety of ways.
a. For #2, the vector path is missing the case for setlt with a '1' constant.
b. For #3, we are missing a match for commuted versions of the shift variants.
5. Therefore, this IR canonicalization can only help get us to the optimal codegen. The version of cmp+sel
produced by this patch will be recognized in the DAG and converted to an ABS node when possible or the
shift sequence when not.
6. In the following examples with this patch applied, we may get conditional moves rather than the shift
produced by the generic DAGCombiner transforms. The conditional move is created using a target-specific
decision for any given target. Whether it is optimal or not for a particular subtarget may be up for debate.
define i32 @abs_shifty(i32 %x) {
%signbit = ashr i32 %x, 31
%add = add i32 %signbit, %x
%abs = xor i32 %signbit, %add
ret i32 %abs
}
define i32 @abs_cmpsubsel(i32 %x) {
%cmp = icmp slt i32 %x, zeroinitializer
%sub = sub i32 zeroinitializer, %x
%abs = select i1 %cmp, i32 %sub, i32 %x
ret i32 %abs
}
define <4 x i32> @abs_shifty_vec(<4 x i32> %x) {
%signbit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%add = add <4 x i32> %signbit, %x
%abs = xor <4 x i32> %signbit, %add
ret <4 x i32> %abs
}
define <4 x i32> @abs_cmpsubsel_vec(<4 x i32> %x) {
%cmp = icmp slt <4 x i32> %x, zeroinitializer
%sub = sub <4 x i32> zeroinitializer, %x
%abs = select <4 x i1> %cmp, <4 x i32> %sub, <4 x i32> %x
ret <4 x i32> %abs
}
> $ ./opt -instcombine shiftyabs.ll -S | ./llc -o - -mtriple=x86_64 -mattr=avx
> abs_shifty:
> movl %edi, %eax
> negl %eax
> cmovll %edi, %eax
> retq
>
> abs_cmpsubsel:
> movl %edi, %eax
> negl %eax
> cmovll %edi, %eax
> retq
>
> abs_shifty_vec:
> vpabsd %xmm0, %xmm0
> retq
>
> abs_cmpsubsel_vec:
> vpabsd %xmm0, %xmm0
> retq
>
> $ ./opt -instcombine shiftyabs.ll -S | ./llc -o - -mtriple=aarch64
> abs_shifty:
> cmp w0, #0 // =0
> cneg w0, w0, mi
> ret
>
> abs_cmpsubsel:
> cmp w0, #0 // =0
> cneg w0, w0, mi
> ret
>
> abs_shifty_vec:
> abs v0.4s, v0.4s
> ret
>
> abs_cmpsubsel_vec:
> abs v0.4s, v0.4s
> ret
>
> $ ./opt -instcombine shiftyabs.ll -S | ./llc -o - -mtriple=powerpc64le
> abs_shifty:
> srawi 4, 3, 31
> add 3, 3, 4
> xor 3, 3, 4
> blr
>
> abs_cmpsubsel:
> srawi 4, 3, 31
> add 3, 3, 4
> xor 3, 3, 4
> blr
>
> abs_shifty_vec:
> vspltisw 3, -16
> vspltisw 4, 15
> vsubuwm 3, 4, 3
> vsraw 3, 2, 3
> vadduwm 2, 2, 3
> xxlxor 34, 34, 35
> blr
>
> abs_cmpsubsel_vec:
> vspltisw 3, -16
> vspltisw 4, 15
> vsubuwm 3, 4, 3
> vsraw 3, 2, 3
> vadduwm 2, 2, 3
> xxlxor 34, 34, 35
> blr
>
Differential Revision: https://reviews.llvm.org/D40984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320921
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Craig Topper [Sat, 16 Dec 2017 08:25:30 +0000 (08:25 +0000)]
[X86] Remove GCCBuiltin from kand/kandn/kor/kxor/kxnor/knot intrinsics so clang can implement with native IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320918
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Craig Topper [Sat, 16 Dec 2017 06:58:30 +0000 (06:58 +0000)]
[X86] Remove unneeded code for handling the old kunpck intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320917
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Hal Finkel [Sat, 16 Dec 2017 05:10:20 +0000 (05:10 +0000)]
Move Transforms/LoopVectorize/consecutive-ptr-cg-bug.ll into the X86 subdirectory
This test depends on X86's TTI; move into the X86 subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320914
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Hal Finkel [Sat, 16 Dec 2017 02:55:24 +0000 (02:55 +0000)]
[LV] Extend InstWidening with CM_Widen_Recursive
Changes to the original scalar loop during LV code gen cause the return value
of Legal->isConsecutivePtr() to be inconsistent with the return value during
legal/cost phases (further analysis and information of the bug is in D39346).
This patch is an alternative fix to PR34965 following the CM_Widen approach
proposed by Ayal and Gil in D39346. It extends InstWidening enum with
CM_Widen_Reverse to properly record the widening decision for consecutive
reverse memory accesses and, consequently, get rid of the
Legal->isConsetuviePtr() call in LV code gen. I think this is a simpler/cleaner
solution to PR34965 than the one in D39346.
Fixes PR34965.
Patch by Diego Caballero, thanks!
Differential Revision: https://reviews.llvm.org/D40742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320913
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Galina Kistanova [Sat, 16 Dec 2017 02:54:17 +0000 (02:54 +0000)]
Fixed warning 'function declaration isn’t a prototype [-Werror=strict-prototypes]'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320912
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Hal Finkel [Sat, 16 Dec 2017 02:42:18 +0000 (02:42 +0000)]
[PowerPC, AsmParser] Enable the mnemonic spell corrector
r307148 added an assembly mnemonic spelling correction support and enabled it
on ARM. This enables that support on PowerPC as well.
Patch by Dmitry Venikov, thanks!
Differential Revision: https://reviews.llvm.org/D40552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320911
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Craig Topper [Sat, 16 Dec 2017 02:40:28 +0000 (02:40 +0000)]
[X86] Add 128 and 256-bit VPOPCNTDQ instructions. Adjust some tablegen classes LZCNT/POPCNT.
I think when this instruction was first published it was only for a Knights CPU and thus VLX version was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320910
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Vitaly Buka [Sat, 16 Dec 2017 02:40:20 +0000 (02:40 +0000)]
[LTO] Update tests for r320905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320909
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Vitaly Buka [Sat, 16 Dec 2017 02:12:35 +0000 (02:12 +0000)]
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320907
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Sam Clegg [Sat, 16 Dec 2017 02:10:16 +0000 (02:10 +0000)]
[WebAssembly] Return ArrayRef's rather than const std::vector&
From working on lld I've learned this is generally the
preferred way for several reasons (e.g. more concise, improves
encapsulation).
Differential Revision: https://reviews.llvm.org/D41265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320906
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Vitaly Buka [Sat, 16 Dec 2017 02:10:00 +0000 (02:10 +0000)]
[LTO] Make processing of combined module more consistent
Summary:
1. Use stream 0 only for combined module. Previously if combined module was not
processes ThinLTO used the stream for own output. However small changes in input,
could trigger combined module and shuffle outputs making life of llvm::LTO harder.
2. Always process combined module and write output to stream 0. Processing empty
combined module is cheap and allows llvm::LTO users to avoid implementing processing
which is already done in llvm::LTO.
Subscribers: mehdi_amini, inglorion, eraman, hiraditya
Differential Revision: https://reviews.llvm.org/D41267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320905
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Teresa Johnson [Sat, 16 Dec 2017 01:35:36 +0000 (01:35 +0000)]
Add another missing -enable-import-metadata to test
r320895 modified a test so that it needs -enable-import-metadata which
is false by default for NDEBUG, found another place that needs this
added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320903
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Hal Finkel [Sat, 16 Dec 2017 01:26:25 +0000 (01:26 +0000)]
[SimplifyLibCalls] Inline calls to cabs when it's safe to do so
When unsafe algerbra is allowed calls to cabs(r) can be replaced by:
sqrt(creal(r)*creal(r) + cimag(r)*cimag(r))
Patch by Paul Walker, thanks!
Differential Revision: https://reviews.llvm.org/D40069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320901
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Hal Finkel [Sat, 16 Dec 2017 01:12:50 +0000 (01:12 +0000)]
[LV] NFC patch for moving VP*Recipe class definitions from LoopVectorize.cpp to VPlan.h
This is a small step forward to move VPlan stuff to where it should belong (i.e., VPlan.*):
1. VP*Recipe classes in LoopVectorize.cpp are moved to VPlan.h.
2. Many of VP*Recipe::print() and execute() definitions are still left in
LoopVectorize.cpp since they refer to things declared in LoopVectorize.cpp. To
be moved to VPlan.cpp at a later time.
3. InterleaveGroup class is moved from anonymous namespace to llvm namespace.
Referencing it in anonymous namespace from VPlan.h ended up in warning.
Patch by Hideki Saito, thanks!
Differential Revision: https://reviews.llvm.org/D41045
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320900
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Teresa Johnson [Sat, 16 Dec 2017 01:00:48 +0000 (01:00 +0000)]
Add -enable-import-metadata to test
r320895 modified a test so that it needs -enable-import-metadata which
is false by default for NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320899
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Craig Topper [Sat, 16 Dec 2017 00:33:16 +0000 (00:33 +0000)]
[X86] Add back the assert from r320830 that was reverted in r320850
Hopefully r320864 has fixed the offending case that failed the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320898
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Teresa Johnson [Sat, 16 Dec 2017 00:29:31 +0000 (00:29 +0000)]
Fix NDEBUG build problem in r320895
Fix incorrect placement of #endif causing NDEBUG build failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320897
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Teresa Johnson [Sat, 16 Dec 2017 00:18:12 +0000 (00:18 +0000)]
[ThinLTO] Enable importing of aliases as copy of aliasee
Summary:
This implements a missing feature to allow importing of aliases, which
was previously disabled because alias cannot be available_externally.
We instead import an alias as a copy of its aliasee.
Some additional work was required in the IndexBitcodeWriter for the
distributed build case, to ensure that the aliasee has a value id
in the distributed index file (i.e. even when it is not being
imported directly).
This is a performance win in codes that have many aliases, e.g. C++
applications that have many constructor and destructor aliases.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D40747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320895
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David Blaikie [Fri, 15 Dec 2017 23:52:06 +0000 (23:52 +0000)]
Fix WebAssembly backend for some LLVM API changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320893
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Quentin Colombet [Fri, 15 Dec 2017 23:24:39 +0000 (23:24 +0000)]
[TableGen][GlobalISel] Make the different Matcher comparable
This opens refactoring opportunities in the match table now that we can
check that two predicates are the same.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320890
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Quentin Colombet [Fri, 15 Dec 2017 23:24:36 +0000 (23:24 +0000)]
[TableGen][GlobalISel] Fix unused variable warning in release mode
Introduced in r320887.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320889
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Paul Robinson [Fri, 15 Dec 2017 23:21:52 +0000 (23:21 +0000)]
Revert "Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header.""
This reverts commit
0afef672f63f0e4e91938656bc73424a8c058bfc.
Still failing at runtime on bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320888
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Quentin Colombet [Fri, 15 Dec 2017 23:07:42 +0000 (23:07 +0000)]
[TableGen][GlobalISel] Have the predicate directly know which data they are dealing with
Prior to this patch, a predicate wouldn't make sense outside of its
rule. Indeed, it was only during emitting a rule that a predicate would
be made aware of the IDs of the data it is checking. Because of that,
predicates could not be moved around or compared between each other.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320887
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Paul Robinson [Fri, 15 Dec 2017 22:57:17 +0000 (22:57 +0000)]
Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."
Adds missing support for DW_FORM_data16.
Update of r320852, fixing the unittest to use a hand-coded struct
instead of std::array to guarantee data layout.
Differential Revision: https://reviews.llvm.org/D41090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320886
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Matthias Braun [Fri, 15 Dec 2017 22:53:33 +0000 (22:53 +0000)]
Fix unused variable in non-assert builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320885
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Matthias Braun [Fri, 15 Dec 2017 22:22:58 +0000 (22:22 +0000)]
MachineFunction: Return reference from getFunction(); NFC
The Function can never be nullptr so we can return a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320884
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Matthias Braun [Fri, 15 Dec 2017 22:22:46 +0000 (22:22 +0000)]
MachineFunction: Slight refactoring; NFC
Slight cleanup/refactor in preparation for upcoming commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320882
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Matthias Braun [Fri, 15 Dec 2017 22:22:42 +0000 (22:22 +0000)]
MachineModuleInfo: Remove unused function; NFC
Remove the unused setModule() function; it would be dangerous if someone
actually used it as it wouldn't reset/recompute various other module
related data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320881
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Galina Kistanova [Fri, 15 Dec 2017 22:15:29 +0000 (22:15 +0000)]
Fixed the gcc 'enumeral and non-enumeral type in conditional expression [-Werror=extra]' warning introduced by r320750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320868
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Krzysztof Parzyszek [Fri, 15 Dec 2017 21:34:05 +0000 (21:34 +0000)]
[Hexagon] Remove recursion in visitUsesOf, replace with use queue
This is primarily to reduce stack usage, but ordering the use queue
according to the position in the code (earlier instructions visited
before later ones) reduces the number of unnecessary bottoms due to
visiting instructions out of order, e.g.
%reg1 = copy %reg0
%reg2 = copy %reg0
%reg3 = and %reg1, %reg2
Here, reg3 should be known to be same as reg0-2, but if reg3 is
evaluated after reg1 is updated, but before reg2 is updated, the two
inputs to the and will appear different, causing reg3 to become
bottom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320866
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Krzysztof Parzyszek [Fri, 15 Dec 2017 21:23:12 +0000 (21:23 +0000)]
[Hexagon] Handle concat_vectors of all allowed HVX types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320865
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 21:18:06 +0000 (21:18 +0000)]
[X86] Use AND32ri8 instead of AND64ri8 in Asan code in EmitCallAsanReport for 32-bit mode.
This seemed to work due to a quirk in the X86 MC encoder that didn't emit a REX byte that the AND64ri8 implies when in 32-bit mode. This made the encoding the same as AND32ri8. I tried to add an assert to catch the dropped REX prefix that caught this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320864
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 15 Dec 2017 21:18:05 +0000 (21:18 +0000)]
[X86] In LowerVectorCTPOP use ISD::ZERO_EXTEND/ISD::TRUNCATE instead of the target specific nodes.
The target independent nodes will get legalized to the target specific nodes by their own legalization process. Someday I'd like to stop using a target specific for zero extends and truncates of legal types so the less places we reference the target specific opcode the better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320863
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Craig Topper [Fri, 15 Dec 2017 20:57:18 +0000 (20:57 +0000)]
[X86] Remove unnecessary TODO.
When I wrote it I thought we were missing a potential optimization for KNL. But investigating further shows that for KNL we still do the optimal thing by widening to v4f32 and then using special isel patterns to widen again to zmm a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320862
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Vitaly Buka [Fri, 15 Dec 2017 20:50:25 +0000 (20:50 +0000)]
[LTO] Remove unused RegularLTOState::HasModule
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320859
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Jun Bum Lim [Fri, 15 Dec 2017 20:33:24 +0000 (20:33 +0000)]
Re-commit : [LICM] Allow sinking when foldable in loop
This recommits r320823 reverted due to the test failure in sink-foldable.ll and
an unused variable. Added "REQUIRES: aarch64-registered-target" in the test
and removed unused variable.
Original commit message:
Continue trying to sink an instruction if its users in the loop is foldable.
This will allow the instruction to be folded in the loop by decoupling it from
the user outside of the loop.
Reviewers: hfinkel, majnemer, davidxl, efriedma, danielcdh, bmakam, mcrosier
Reviewed By: hfinkel
Subscribers: javed.absar, bmakam, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320858
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Paul Robinson [Fri, 15 Dec 2017 20:29:25 +0000 (20:29 +0000)]
Revert "[DWARFv5] Dump an MD5 checksum in the line-table header."
Unit test fails on some bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320857
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Jake Ehrlich [Fri, 15 Dec 2017 20:17:55 +0000 (20:17 +0000)]
[llvm-objcopy] Reformat everything using clang-format -i
Overtime some non-clang formatted code has creeped into llvm-objcopy. This
patch fixes all of that.
Differential Revision: https://reviews.llvm.org/D41262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320856
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Fri, 15 Dec 2017 20:13:57 +0000 (20:13 +0000)]
[Hexagon] Fix operand-swapping PatFrag for atomic stores
PatFrag now has the atomicity information stored as bit fields. They
need to be copied to the new PatFrag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320855
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Paul Robinson [Fri, 15 Dec 2017 19:52:34 +0000 (19:52 +0000)]
[DWARFv5] Dump an MD5 checksum in the line-table header.
Adds missing support for DW_FORM_data16.
Differential Revision: https://reviews.llvm.org/D41090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320852
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Craig Topper [Fri, 15 Dec 2017 19:38:14 +0000 (19:38 +0000)]
[X86] Remove assert in X86MCCodeEmitter.cpp that was added in r320830.
It seems to be failing real code which is concerning, but we were silently getting away with it. I'll investigate further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320850
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Craig Topper [Fri, 15 Dec 2017 19:35:22 +0000 (19:35 +0000)]
[SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-constant index
Summary:
Currently we don't handle v32i1/v64i1 insert_vector_elt correctly as we fail to look at the number of elements closely and assume it can only be v16i1 or v8i1.
We also can't type legalize v64i1 insert_vector_elt correctly on KNL due to the type not being byte addressable as required by the legalizing through memory accesses path requires.
For the first issue, the patch now tries to pick a 512-bit register with the correct number of elements and promotes to that.
For the second issue, we now extend the vector to a byte addressable type, do the stores to memory, load the two halves, and then truncate the halves back to the original type. Technically since we changed the type, we may not need two loads, but actually checking that is more work and for the v64i1 case we do need them.
Reviewers: RKSimon, delena, spatel, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320849
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Sean Fertile [Fri, 15 Dec 2017 19:29:12 +0000 (19:29 +0000)]
[Memcpy Loop Lowering] Insert loop BB inbetween the split BB.
The original memcpy expansion inserted the loop basic block inbetween
the 2 new basic blocks created by splitting the original block the memcpy
call was in. This commit makes the new memcpy expansion do the same to keep the
layout of the IR matching between the old and new implementations.
Differential Review: https://reviews.llvm.org/D41197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320848
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Craig Topper [Fri, 15 Dec 2017 19:01:51 +0000 (19:01 +0000)]
[X86] Add 'Requires<[In64BitMode]>' to a bunch of instructions that only have memory and immediate operands.
The asm parser wasn't preventing these from being accepted in 32-bit mode. Instructions that use a GR64 register are protected by the parser rejecting the register in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320846
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Craig Topper [Fri, 15 Dec 2017 19:01:50 +0000 (19:01 +0000)]
[X86] Change BNDLDX to use anymem instead of i64mem for itsmemory operand.
This instruction doesn't access memory. It juse use a similar looking memory encoding. Don't require Intel syntax to put "qword ptr" in front of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320845
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Craig Topper [Fri, 15 Dec 2017 19:01:49 +0000 (19:01 +0000)]
[X86] Remove the 'Requires' In64BitMode/Not64BitMode from the LWP instructions.
These aren't doing anything due to a top level "let Predicates =". I think the GR32/GR64 register class protects these anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320844
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Craig Topper [Fri, 15 Dec 2017 19:01:48 +0000 (19:01 +0000)]
[X86] Remove the 'Requires<[In64BitMode]>' from SHSTK instructions.
This has no effect due to a top level "let Predicates =" around the instructions. But its also not required because the GR64 usage in the instruction guarantees it can never match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320843
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Sanjay Patel [Fri, 15 Dec 2017 18:54:29 +0000 (18:54 +0000)]
[TargetLibraryInfo] fix documentation comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320842
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Sanjay Patel [Fri, 15 Dec 2017 18:34:45 +0000 (18:34 +0000)]
[CodeGen] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320840
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Evandro Menezes [Fri, 15 Dec 2017 18:26:54 +0000 (18:26 +0000)]
[AArch64] Fix typo in the ASIMD instruction optimization pass
Fix typo in the representative instruction replacement.
Also, fix formatting and reword some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320839
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Sanjay Patel [Fri, 15 Dec 2017 18:25:13 +0000 (18:25 +0000)]
fix typo in comment and remove inaccurate comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320838
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Andrew V. Tischenko [Fri, 15 Dec 2017 18:13:05 +0000 (18:13 +0000)]
Fix for bug PR35549 - Repeated schedule comments.
Differential Revision: https://reviews.llvm.org/D40960
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320837
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Jun Bum Lim [Fri, 15 Dec 2017 18:12:49 +0000 (18:12 +0000)]
Revert "Re-commit : [LICM] Allow sinking when foldable in loop"
This reverts commit r320833.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320836
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Sanjay Patel [Fri, 15 Dec 2017 18:09:33 +0000 (18:09 +0000)]
[CodeGen] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320835
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Jun Bum Lim [Fri, 15 Dec 2017 17:58:59 +0000 (17:58 +0000)]
Re-commit : [LICM] Allow sinking when foldable in loop
This recommit r320823 after fixing a test failure.
Original commit message:
Continue trying to sink an instruction if its users in the loop is foldable.
This will allow the instruction to be folded in the loop by decoupling it from
the user outside of the loop.
Reviewers: hfinkel, majnemer, davidxl, efriedma, danielcdh, bmakam, mcrosier
Reviewed By: hfinkel
Subscribers: javed.absar, bmakam, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320833
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Michael Trent [Fri, 15 Dec 2017 17:57:40 +0000 (17:57 +0000)]
Updated llvm-objdump to display local relocations in Mach-O binaries
Summary:
llvm-objdump's Mach-O parser was updated in r306037 to display external
relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O
parser to display local relocations for MH_PRELOAD files. When used with
the -macho option relocations will be displayed in a historical format.
All tests are passing for llvm, clang, and lld. llvm-objdump builds without
compiler warnings.
rdar://
35778019
Reviewers: enderby
Reviewed By: enderby
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320832
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Craig Topper [Fri, 15 Dec 2017 17:22:58 +0000 (17:22 +0000)]
[X86] Fix XSAVE64 and similar instructions to not be allowed by the assembler in 32-bit mode.
There was a top level "let Predicates =" in the .td file that was overriding the Requires on each instruction.
I've added an assert to the code emitter to catch more cases like this. I'm sure this isn't the only place where the right predicates aren't being applied. This assert already found that we don't block btq/btsq/btrq in 32-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320830
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Jun Bum Lim [Fri, 15 Dec 2017 16:35:09 +0000 (16:35 +0000)]
Revert "[LICM] Allow sinking when foldable in loop"
This reverts commit r320823.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320828
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Francis Visoiu Mistrih [Fri, 15 Dec 2017 16:33:45 +0000 (16:33 +0000)]
[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%stack.0` instead of `<fi#0>`, and `%fixed-stack.0` instead of
`<fi#-4>` (supposing there are 4 fixed stack objects).
Only debug syntax is affected.
Differential Revision: https://reviews.llvm.org/D41027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320827
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Eugene Leviant [Fri, 15 Dec 2017 16:27:33 +0000 (16:27 +0000)]
[ThinLTO] Disallow multiple prevailing defs
https://reviews.llvm.org/D41291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320825
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Craig Topper [Fri, 15 Dec 2017 16:22:20 +0000 (16:22 +0000)]
[X86] Widen (v2i32 (fp_to_uint v2f64)) to (v8i32 (fp_to_uint v8f64)) during legalization if we have AVX512F, but not VLX. NFC
Previously we widened it using isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320824
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Jun Bum Lim [Fri, 15 Dec 2017 16:09:54 +0000 (16:09 +0000)]
[LICM] Allow sinking when foldable in loop
Summary:
Continue trying to sink an instruction if its users in the loop is foldable.
This will allow the instruction to be folded in the loop by decoupling it from
the user outside of the loop.
Reviewers: hfinkel, majnemer, davidxl, efriedma, danielcdh, bmakam, mcrosier
Reviewed By: hfinkel
Subscribers: javed.absar, bmakam, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320823
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Sam Parker [Fri, 15 Dec 2017 15:30:39 +0000 (15:30 +0000)]
[ARM] Some DAG combine tests
Add some more and and shift load combine tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320822
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Francis Visoiu Mistrih [Fri, 15 Dec 2017 15:17:18 +0000 (15:17 +0000)]
[MIR] Add support for missing CFI directives
The following CFI directives are suported by MC but not by MIR:
* .cfi_rel_offset
* .cfi_adjust_cfa_offset
* .cfi_escape
* .cfi_remember_state
* .cfi_restore_state
* .cfi_undefined
* .cfi_register
* .cfi_window_save
Add support for printing, parsing and update tests.
Differential Revision: https://reviews.llvm.org/D41230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320819
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Simon Pilgrim [Fri, 15 Dec 2017 14:37:28 +0000 (14:37 +0000)]
[X86] Add RTM schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320815
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Haicheng Wu [Fri, 15 Dec 2017 14:34:41 +0000 (14:34 +0000)]
[InlineCost] Find repeated loads in the callee
SROA analysis of InlineCost can figure out that some stores can be removed
after inlining and then the repeated loads clobbered by these stores are also
free. This patch finds these clobbered loads and adjust the inline cost
accordingly.
Differential Revision: https://reviews.llvm.org/D33946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320814
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Simon Pilgrim [Fri, 15 Dec 2017 14:22:15 +0000 (14:22 +0000)]
[X86] Add MWAITX/MONITORX schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320812
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Nemanja Ivanovic [Fri, 15 Dec 2017 14:17:45 +0000 (14:17 +0000)]
Fix the second build bot break introduced by r320791.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320811
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 15 Dec 2017 14:02:35 +0000 (14:02 +0000)]
[X86] Add XOP schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320810
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Fri, 15 Dec 2017 11:47:48 +0000 (11:47 +0000)]
Fix code causing fallthrough warnings in the PPC back end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320806
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Simon Pilgrim [Fri, 15 Dec 2017 11:32:31 +0000 (11:32 +0000)]
[X86] Add AVX512 VPOPCNTDQ schedule tests
Demonstrates how to perform full coverage avx512 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320805
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Alex Bradbury [Fri, 15 Dec 2017 10:20:51 +0000 (10:20 +0000)]
[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C.
This patch adds uimmlog2xlennonzero to reflect this constraint as well as
tests.
Differential Revision: https://reviews.llvm.org/D41216
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320799
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Nemanja Ivanovic [Fri, 15 Dec 2017 09:51:34 +0000 (09:51 +0000)]
Fix the build bot break introduced by r320791.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320798
91177308-0d34-0410-b5e6-
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Alex Bradbury [Fri, 15 Dec 2017 09:47:01 +0000 (09:47 +0000)]
[RISCV] Enable emission of alias instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.
Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)
Differential Revision: https://reviews.llvm.org/D41225
Patch by Mario Werner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320797
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Fedor Sergeev [Fri, 15 Dec 2017 09:32:11 +0000 (09:32 +0000)]
[PM] port Rewrite Statepoints For GC to the new pass manager.
Summary:
The port is nearly straightforward.
The only complication is related to the analyses handling,
since one of the analyses used in this module pass is domtree,
which is a function analysis. That requires asking for the results
of each function and disallows a single interface for run-on-module
pass action.
Decided to copy-paste the main body of this pass.
Most of its code is requesting analyses anyway, so not that much
of a copy-paste.
The rest of the code movement is to transform all the implementation
helper functions like stripNonValidData into non-member statics.
Extended all the related LLVM tests with new-pass-manager use.
No failures.
Reviewers: sanjoy, anna, reames
Reviewed By: anna
Subscribers: skatkov, llvm-commits
Differential Revision: https://reviews.llvm.org/D41162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320796
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Roger Ferrer Ibanez [Fri, 15 Dec 2017 09:24:46 +0000 (09:24 +0000)]
[ARM] Add tests for D34515
This is NFC and a preparatory step for D34515.
Differential Revision: https://reviews.llvm.org/D41122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320795
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Eugene Leviant [Fri, 15 Dec 2017 09:18:21 +0000 (09:18 +0000)]
[LLVMgold] Don't set undefined symbol as prevailing
Differential revision: https://reviews.llvm.org/D41113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320794
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Nemanja Ivanovic [Fri, 15 Dec 2017 07:27:53 +0000 (07:27 +0000)]
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
This patch adds the necessary infrastructure to convert instructions that
take two register operands to those that take a register and immediate if
the necessary operand is produced by a load-immediate. Furthermore, it uses
this infrastructure to perform such conversions twice - first at MachineSSA
and then pre-emit.
There are a number of reasons we may end up with opportunities for this
transformation, including but not limited to:
- X-Form instructions chosen since the exact offset isn't available at ISEL time
- Atomic instructions with constant operands (we will add patterns for this
in the future)
- Tail duplication may duplicate code where one block contains this redundancy
- When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant
comparands specially
Furthermore, this patch moves the initialization of PPCMIPeepholePass so that
it can be used for MIR tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320791
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Craig Topper [Fri, 15 Dec 2017 07:16:41 +0000 (07:16 +0000)]
[X86] Fix a couple bugs in my recent changes to vXi1 insert_subvector lowering.
A couple places didn't use the same SDValue variables to connect everything all the way through.
I don't have a test case for a bug in insert into the lower bits of a non-zero, non-undef vector. Not sure the best way to create that. We don't create the case when lowering concat_vectors which is the main way to get insert_subvectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320790
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Serguei Katkov [Fri, 15 Dec 2017 05:24:42 +0000 (05:24 +0000)]
[SCEV] Fix the movement of insertion point in expander. PR35406.
We cannot move the insertion point to header if SCEV contains div/rem
operations due to they may go over check for zero denominator.
Reviewers: sanjoy, mkazantsev, sebpop
Reviewed By: sebpop
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320789
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Yaxun Liu [Fri, 15 Dec 2017 03:56:57 +0000 (03:56 +0000)]
Recommit CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
The regression on ppc64 was not due to this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320788
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Nemanja Ivanovic [Fri, 15 Dec 2017 01:38:03 +0000 (01:38 +0000)]
Disabling r312514 as it causes miscompiles that show up on bootstrap
The compare elimination peephole introduced in https://reviews.llvm.org/rL312514
causes a miscompile in AMDGPUInstrInfo.cpp which in turn causes some AMDGPU
test case failures in stage2 bootstrap testing. This miscompile didn't cause any
test case failures until https://reviews.llvm.org/rL320614, so it appeared as if
that patch caused these failures.
Disabling this transformation for now to bring the build bots back to green and
the author of the patch will investigate the miscompile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320786
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Shoaib Meenai [Fri, 15 Dec 2017 01:05:48 +0000 (01:05 +0000)]
[cmake] Fix clang-cl cross-compilation on macOS
macOS paths usually start with /Users, which clang-cl interprets as a
macro undefine, leading to pretty much everything failing to compile.
CMake should be taught to put a -- in its compilation rules for clang-cl
(and I've been meaning to submit that upstream for a while). In the
meantime, however, and to support older CMake versions, we can just
create a custom make rules override to fix the compilation rules.
Differential Revision: https://reviews.llvm.org/D41219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320785
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Craig Topper [Fri, 15 Dec 2017 01:03:46 +0000 (01:03 +0000)]
[X86] Add a TODO about v8i1 CONCAT_VECTORS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320784
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