OSDN Git Service
Edward O'Callaghan [Mon, 30 Nov 2015 05:58:18 +0000 (15:58 +1000)]
r600: handle barrier opcode.
This handles the barrier opcode for EG/CM.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:56:33 +0000 (15:56 +1000)]
r600/shader: handle tess related system-values.
This adds handling for TESSINNER/TESSOUTER in the TES
where they need to be fetched from LDS,
and TESSCOORD which comes in via r0.
It also handle primitive ID and invocation ID.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:51:54 +0000 (15:51 +1000)]
r600/shader: allow multi-dimension arrays for tcs/tes inputs/outputs.
This just allows multi-dim arrays to be processed.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:51:01 +0000 (15:51 +1000)]
r600/shader: handle TES exports and streamout
when tessellation is enabled the TES shader is responsible
for handling streamout and exports.
This adds the streamout and export workarounds to TES,
and also makes sure TES sets up spi_sid.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:48:22 +0000 (15:48 +1000)]
r600/shader: emit tessellation factors to GDS at end of TCS.
When we are finished the shader, we read back all the tess factors
from LDS and write them to special global memory storage using
GDS instructions.
This also handles adding NOP when GDS or ENDLOOP end the TCS.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:46:58 +0000 (15:46 +1000)]
r600/shader: handle TCS output writing.
TCS outputs whenever they are written in the shader,
need to be written to LDS not temporaries, this handles
this case. It also fixes up the case where the output
is a relative addressed output, so we don't try to apply
the relative address at the wrong time.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:45:46 +0000 (15:45 +1000)]
r600/shader: handle VS shader writing to the LDS outputs. (v1.1)
This writes the VS shaders outputs to the LDS memory in
the correct places.
v1.1: use 24-bit
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:41:35 +0000 (15:41 +1000)]
r600/shader: handle fetching tcs/tes inputs and tcs outputs
This handles the logic for doing fetches from LDS for
TCS and TES. For TCS we need to fetch both inputs and outputs,
for TES only inputs need to be fetched.
v2: use 24-bit ops.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:39:58 +0000 (15:39 +1000)]
r600/shader: add get_lds_offset0 helper
This retrievs the offset into the LDS for a patch or
non-patch variable, it takes the RelPatch channel
and a temporary register.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:32:18 +0000 (15:32 +1000)]
r600/shader: add function to get tess constants info
This function retrieves the tess input/output info
from the tess constant buffer that is bound to the shader.
This uses a vfetch to get the values into the shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:34:14 +0000 (15:34 +1000)]
r600/shader: add utility functions to do single slot arithmatic
These utilities are to be used to do things like integer adds and
multiplies to be used in calculating the LDS offsets etc.
It handles CAYMAN MULLO differences as well.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:22:06 +0000 (15:22 +1000)]
r600/eg: workaround bug with tess shader and dynamic GPRs.
When using tessellation on eg/ni chipsets, we must disable
dynamic GPRs to workaround a hw bug where the GPU hangs
when too many things get queued.
This implements something like the r600 code to emit
the transition between static and dynamic GPRs, and to
statically allocate GPRs when tessellation is enabled.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:10:51 +0000 (15:10 +1000)]
r600/shader: move get_temp and last_instruction helpers up
These are required for tess to be used earlier.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:07:34 +0000 (15:07 +1000)]
r600: bind geometry shader ring to the correct place
When tess/gs are enabled, the geom shader ring needs
to bind to the tess eval not the vertex shader.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 05:06:23 +0000 (15:06 +1000)]
r600: create fixed function tess control shader fallback.
If we have no tess control shader, then we have to use a fallback
one that just writes the tessellation factors.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:56:10 +0000 (14:56 +1000)]
r600: create LDS info constants buffer and write LDS registers. (v2)
This creates a constant buffer with the information about
the layout of the LDS memory that is given to the vertex, tess
control and tess evaluation shaders.
This also programs the LDS size and the LS_HS_CONFIG registers,
on evergreen only.
v2: calculate lds hs num waves properly (Marek)
Emit the state only when something has changed (airlied).
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:49:02 +0000 (14:49 +1000)]
r600/eg: update shader stage emission/tf param for tess.
This update the setting of the shader stages register
when tess is enabled and add the setting of the VGT_TF_PARAM
register from the tess shader properties.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:47:07 +0000 (14:47 +1000)]
r600: hook TES/TCS shaders to the selection logic.
This hooks the TES/TCS bindings to the HW stages up.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:44:30 +0000 (14:44 +1000)]
r600: workout bitmask for the used tcs inputs/outputs.
This is used later to setup the constants to be given
to the tessellation shaders.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:43:07 +0000 (14:43 +1000)]
r600: port over the get_lds_unique_index from radeonsi
On r600 this needs to subtract 9 due to texcoord interactions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:38:18 +0000 (14:38 +1000)]
r600: add set_tess_state callback.
This just stores the values in the context to be used later
when emitting the constant buffers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:33:05 +0000 (14:33 +1000)]
r600/eg: init tess registers to defaults (v1.1)
This initialises the tess min/max using fglrx values,
and also initialises a number of other registers related
to tessellation.
v1.1: caicos doesn't have some registers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:55:43 +0000 (10:55 +1000)]
r600: hook up constants/samplers/sampler view for tessellation
This hooks the resources to the correct hw shaders when tess
is enabled.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:53:58 +0000 (10:53 +1000)]
r600: add create/bind/delete shader hooks for tessellation
This hooks up the gallium API for the tessellation shaders.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:52:23 +0000 (10:52 +1000)]
r600/sb: add LS/HS hw shader types.
This just adds printing for the hw shader types, and hooks it up.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:51:21 +0000 (10:51 +1000)]
r600/blit: add tcs/tes shader saves.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:49:11 +0000 (10:49 +1000)]
r600: disable SB for now on tess related shaders.
Note we have to disable on vertex shaders when we are
operating in tes mode.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:48:14 +0000 (10:48 +1000)]
r600: update correct hw shaders depending on configuration.
This updates the tess hw shaders from the sw ones routing
things correctly.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:45:19 +0000 (10:45 +1000)]
r600: add shader key entries for tcs and tes.
with tessellation vs can now run on ls, and tes can
run on vs or es, tcs runs on hs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:40:30 +0000 (10:40 +1000)]
r600: add PATCHES to the pipe conversion.
This just converts the value to the hw value.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:29:12 +0000 (10:29 +1000)]
r600: add functions to update ls/hs state.
This just adds the two functions, these will get hooked up
later in the shader code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Glenn Kennard [Mon, 30 Nov 2015 00:10:23 +0000 (10:10 +1000)]
r600g/sb: Support LDS ops in SB bytecode I/O
This just adds the LDS ops to the SB bytecode reader/writers.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:07:44 +0000 (10:07 +1000)]
r600: add support for LDS instruction encoding.
These are used in tessellation shaders to read/write values
between VS/TCS/TES.
This splits the eg alu assembler out to handle these
instructions.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:04:32 +0000 (10:04 +1000)]
r600/sb: add support for GDS to the sb decoder/dump. (v1.1)
This just adds support to the decoder, not actual SB support.
v1.1: fixup GDS relative mode. (Glenn).
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 00:01:41 +0000 (10:01 +1000)]
r600: add support for GDS clause to the assembler.
This just adds enough for the tessellation shaders,
which require TF_WRITE to work.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:46:14 +0000 (11:46 +1000)]
r600: use macros for updating the various stages.
These macros will make things easier to see when tess
is added to the mix.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:20:05 +0000 (11:20 +1000)]
r600: add SET_NULL_SHADER macro.
This is used to set a hw shader to NULL.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:17:08 +0000 (11:17 +1000)]
r600: move clip misc and streamout stream updates to a single place
This will be updated in a macro later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:14:26 +0000 (11:14 +1000)]
r600: move selecting shaders into earlier code.
select the ps/gs/vs in that order then process the results.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 01:12:07 +0000 (11:12 +1000)]
r600: use a macro to remove common shader selection code.
This function is going to get a lot messier with tessellation
so I'm going to use some macros to try and clean some bits
of common code up.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 03:27:22 +0000 (13:27 +1000)]
r600: move to using hw stages array for hw stage atoms
This moves to using an array of hw stages for the atoms.
Note this drops the 23 from the vertex shader, this value
is calculated internally when shaders are bound, so not
required here.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 03:15:57 +0000 (13:15 +1000)]
r600: make adjust_gprs use hw stages.
This changes the r600 specific GPR adjustment code
to use the stage defines, and arrays.
This is prep work for the tess changes later.
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 03:12:45 +0000 (13:12 +1000)]
r600: introduce HW shader stage defines
Add a list of defines for the HW stages.
We will use this for GPR calculations amongst other things.
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 30 Nov 2015 04:41:27 +0000 (14:41 +1000)]
r600: fix masks for two of the unused evergreen regs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Edward O'Callaghan [Fri, 4 Dec 2015 09:08:09 +0000 (20:08 +1100)]
gallium: Remove redundant NULL ptr checks
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 11:08:22 +0000 (22:08 +1100)]
gallium/drivers: Sanitize NULL checks into canonical form
Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 10:26:50 +0000 (21:26 +1100)]
gallium/auxiliary: Sanitize NULL checks into canonical form
Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 06:12:30 +0000 (17:12 +1100)]
gallium/auxiliary: Trivial code style cleanup
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 05:47:56 +0000 (16:47 +1100)]
gallium/drivers: Trivial code-style cleanup
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 05:36:02 +0000 (16:36 +1100)]
gallium/auxiliary: Fix zero integer literal to pointer comparison
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:34:33 +0000 (15:34 +1100)]
winsys/amdgpu: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:31:40 +0000 (15:31 +1100)]
svga: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:28:11 +0000 (15:28 +1100)]
llvmpipe: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Fri, 4 Dec 2015 04:27:18 +0000 (15:27 +1100)]
gallium/drivers/nouveau: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Edward O'Callaghan [Sun, 6 Dec 2015 07:37:49 +0000 (18:37 +1100)]
gallium/radeon*: Remove useless casts
These are unnecessary and are likely just left overs from prior
work.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Fri, 4 Dec 2015 22:26:32 +0000 (17:26 -0500)]
nv50/ir: fold shl + mul with immediates
On SM20 this gives:
total instructions in shared programs :
6299222 ->
6294240 (-0.08%)
total gprs used in shared programs : 944139 -> 944068 (-0.01%)
total local used in shared programs : 54116 -> 54116 (0.00%)
local gpr inst bytes
helped 0 126 2781 2781
hurt 0 55 11 11
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 20:21:11 +0000 (15:21 -0500)]
nv50/ir: propagate indirect loads into instructions
This way $r1 = $r0 + 4; c1[$r1] becomes c1[$r0+4].
On SM35:
total instructions in shared programs :
6206257 ->
6185058 (-0.34%)
total gprs used in shared programs : 911045 -> 910722 (-0.04%)
total local used in shared programs : 39072 -> 39072 (0.00%)
local gpr inst bytes
helped 0 417 4195 4195
hurt 0 280 0 0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 21:05:56 +0000 (16:05 -0500)]
nv50/ir: flip shl(add, imm) into add(shl, imm)
This works when the add also has an immediate. This often happens in
address calculations. These addresses can then be inlined as well.
On code targeted to SM35:
total instructions in shared programs :
6223346 ->
6206257 (-0.27%)
total gprs used in shared programs : 911075 -> 911045 (-0.00%)
total local used in shared programs : 39072 -> 39072 (0.00%)
local gpr inst bytes
helped 0 119 3664 3664
hurt 0 74 15 15
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Anholt [Fri, 4 Dec 2015 21:41:50 +0000 (13:41 -0800)]
vc4: Fix accidental scissoring when scissor is disabled.
Even if the rasterizer has scissor disabled, we'll have whatever
vc4->scissor bounds were last set when someone set up a scissor, so we
shouldn't clip to them in that case.
Fixes piglit fbo-blit-rect, and a lot of MSAA tests once they're enabled.
Eric Anholt [Fri, 4 Dec 2015 21:15:01 +0000 (13:15 -0800)]
vc4: Disable RCL blitting when scissors are enabled.
We could potentially handle scissored blits when they're tile aligned, but
it doesn't seem worth it. If you're doing a scissored blit, you're
probably a testcase.
Fixes piglit's fbo-scissor-blit fbo
Eric Anholt [Sat, 5 Dec 2015 20:25:25 +0000 (12:25 -0800)]
vc4: Bring over cleanups from submitting to the kernel.
Samuel Pitoiset [Wed, 2 Dec 2015 22:52:07 +0000 (23:52 +0100)]
nvc0: expose a group of performance metrics for SM30 (Kepler)
This allows to monitor these performance metrics through
GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:56:23 +0000 (16:56 +0100)]
nvc0: re-introduce performance metrics for SM30 (Kepler)
This implements more performance metrics than the previous support,
but some other metrics still need to be figured out.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:33:22 +0000 (16:33 +0100)]
nvc0: remove useless counting operations for MP counters
Those bits were related to old performance metrics support.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:30:20 +0000 (16:30 +0100)]
nvc0: remove old performance metrics support on Kepler
These performance metrics will be re-introduced in an upcoming
patch that will follow the same design as Fermi.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 28 Oct 2015 13:34:43 +0000 (14:34 +0100)]
nvc0: remove wrong inst_issued HW SM perf counter on Kepler
inst_issued is performance metric not a hardware event on Kepler (SM30).
It will be re-introduced in an upcoming patch.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Mon, 19 Oct 2015 21:01:07 +0000 (23:01 +0200)]
nvc0: add missing HW SM perf counters for SM30 (Kepler)
SM30 is the compute capability version for GK104/GK106/GK107.
This also introduces a new signal group selection called UNK0F.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 2 Dec 2015 15:19:50 +0000 (16:19 +0100)]
nvc0: fix the comment that describe MP counters storage on Kepler
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Rob Clark [Sat, 5 Dec 2015 13:46:40 +0000 (08:46 -0500)]
freedreno/ir3: nir shader prints with 'disasm' debug option
Move these to 'disasm' instead of the more verbose 'optmsgs' since, like
the tgsi dumps, it is useful without the more verbose compiler logging
enabled.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 4 Dec 2015 20:08:23 +0000 (15:08 -0500)]
gallium/util: fix pipe_debug_message macro to allow 0 args
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Eric Anholt [Sun, 9 Aug 2015 21:16:30 +0000 (14:16 -0700)]
vc4: Add debug dumping of MSAA surfaces.
Eric Anholt [Tue, 23 Jun 2015 00:41:08 +0000 (17:41 -0700)]
vc4: Add support for laying out MSAA resources.
For MSAA, we store full resolution tile buffer contents, which have their
own tiling format. Since they're full resolution buffers, we have to
align their size to full tiles.
Eric Anholt [Sat, 21 Nov 2015 01:18:03 +0000 (17:18 -0800)]
vc4: Add support for storing sample mask.
From the API perspective, writing 1 bits can't turn on pixels that were
off, so we AND it with the sample mask from the payload.
Eric Anholt [Sun, 22 Nov 2015 03:26:54 +0000 (19:26 -0800)]
vc4: Fix up tile alignment checks for blitting using just an RCL.
We were checking that the blit started at 0 and was 1:1, but not that it
went to the full width of the surface, or that the width was aligned to a
tile. We then told it to blit to the full width/height of the surface,
causing contents to be stomped in a bunch of MSAA tests that happen to
include half-screen-width blits to 0,0.
Eric Anholt [Sat, 21 Nov 2015 01:11:18 +0000 (17:11 -0800)]
vc4: Add support for loading sample mask.
Rob Clark [Mon, 30 Nov 2015 20:52:26 +0000 (15:52 -0500)]
freedreno/ir3: convert scheduler back to recursive algo
I've played with a few different approaches to tweak instruction
priority according to how much they increase/decrease register pressure,
etc. But nothing seems to change the fact that compared to original
(pre-multiple-block-support) scheduler, in some edge cases we are
generating shaders w/ 5-6x higher register usage.
The problem is that the priority queue approach completely looses the
dependency between instructions, and ends up scheduling all paths at the
same time.
Original reason for switching was that recursive approach relied on
starting from the shader outputs array. But we can achieve more or less
the same thing by starting from the depth-sorted list.
shader-db results:
total instructions in shared programs: 113350 -> 105183 (-7.21%)
total dwords in shared programs: 219328 -> 211168 (-3.72%)
total full registers used in shared programs: 7911 -> 7383 (-6.67%)
total half registers used in shader programs: 109 -> 109 (0.00%)
total const registers used in shared programs: 21294 -> 21294 (0.00%)
half full const instr dwords
helped 0 322 0 711 215
hurt 0 163 0 38 4
The shaders hurt tend to gain a register or two. While there are also a
lot of helped shaders that only loose a register or two, the more
complex ones tend to loose significanly more registers used. In some
more extreme cases, like glsl-fs-convolution-1.shader_test it is more
like 7 vs 34 registers!
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 3 Dec 2015 16:49:51 +0000 (11:49 -0500)]
freedreno/ir3: don't reuse a0.x across blocks
It causes confusion in sched if we need to split_addr() since otherwise
we wouldn't easily know which block the new addr instr will be scheduled
in. So just side-step the whole situation.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 3 Dec 2015 15:21:32 +0000 (10:21 -0500)]
freedreno/ir3: rename ir3_block::bd
We'll need to add similar for ir3_instruction, but following the pattern
to use 'id' seems confusing. Let's just go w/ generic 'data' as the
name.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Giuseppe Bilotta [Fri, 4 Dec 2015 14:03:24 +0000 (14:03 +0000)]
util: fix comment typo
Undefining the NDEBUG is relevant for release build, as they are the
ones that set it.
[Emil Velikov: split from previous patch]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Giuseppe Bilotta [Sun, 29 Nov 2015 17:19:35 +0000 (18:19 +0100)]
xvmc: force assertion in XvMC tests
This follows the src/util/u_atomic_test.c model of undefining NDEBUG
unconditionally throughouth the XvMC tests, to force asserts regardless
of debug mode.
The comment on u_atomic_test.c is also fixed (read 'debug' where it
should have been 'release').
v2: s/debug/release/ in relevant comments
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
[Emil Velikov: keep the src/util/ hunk as separate patch]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Giuseppe Bilotta [Sat, 28 Nov 2015 15:43:56 +0000 (16:43 +0100)]
radeon: const correctness
Add missing `const` specifier for pointer pointing to a const struct.
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Giuseppe Bilotta [Sat, 28 Nov 2015 15:43:55 +0000 (16:43 +0100)]
radeon: whitespace cleanup
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 3 Dec 2015 22:01:31 +0000 (22:01 +0000)]
mesa/tests: add KHR_debug GLES glGetPointervKHR entry points
Should have been part of commit
f53f9eb8d49 "glapi: add GetPointervKHR
to the ES dispatch".
v2: comment out the ES1.1 symbol and use the same description (pattern)
as elsewhere (Matt)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93235
Fixes:
f53f9eb8d49 "glapi: add GetPointervKHR to the ES dispatch".
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org> (v1)
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Jason Ekstrand [Thu, 26 Nov 2015 08:05:32 +0000 (00:05 -0800)]
i965/vec4: Stop pretending to support indirect output stores
Since we're using nir_lower_outputs_to_temporaries to shadow all our
outputs, it's impossible to actually get an indirect store. The code we
had to "handle" this was pretty bogus as it created a register with a
reladdr and then stuffed it in a fixed varying slot without so much as a
MOV. Not only does this not do the MOV, it also puts the indirect on the
wrong side of the transaction. Let's just delete the broken dead code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 25 Nov 2015 22:01:00 +0000 (14:01 -0800)]
i965/vec4: Get rid of the nir_inputs array
It's not really buying us anything at this point. It's just a way of
remapping one offset namespace onto another. We can just use the location
namespace the whole way through.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 25 Nov 2015 20:33:38 +0000 (12:33 -0800)]
nir/lower_io: Pass the builder and type_size into get_io_offset
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Fri, 4 Dec 2015 04:43:44 +0000 (23:43 -0500)]
nv50/ir: replace zeros in movs as well
The original change to put zeroes directly into instructions created
conditional mov's with the zero immediate. However that can't be
emitted, so make sure to replace the zero with r63.
Fixes:
52a800a68 (nv50/ir: allow immediate 0 to be loaded anywhere)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 3 Dec 2015 02:02:12 +0000 (21:02 -0500)]
nv50/ir: fold fma/mad when all 3 args are immediates
This happens pretty rarely, but might as well do it when it does.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 4 Dec 2015 03:37:22 +0000 (22:37 -0500)]
nv50/ir: avoid looking at uninitialized srcMods entries
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Thu, 3 Dec 2015 19:04:06 +0000 (14:04 -0500)]
nv50/ir: fix DCE to not generate 96-bit loads
A situation where there's a 128-bit load where the last component gets
DCE'd causes a 96-bit load to be generated, which no GPU can actually
emit. Avoid generating such instructions by scaling back to 64-bit on
the first load when splitting.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Roland Scheidegger [Fri, 4 Dec 2015 02:42:02 +0000 (03:42 +0100)]
draw: fix clipping of layer/vp index outputs
This was just plain broken. It used always the value from v0 (for vp_index)
but would pass the value from the provoking vertex to later stages - but only
if there was a corresponding fs input, otherwise the layer/vp index would get
lost completely (as it would try to interpolate the (unsigned) values as
floats).
So, make it obey provoking vertex rules (drivers relying on draw will need to
do the same). And make sure that the default interpolation mode (when no
corresponding fs input is found) for them is constant.
Also, change the code a bit so constant inputs aren't interpolated then
copied over later.
Fixes the new piglit test gl-layer-render-clipped.
v2: more consistent whitespaces fixes for function defs, and more tab killing
(overall still not quite right however).
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 3 Dec 2015 00:19:52 +0000 (01:19 +0100)]
softpipe: use provoking vertex for layer
Same as for llvmpipe, albeit softpipe only really handles multiple layers,
not multiple viewports/scissors.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 3 Dec 2015 00:18:14 +0000 (01:18 +0100)]
llvmpipe: use provoking vertex for layer/viewport
d3d10 actually requires using provoking (first) vertex. GL is happy with
any vertex (as long as we say it's undefined in the corresponding queries).
Up to now we actually used vertex 0 for viewport index, and vertex 1 for
layer (for tris), which really didn't make sense (probably a typo). Also,$
since we reorder vertices of clockwise triangle, that actually meant we used
a different vertex depending if the traingle was cw or ccw (still ok by gl).
However, it should be consistent with what draw (clip) does, and using
provoking vertex seems like the sensible choice (draw clip will be fixed
next as it is totally broken there).
While here, also use the correct viewport always even when not needed
in setup (we pass it down to jit fragment shader it might be needed there
for getting correct near/far depth values).
No piglit changes.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Sun, 22 Nov 2015 03:10:02 +0000 (19:10 -0800)]
vc4: Add the RCL to CL debug dumping when in simulator mode.
We can't dump it in the real driver, since the kernel doesn't give us a
handle to it (except after a GPU hang, using a root ioctl). In the
simulator we can.
Marek Olšák [Thu, 3 Dec 2015 22:50:00 +0000 (23:50 +0100)]
radeonsi: fix Fiji for LLVM <= 3.7
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Tue, 27 Oct 2015 22:10:51 +0000 (23:10 +0100)]
radeonsi: fix occlusion queries on Fiji
Tested.
Marek Olšák [Tue, 24 Nov 2015 22:00:00 +0000 (23:00 +0100)]
radeonsi: dump init_config IBs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 23 Nov 2015 12:30:23 +0000 (13:30 +0100)]
radeonsi: print framebuffer info into ddebug logs
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 23:02:53 +0000 (00:02 +0100)]
gallium/radeon: print more info about HTILE
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 21 Nov 2015 22:54:27 +0000 (23:54 +0100)]
gallium/radeon: print more info about CMASK
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>