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Jonas Devlieghere [Tue, 16 Jan 2018 11:17:57 +0000 (11:17 +0000)]
[DebugInfo] Unify dumping of address ranges
Summary:
This patch unifies the printing of address ranges as [0x0, 0x1).
rdar://
34822059
Reviewers: aprantl, dblaikie
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D42056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322543
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Francis Visoiu Mistrih [Tue, 16 Jan 2018 10:53:14 +0000 (10:53 +0000)]
[CodeGen] Remove special case of printing subRegIdx from MachineInstr::print
Support in MachineOperand has been added in r320209. No need to special
case this anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322542
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Francis Visoiu Mistrih [Tue, 16 Jan 2018 10:53:11 +0000 (10:53 +0000)]
[CodeGen][NFC] Correct case for printSubRegIdx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322541
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Clement Courbet [Tue, 16 Jan 2018 09:11:20 +0000 (09:11 +0000)]
Add a value_type to ArrayRef.
Summary: Not sure this needs a review or not. Erring on the safe side.
Reviewers: dblaikie
Differential Revision: https://reviews.llvm.org/D41666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322538
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Gadi Haber [Tue, 16 Jan 2018 08:50:29 +0000 (08:50 +0000)]
[X86][XSAVE]: Adding full coverage of MC encoding for the XSAVE isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the XSAVE ISA sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper
Differential Revision: https://reviews.llvm.org/D41282
Change-Id: I325bf8f421f78c80179a04fc39033366759cbe45
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322537
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George Rimar [Tue, 16 Jan 2018 08:09:24 +0000 (08:09 +0000)]
[FileCheck] - Fix possible buffer out of bounds access when parsing --check-prefix.
FileCheck tool crashes when trying to parse --check-prefix argument if there is no any
data after it.
For example test like following would crash if there are no symbols and no EOL mark after `boom`:
# REQUIRES: x86
# RUN: <skipped few lines>
# RUN: llvm-readobj -t %t | FileCheck %s --check-prefix=boom
Patch fixes the issue.
Differential revision: https://reviews.llvm.org/D42057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322536
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Yonghong Song [Tue, 16 Jan 2018 07:27:20 +0000 (07:27 +0000)]
[BPF] Mark pseudo insn patterns as isCodeGenOnly
These pseudos are not supposed to be visible to user.
This patch reduced the auto-generated instruction matcher. For example,
the following words are removed from keyword list of LLVM BPF assembler.
- MCK__35_, // '#'
- MCK__COLON_, // ':'
- MCK__63_, // '?'
- MCK_ADJCALLSTACKDOWN, // 'ADJCALLSTACKDOWN'
- MCK_ADJCALLSTACKUP, // 'ADJCALLSTACKUP'
- MCK_PSEUDO, // 'PSEUDO'
- MCK_Select, // 'Select'
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322535
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Yonghong Song [Tue, 16 Jan 2018 07:27:19 +0000 (07:27 +0000)]
[BPF] Teach DAG2DAG AND elimination about load intrinsics
As commented on the existing code:
// The Reg operand should be a virtual register, which is defined
// outside the current basic block. DAG combiner has done a pretty
// good job in removing truncating inside a single basic block.
However, when the Reg operand comes from bpf_load_[byte | half | word]
intrinsics, the generic optimizer doesn't understand their results are
zero extended, so these single basic block elimination opportunities were
missed.
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322534
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Hiroshi Inoue [Tue, 16 Jan 2018 06:23:05 +0000 (06:23 +0000)]
[SROA] fix assetion failure
This patch fixes the assertion failure in SROA reported in PR35657.
PR35657 reports the assertion failure due to r319522 (splitting for non-whole-alloca slices), but this problem can happen even without r319522.
The problem exists in a check for reusing an existing alloca when rewriting partitions. As the original comment said, we can reuse the existing alloca if the new alloca has the same type and offset with the existing one. But the code checks only type of the alloca and then check the offset using an assert.
In a corner case with out-of-bounds access (e.g. @PR35657 function added in unit test), it is possible that the two allocas have the same type but different offsets.
This patch makes the check of the offset in the if condition, and re-enables the splitting for non-whole-alloca slices.
Differential Revision: https://reviews.llvm.org/D41981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322533
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Craig Topper [Tue, 16 Jan 2018 06:07:16 +0000 (06:07 +0000)]
[X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode using the 0x90 encoding in 64-bit mode.
Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90.
This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322532
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Craig Topper [Tue, 16 Jan 2018 06:07:14 +0000 (06:07 +0000)]
[X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.
Previously we encoded it as 0x48 0x90.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322531
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Simon Pilgrim [Mon, 15 Jan 2018 22:40:06 +0000 (22:40 +0000)]
Avoid Wparentheses warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322526
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Simon Pilgrim [Mon, 15 Jan 2018 22:32:40 +0000 (22:32 +0000)]
[X86][MMX] Add support for MMX zero vector creation
As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register.
This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well.
Differential Revision: https://reviews.llvm.org/D41908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322525
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Simon Pilgrim [Mon, 15 Jan 2018 22:18:45 +0000 (22:18 +0000)]
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
Add support for custom execution domain fixing and implement support for BLENDPD/BLENDPS/PBLENDD/PBLENDW.
Differential Revision: https://reviews.llvm.org/D42042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322524
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Sanjay Patel [Mon, 15 Jan 2018 21:57:41 +0000 (21:57 +0000)]
[x86] add tests to show missed constant shrinking (PR35907); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322523
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Sanjay Patel [Mon, 15 Jan 2018 21:32:39 +0000 (21:32 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322522
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Sanjay Patel [Mon, 15 Jan 2018 21:28:52 +0000 (21:28 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322521
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Brian Gesiak [Mon, 15 Jan 2018 21:23:32 +0000 (21:23 +0000)]
[docs] Only LLVM IR bitstreams begin with 'BC'
Summary:
The LLVM Bitcode File Format documentation states that all bitstreams
begin with the magic number 'BC', and that generic bitstream analyzer
tools may check for this number in order to determine whether the
stream is a bitstream.
However, in practice:
* Only LLVM IR bitcode begins with 'BC'. Other bitstreams -- Clang
AST files and precompiled headers, Clang serialized diagnostics,
Swift modules -- do not start with 'BC'. A tool that actually checked
for 'BC' would only be able to recognize LLVM IR.
* The `llvm-bcanalyzer`, arguably the most used generic bitstream
analyzer tool, does not check for a magic number 'BC' (except to
determine whether the file is LLVM IR).
Update the bitcode format documentation to make it clear that not all
bitstreams begin with 'BC', and that tools should not rely on that
particular magic number value.
Test Plan:
Build the `docs-llvm-html` target and confirm the changes render in
a Safari web browser.
Reviewers: harlanhaskins, eugenis, mehdi_amini, pcc, angerman
Reviewed By: angerman
Subscribers: angerman, llvm-commits
Differential Revision: https://reviews.llvm.org/D42002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322520
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Sanjay Patel [Mon, 15 Jan 2018 21:22:46 +0000 (21:22 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322519
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Craig Topper [Mon, 15 Jan 2018 20:33:53 +0000 (20:33 +0000)]
[X86] Use MVT::getVectorVT instead of EVT::getVectorVT when splitting 256/512 bit build_vectors. NFC
We must be creating a legal type here which means it can be an MVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322512
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Craig Topper [Mon, 15 Jan 2018 20:33:52 +0000 (20:33 +0000)]
[X86] Generalize some code in LowerBUILD_VECTOR. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322511
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Craig Topper [Mon, 15 Jan 2018 20:33:50 +0000 (20:33 +0000)]
[X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCI
We were checking for 128, 256, or 512 bit vectors, but those are the only types that can get here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322510
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Dan Gohman [Mon, 15 Jan 2018 20:08:14 +0000 (20:08 +0000)]
[WebAssembly] Update README.txt.
Describe more of the current status, mention Rust as another easy
way to use this backend, and add more documentation links.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322508
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Stanislav Mekhanoshin [Mon, 15 Jan 2018 18:49:15 +0000 (18:49 +0000)]
[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
Differential Revision: https://reviews.llvm.org/D41617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322500
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Krzysztof Parzyszek [Mon, 15 Jan 2018 18:43:55 +0000 (18:43 +0000)]
[Hexagon] Implement signed and unsigned multiply-high for vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322499
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Krzysztof Parzyszek [Mon, 15 Jan 2018 18:33:33 +0000 (18:33 +0000)]
[Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors
The old implementation was not always correct. The new one recognizes
more shuffles that match specific instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322498
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Stanislav Mekhanoshin [Mon, 15 Jan 2018 17:55:35 +0000 (17:55 +0000)]
[AMDGPU] Copy impdefs from pseudo to real instructions
In some cases we do not copy implicit defs from pseudo to real
VOP instructions. It has no visible impact at the moment thus no
tests are affected or added.
Differential Revision: https://reviews.llvm.org/D41783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322496
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Simon Pilgrim [Mon, 15 Jan 2018 17:55:21 +0000 (17:55 +0000)]
[X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt pattern names. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322495
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Jan Korous [Mon, 15 Jan 2018 17:11:22 +0000 (17:11 +0000)]
[docs] Fix mention of GCC frontend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322491
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Dan Gohman [Mon, 15 Jan 2018 17:06:23 +0000 (17:06 +0000)]
[WebAssembly] Make WasmObjectWriter's destructor public; NFC
This fixes the FIXME introduced in r315327.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322490
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Jonas Paulsson [Mon, 15 Jan 2018 15:41:26 +0000 (15:41 +0000)]
[SystemZ] Check for legality before doing LOAD AND TEST transformations.
Since a load and test instruction treat its operands as signed, it can only
replace a logical compare for EQ/NE uses.
Review: Ulrich Weigand
https://bugs.llvm.org/show_bug.cgi?id=35662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322488
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Sam McCall [Mon, 15 Jan 2018 14:43:04 +0000 (14:43 +0000)]
Allow function_ref(nullptr) like std::function, since it's nullable already
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322487
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Clement Courbet [Mon, 15 Jan 2018 14:24:07 +0000 (14:24 +0000)]
[X86] Add missing predicates for VRNDSCALES{D,S}{m,r}
Summary: This is similar to https://reviews.llvm.org/D41983.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322486
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Andrew V. Tischenko [Mon, 15 Jan 2018 14:21:11 +0000 (14:21 +0000)]
Update BTVER2 sched numbers for some AVX instructions (xmm version).
Differential Revision: https://reviews.llvm.org/D40067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322485
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Clement Courbet [Mon, 15 Jan 2018 13:37:05 +0000 (13:37 +0000)]
[X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.
Summary:
Due to missing parentheses.
This is similar to https://reviews.llvm.org/D41983.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322483
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Sander de Smalen [Mon, 15 Jan 2018 12:47:17 +0000 (12:47 +0000)]
[AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions.
Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker
Reviewed By: fhahn, samparker
Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322481
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Clement Courbet [Mon, 15 Jan 2018 12:05:33 +0000 (12:05 +0000)]
[X86] Fix missing predicates HasAVX512 Predicates in avx512_sqrt_scalar.
Summary:
For example, VSQRTSDZr and VSQRTSSZr were missing the predicate.
Also fix braces indentation and braces for consistency.
Reviewers: craig.topper, RKSimon
Suscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322478
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Pavel Labath [Mon, 15 Jan 2018 11:03:30 +0000 (11:03 +0000)]
[Support] Remove MemoryBuffer::getNewMemBuffer
all callers have been switched the the Writable version (which does not
require const_casting to be useful).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322475
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Benjamin Kramer [Mon, 15 Jan 2018 10:57:24 +0000 (10:57 +0000)]
Revert "[DAG] Elide overlapping stores"
This reverts commit r322085. Internal PPC testing is still showing the
same symptoms as when this patch landed the last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322474
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Andrei Elovikov [Mon, 15 Jan 2018 10:56:07 +0000 (10:56 +0000)]
[LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV from a trunc.
Summary:
This method is supposed to be called for IVs that have casts in their use-def
chains that are completely ignored after vectorization under PSE. However, for
truncates of such IVs the same InductionDescriptor is used during
creation/widening of both original IV based on PHINode and new IV based on
TruncInst.
This leads to unintended second call to recordVectorLoopValueForInductionCast
with a VectorLoopVal set to the newly created IV for a trunc and causes an
assert due to attempt to store new information for already existing entry in the
map. This is wrong and should not be done.
Fixes PR35773.
Reviewers: dorit, Ayal, mssimpso
Reviewed By: dorit
Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D41913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322473
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Gadi Haber [Mon, 15 Jan 2018 09:39:08 +0000 (09:39 +0000)]
[X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 bits isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko
Differential Revision: https://reviews.llvm.org/D41172
Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322471
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Mikael Holmen [Mon, 15 Jan 2018 07:05:51 +0000 (07:05 +0000)]
[GlobalsAA] Don't let dbg intrinsics affect analysis result
Summary:
This fixes PR35899.
Debug info intrinsics shouldn't affect code generation so ignore them
in GlobalsAA.
Reviewers: hfinkel, aprantl
Reviewed By: aprantl
Subscribers: aprantl, llvm-commits
Differential Revision: https://reviews.llvm.org/D41984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322470
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Max Kazantsev [Mon, 15 Jan 2018 05:44:43 +0000 (05:44 +0000)]
[NFC] Fix comment to adjust to reality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322468
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Davide Italiano [Mon, 15 Jan 2018 01:40:18 +0000 (01:40 +0000)]
[BasicAA] Stop crashing when dealing with pointers > 64 bits.
An alternative (and probably better) fix would be that of
making `Scale` an APInt, and there's a patch floating around
to do this. As we're still discussing it, at least stop crashing
in the meanwhile (added bonus, we now have a regression test for
this situation).
Fixes PR35843.
Thanks to Eli for suggesting the fix and Simon for reporting and
reducing the bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322467
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Amara Emerson [Mon, 15 Jan 2018 00:44:20 +0000 (00:44 +0000)]
[GlobalISel][Legalizer] Convert some typedefs to using. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322466
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Simon Pilgrim [Sun, 14 Jan 2018 21:59:43 +0000 (21:59 +0000)]
[X86][SSE] Tag PR21137 test case
The test was added ages ago, but we didn't comment where it came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322465
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Craig Topper [Sun, 14 Jan 2018 20:53:49 +0000 (20:53 +0000)]
[X86] Add test cases for D41794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322464
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Simon Pilgrim [Sun, 14 Jan 2018 19:57:50 +0000 (19:57 +0000)]
[X86][SSE] Add PR22391 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322463
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Craig Topper [Sun, 14 Jan 2018 19:24:10 +0000 (19:24 +0000)]
[X86] Autoupgrade kunpck intrinsics using vector operations instead of scalar operations
Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free.
Reviewers: spatel, RKSimon, zvi, jina.nahias
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322462
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Simon Pilgrim [Sun, 14 Jan 2018 19:07:41 +0000 (19:07 +0000)]
[X86] Regenerate fp128 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322460
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Simon Pilgrim [Sun, 14 Jan 2018 18:50:34 +0000 (18:50 +0000)]
[X86][SSE] Support combining MOVLHPS undef inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322459
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 14 Jan 2018 18:38:21 +0000 (18:38 +0000)]
[X86][SSE] Add v2f64 3u shuffle test
Shows a missed opportunity to remove a unnecessary move compared to 31 shuffle mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322458
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Sanjay Patel [Sun, 14 Jan 2018 17:47:40 +0000 (17:47 +0000)]
[x86] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322457
91177308-0d34-0410-b5e6-
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Sanjay Patel [Sun, 14 Jan 2018 15:58:18 +0000 (15:58 +0000)]
[InstSimplify] fix code comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322456
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 14 Jan 2018 08:11:36 +0000 (08:11 +0000)]
[X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output types have the same number of elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322455
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 14 Jan 2018 08:11:33 +0000 (08:11 +0000)]
[X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.
We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements.
Ideally we'd just use ISD::TRUNCATE for these cases instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322454
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Craig Topper [Sun, 14 Jan 2018 02:05:51 +0000 (02:05 +0000)]
[X86] Improve legalization of vXi16/vXi8 selects.
Extend vXi1 conditions of vXi8/vXi16 selects even before type legalization gets a chance to split wide vectors. Previously we would only extend 128 and 256 bit vectors. But if we start with a 512 bit vector or wider that needs to be split we wouldn't extend until after the split had taken place. By extending early we improve the results of type legalization.
Don't widen condition of 128/256 bit vXi16/vXi8 selects when we have BWI but not VLX. We can still use a mask register by widening the select to 512-bits instead. This is similar to what we do for compares already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322450
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Craig Topper [Sun, 14 Jan 2018 02:05:49 +0000 (02:05 +0000)]
[X86] Add an avx512bw command line to the avx512-vec-cmp.ll test. Add some additional test cases.
Additional test cases cover selects with i16/i8 conditions that are only 128/256-bits wide, but the compares are 512-bits wide and can only produce k-registers. We should be able to artificially widen the selects to avoid moving the k-register to an xmm/ymm register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322449
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Zvi Rackover [Sat, 13 Jan 2018 17:42:19 +0000 (17:42 +0000)]
X86: Add pattern matching for PMADDWD
In addition to the existing match as part of a loop-reduction, add a
straightforward pattern match for DAG-contained patterns.
Reviewers: RKSimon, craig.topper
Subscribers: llvm-commits
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D41811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322446
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Simon Pilgrim [Sat, 13 Jan 2018 16:55:28 +0000 (16:55 +0000)]
[X86] Regenerate double shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322444
91177308-0d34-0410-b5e6-
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Sanjay Patel [Sat, 13 Jan 2018 15:44:44 +0000 (15:44 +0000)]
[InstSimplify] fold implied null ptr check (PR35790)
This extends rL322327 to handle the pointer cast and should solve:
https://bugs.llvm.org/show_bug.cgi?id=35790
Name: or_eq_zero
%isnull = icmp eq i64* %p, null
%x = ptrtoint i64* %p to i64
%somebits = and i64 %x, %y
%somebits_are_zero = icmp eq i64 %somebits, 0
%or = or i1 %somebits_are_zero, %isnull
=>
%or = %somebits_are_zero
Name: and_ne_zero
%isnotnull = icmp ne i64* %p, null
%x = ptrtoint i64* %p to i64
%somebits = and i64 %x, %y
%somebits_are_not_zero = icmp ne i64 %somebits, 0
%and = and i1 %somebits_are_not_zero, %isnotnull
=>
%and = %somebits_are_not_zero
https://rise4fun.com/Alive/CQ3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322439
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Simon Pilgrim [Sat, 13 Jan 2018 12:29:06 +0000 (12:29 +0000)]
[X86][MMX] Add test for MMX zero folding
As discussed in D41908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322436
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Zvi Rackover [Sat, 13 Jan 2018 08:21:29 +0000 (08:21 +0000)]
X86 Tests: add more pamddwd cases. NFC
Improve coverage of D41811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322434
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Craig Topper [Sat, 13 Jan 2018 06:24:46 +0000 (06:24 +0000)]
[X86] Add DAG combine to promote vXi1 result of a vXi8/vXi16 setcc when we have AVX512 but not BWI.
This avoids having the result type stick around until lowering where we have to extend the setcc and insert a truncate. If we get the types converted early we can do more to optimize it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322432
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Paul Robinson [Sat, 13 Jan 2018 01:39:30 +0000 (01:39 +0000)]
XFAIL a test on Darwin, line-table stuck on DWARF 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322430
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Evgeniy Stepanov [Sat, 13 Jan 2018 01:32:15 +0000 (01:32 +0000)]
[hwasan] An LLVM flag to disable stack tag randomization.
Summary: Necessary to achieve consistent test results.
Reviewers: kcc, alekseyshl
Subscribers: kubamracek, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D42023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322429
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Jessica Paquette [Sat, 13 Jan 2018 00:42:28 +0000 (00:42 +0000)]
[MachineOutliner] Move hasAddressTaken check to MachineOutliner.cpp
*Mostly* NFC. Still updating the test though just for completeness.
This moves the hasAddressTaken check to MachineOutliner.cpp and replaces it
with a per-basic block test rather than a per-function test. The old test was
too conservative and was preventing functions in C programs from being
outlined even though they were safe to outline.
This was mostly a problem in C sources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322425
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Tim Renouf [Fri, 12 Jan 2018 22:57:24 +0000 (22:57 +0000)]
[AMDGPU] stop image_store being moved illegally
Summary:
A recent change
321556: AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores
can allow the machine instruction scheduler to move an image store past
an image load using the same descriptor.
V2: Fixed by marking image ops as mayAlias and isAliased. This may be
overly conservative, and we may need to revisit.
V3: Reverted test change done on 321556.
Reviewers: arsenm, nhaehnle, dstuttard
Subscribers: llvm-commits, t-tye, yaxunl, wdng, kzhuravl
Differential Revision: https://reviews.llvm.org/D41969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322419
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Sanjay Patel [Fri, 12 Jan 2018 22:16:26 +0000 (22:16 +0000)]
[InstSimplify] add tests for implied ptr cmp with null (PR35790); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322411
91177308-0d34-0410-b5e6-
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Rui Ueyama [Fri, 12 Jan 2018 22:09:19 +0000 (22:09 +0000)]
Allow unaligned access to ELF file data structures.
The ELF specification says that all ELF data structures are aligned to
their natural alignments both in memory and file. That means when we
access mmap'ed ELF files, we could assume that all data structures are
aligned properly.
However, in reality, we assume that the data structures are aligned only
to two bytes because .a files only guarantee that their member files are
aligned to two bytes in archive files. So the data access is already
unaligned.
This patch relaxes the alignment requirement even more, so that we
accept unaligned access to all ELF data structures.
This patch in particular makes lld bug-compatible with icc. Intel C
compiler doesn't seem to care about data alignment and generates unaligned
relocation sections (https://bugs.llvm.org/show_bug.cgi?id=35854).
I also saw another instance of compatibility issues with our internal tool
which creates unaligned section headers.
Because GNU linkers are not picky about alignment, looks like it is
not uncommon that ELF-generating tools create unaligned files.
There is a performance penalty with this patch on host machines on which
unaligned access is expensive. x86 and AArch64 are fine. ARMv6 is a
problem, but I don't think using ARMv6 machines as hosts is common, so I
believe it's not a real problem.
Differential Revision: https://reviews.llvm.org/D41978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322407
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Zachary Turner [Fri, 12 Jan 2018 21:42:39 +0000 (21:42 +0000)]
Update MSF File Documentation.
This adds some more detail about the PDB container format,
specifically surrounding the layout of the Free Page Map.
Patch by Colden Cullen
Differential Revision: https://reviews.llvm.org/D41825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322404
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Daniel Neilson [Fri, 12 Jan 2018 21:33:37 +0000 (21:33 +0000)]
[NFC] Change MemIntrinsicInst::setAlignment() to take an unsigned instead of a Constant
Summary:
In preparation for https://reviews.llvm.org/D41675 this NFC changes this
prototype of MemIntrinsicInst::setAlignment() to accept an unsigned instead
of a Constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322403
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Changpeng Fang [Fri, 12 Jan 2018 21:12:19 +0000 (21:12 +0000)]
AMDGPU/SI: Add d16 support for buffer intrinsics.
Differential Revision:
https://reviews.llvm.org/D38906
Reviewers:
Matt and Brian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322402
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Brian M. Rzycki [Fri, 12 Jan 2018 21:06:48 +0000 (21:06 +0000)]
[JumpThreading] Preservation of DT and LVI across the pass
Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.
Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.
LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perform the
preversation was minimally altered and simply marked as
preserved for the PassManager to be informed.
This extends the analysis available to JumpThreading for
future enhancements such as threading across loop headers.
Reviewers: dberlin, kuhar, sebpop
Reviewed By: kuhar, sebpop
Subscribers: mgorny, dmgreen, kuba, rnk, rsmith, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322401
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Paul Robinson [Fri, 12 Jan 2018 20:54:45 +0000 (20:54 +0000)]
Try to fix more bots after r322391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322400
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Florian Hahn [Fri, 12 Jan 2018 20:35:45 +0000 (20:35 +0000)]
Silence GCC 7 warning by using an enum class.
This silences the following GCC7 warning:
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp:142:30: warning:
enumeral and non-enumeral type in conditional expression [-Wextra]
return F != Colors.end() ? F->second : None;
~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~
Reviewers: amharc, RKSimon, davide
Reviewed By: RKSimon, davide
Differential Revision: https://reviews.llvm.org/D41003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322398
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Max Moroz [Fri, 12 Jan 2018 20:31:32 +0000 (20:31 +0000)]
[llvm-cov] Skip unnecessary coverage computations for "export -summary-only".
Summary:
This speeds up export "summary-only" execution by an order of magnitude or two,
depending on number of threads used for prepareFileReports execution.
Also includes minor refactoring for splitting render of summary and detailed data
in two independent methods.
Reviewers: vsk, morehouse
Reviewed By: vsk
Subscribers: llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D42000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322397
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Rui Ueyama [Fri, 12 Jan 2018 19:59:43 +0000 (19:59 +0000)]
Remove ELFDataTypeTypedefHelper class.
Differential Revision: https://reviews.llvm.org/D41973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322395
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Paul Robinson [Fri, 12 Jan 2018 19:58:35 +0000 (19:58 +0000)]
Add toothpicks to test from r322391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322394
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Evandro Menezes [Fri, 12 Jan 2018 19:20:11 +0000 (19:20 +0000)]
[AArch64] Fix scheduling resources for post indexed loads and stores
Fix typos in the default scheduling resources when using the post indexed
addressing modes.
Differential revision: https://reviews.llvm.org/D40511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322392
91177308-0d34-0410-b5e6-
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Paul Robinson [Fri, 12 Jan 2018 19:17:50 +0000 (19:17 +0000)]
[DWARFv5] CodeGen support for MD5 file checksums
Pass MD5 checksums through from IR to assembly/object files.
After this, getting Clang to compute the MD5 should be the last step
to supporting MD5 in the DWARF v5 line table header.
Differential Revision: https://reviews.llvm.org/D41926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322391
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Sam Clegg [Fri, 12 Jan 2018 18:05:40 +0000 (18:05 +0000)]
MC: Remove redundant `SetUsed` arguments in MCSymbol methods
We can probably take this a step further since the only
user of the isUsed flag is AsmParser it should probably
be doing this explicitly. For now this is a step in the
right direction though.
Differential Revision: https://reviews.llvm.org/D41971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322386
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 12 Jan 2018 18:05:29 +0000 (18:05 +0000)]
[X86][SSE] Force blend domains on stack folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322385
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 12 Jan 2018 18:02:52 +0000 (18:02 +0000)]
[X86][AVX] Regenerate element insertion tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322384
91177308-0d34-0410-b5e6-
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Craig Topper [Fri, 12 Jan 2018 17:34:09 +0000 (17:34 +0000)]
[X86] Remove unused isel pattern for zero extend from v16i1/v8i1 to v16i32/v8i64.
We have custom lowering on vzext that produces a vselect and a build vector. So zext never gets to isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322381
91177308-0d34-0410-b5e6-
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Rafael Espindola [Fri, 12 Jan 2018 17:03:43 +0000 (17:03 +0000)]
Allow dso_local on ifunc.
It was never fully disallowed. We were rejecting it in the asm parser,
but not in the verifier.
Currently TargetMachine::shouldAssumeDSOLocal returns true for hidden
ifuncs. I considered changing it and moving the check from the asm
parser to the verifier.
The reason for deciding to allow it instead is that all linkers handle
a direct reference just fine. They use the plt address as the address
of the function. In fact doing that means that clang doesn't have the
same bug as gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83782.
This patch then removes the check from the asm parser and updates the
bitcode reader and writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322378
91177308-0d34-0410-b5e6-
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Ben Hamilton [Fri, 12 Jan 2018 15:44:35 +0000 (15:44 +0000)]
[docs] Tweak update to Phabricator docs about setting repository for diffs uploaded via web
Summary:
In D41919, I missed that there was a *second* step when uploading
diffs via web where the repository should be specified.
Reviewers: asb, probinson
Reviewed By: asb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322375
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Ben Hamilton [Fri, 12 Jan 2018 15:37:41 +0000 (15:37 +0000)]
[llvm] Set up .arcconfig to point to Diffusion L repository
Summary:
Thanks to probinson for noticing this in his review of D41956.
Now that we have repository callsigns set in all the other
LLVM/Clang projects' .arcconfig files, we can set the top-level
LLVM .arcconfig repository callsign to "L".
This will correctly Cc: llvm-commits@ on all review requests
sent out from the LLVM repo directory, using Herald rule H270.
Reviewers: klimek, sammccall
Reviewed By: sammccall
Subscribers: llvm-commits, probinson, asb
Differential Revision: https://reviews.llvm.org/D41964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322374
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Benjamin Kramer [Fri, 12 Jan 2018 15:03:24 +0000 (15:03 +0000)]
[PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate
I'm not even sure if this transform is ever worth it, but this at least
stops the bleeding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322373
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Fri, 12 Jan 2018 14:58:41 +0000 (14:58 +0000)]
[PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP
Part of the fix for https://bugs.llvm.org/show_bug.cgi?id=35812.
This patch ensures that the compare operand for the atomic compare and swap
is properly zero-extended to 32 bits if applicable.
A follow-up commit will fix the extension for the SETCC node generated when
expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS. That will complete the bug fix.
Differential Revision: https://reviews.llvm.org/D41856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322372
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Stefan Pintilie [Fri, 12 Jan 2018 13:12:49 +0000 (13:12 +0000)]
Revert "[PowerPC] Manually schedule the prologue and epilogue"
This reverts commit r322124 since some tests were broken by that patch.
Will recommmit once the patch is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322369
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Diana Picus [Fri, 12 Jan 2018 12:44:36 +0000 (12:44 +0000)]
[ARM GlobalISel] Add inst selector tests for G_FMA
We don't yet match all the patterns involving G_FMA. Add tests for some
of the ones that we do match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322368
91177308-0d34-0410-b5e6-
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Diana Picus [Fri, 12 Jan 2018 12:06:01 +0000 (12:06 +0000)]
[ARM GlobalISel] Map G_FMA to FPR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322367
91177308-0d34-0410-b5e6-
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Diana Picus [Fri, 12 Jan 2018 11:30:45 +0000 (11:30 +0000)]
[ARM GlobalISel] Legalize G_FMA
For hard float with VFP4, it is legal. Otherwise, we use libcalls.
This needs a bit of support in the LegalizerHelper for soft float
because we didn't handle G_FMA libcalls yet. The support is trivial, as
the only difference between G_FMA and other libcalls that we already
handle is that it has 3 input operands rather than just 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322366
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Max Kazantsev [Fri, 12 Jan 2018 10:00:26 +0000 (10:00 +0000)]
[IRCE][NFC] Make range check's End a non-null SCEV
Currently, IRC contains `Begin` and `Step` as SCEVs and `End` as value.
Aside from that, `End` can also be `nullptr` which can be later conditionally
converted into a non-null SCEV.
To make this logic more transparent, this patch makes `End` a SCEV and
calculates it early, so that it is never a null.
Differential Revision: https://reviews.llvm.org/D39590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322364
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Andre Vieira [Fri, 12 Jan 2018 09:24:41 +0000 (09:24 +0000)]
[ARM] Add codegen for SMMULR, SMMLAR and SMMLSR
This patch teaches the Arm back-end to generate the SMMULR, SMMLAR and SMMLSR
instructions from equivalent IR patterns.
Differential Revision: https://reviews.llvm.org/D41775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322361
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Andre Vieira [Fri, 12 Jan 2018 09:21:09 +0000 (09:21 +0000)]
[ARM] Fix erroneous availability of SMMLS for Armv7-M
Differential Revision: https://reviews.llvm.org/D41855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322360
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Serguei Katkov [Fri, 12 Jan 2018 08:33:34 +0000 (08:33 +0000)]
[CGP] Re-enable Select in complex addressing mode
Re-enable Select after a couple of fixes.
Differential Revision: https://reviews.llvm.org/D40634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322358
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Serguei Katkov [Fri, 12 Jan 2018 07:24:43 +0000 (07:24 +0000)]
[LoopDeletion] Handle users in unreachable block
This is a fix for PR35884.
When we want to delete dead loop we must clean uses in unreachable blocks
otherwise we'll get an assert during deletion of instructions from the loop.
Reviewers: anna, davide
Reviewed By: anna
Subscribers: llvm-commits, lebedev.ri
Differential Revision: https://reviews.llvm.org/D41943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322357
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 12 Jan 2018 06:48:26 +0000 (06:48 +0000)]
[X86] Don't allow lods/stos/scas/cmps/movs to be parsed without a suffix and only memory operand in at&t syntax.
Without a register with a size being mentioned the instruction is ambiguous in at&t syntax. With Intel syntax the memory operation caries a size that can be used to disambiguate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322356
91177308-0d34-0410-b5e6-
96231b3b80d8