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Michael Zuckerman [Thu, 18 Feb 2016 09:52:12 +0000 (09:52 +0000)]
[AVX512][PRORQ][PRORD] Change imm8 to int
Differential Revision: http://reviews.llvm.org/D17024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261198
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Chandler Carruth [Thu, 18 Feb 2016 09:45:17 +0000 (09:45 +0000)]
[PM/AA] Teach the new pass manager to use pass-by-lambda for registering
analysis passes, support pre-registering analyses, and use that to
implement parsing and pre-registering a custom alias analysis pipeline.
With this its possible to configure the particular alias analysis
pipeline used by the AAManager from the commandline of opt. I've updated
the test to show this effectively in use to build a pipeline including
basic-aa as part of it.
My big question for reviewers are around the APIs that are used to
expose this functionality. Are folks happy with pass-by-lambda to do
pass registration? Are folks happy with pre-registering analyses as
a way to inject customized instances of an analysis while still using
the registry for the general case?
Other thoughts of course welcome. The next round of patches will be to
add the rest of the alias analyses into the new pass manager and wire
them up here so that they can be used from opt. This will require
extending the (somewhate limited) functionality of AAManager w.r.t.
module passes.
Differential Revision: http://reviews.llvm.org/D17259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261197
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NAKAMURA Takumi [Thu, 18 Feb 2016 07:37:17 +0000 (07:37 +0000)]
Make a stub version of MITests, instead of reverting.
Lit tends to find out-of-date unittests in the build tree.
FIXME: It may be reverted several days after.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261194
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Dan Gohman [Thu, 18 Feb 2016 06:32:53 +0000 (06:32 +0000)]
[WebAssembly] Don't use setRequiresStructuredCFG(true).
While we still do want reducible control flow, the RequiresStructuredCFG
flag imposes more strict structure constraints than WebAssembly wants.
Unsetting this flag enables critical edge splitting and tail merging.
Also, disable TailDuplication explicitly, as it doesn't support virtual
registers, and was previously only disabled by the RequiresStructuredCFG
flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261190
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Matthias Braun [Thu, 18 Feb 2016 05:21:43 +0000 (05:21 +0000)]
Revert "LiveIntervalAnalysis: Remove LiveVariables requirement" and LiveIntervalTest
The commit breaks stage2 compilation on PowerPC. Reverting for now while
this is analyzed. I also have to revert the LiveIntervalTest for now as
that depends on this commit.
Revert "LiveIntervalAnalysis: Remove LiveVariables requirement"
This reverts commit r260806.
Revert "Remove an unnecessary std::move to fix -Wpessimizing-move warning."
This reverts commit r260931.
Revert "Fix typo in LiveIntervalTest"
This reverts commit r260907.
Revert "Add unittest for LiveIntervalAnalysis::handleMove()"
This reverts commit r260905.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261189
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Craig Topper [Thu, 18 Feb 2016 04:54:32 +0000 (04:54 +0000)]
[TableGen,X86] Add NDEBUG check to a variable initialization that's only used by asserts. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261188
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Craig Topper [Thu, 18 Feb 2016 04:54:29 +0000 (04:54 +0000)]
[TableGen,X86] Remove extra optional operand from RawFrm. RawFrm with 2 immediates is handled by RawFrmImm8/RawFrmImm16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261187
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Tom Stellard [Thu, 18 Feb 2016 03:42:32 +0000 (03:42 +0000)]
[AMDGPU] Disassembler: Added basic disassembler for AMDGPU target
Changes:
- Added disassembler project
- Fixed all decoding conflicts in .td files
- Added DecoderMethod=“NONE” option to Target.td that allows to
disable decoder generation for an instruction.
- Created decoding functions for VS_32 and VReg_32 register classes.
- Added stubs for decoding all register classes.
- Added several tests for disassembler
Disassembler only supports:
- VI subtarget
- VOP1 instruction encoding
- 32-bit register operands and inline constants
[Valery]
One of the point that requires to pay attention to is how decoder
conflicts were resolved:
- Groups of target instructions were separated by using different
DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate
approach.
- There were conflicts in IMAGE_<> instructions caused by two
different reasons:
1. dmask wasn’t specified for the output (fixed)
2. There are image instructions that differ only by the number of
the address components but have the same encoding by the HW spec. The
actual number of address components is determined by the HW at runtime
using image resource descriptor starting from the VGPR encoded in an
IMAGE instruction. This means that we should choose only one instruction
from conflicting group to be the rule for decoder. I didn’t find the way
to disable decoder generation for an arbitrary instruction and therefore
made a onelinear fix to tablegen generator that would suppress decoder
generation when DecoderMethod is set to “NONE”. This is a change that
should be reviewed and submitted first. Otherwise I would need to
specify different DecoderNamespace for every instruction in the
conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not
used in other targets.
3. IMAGE_GATHER decoder generation is for now disabled and to be
done later.
[/Valery]
Patch By: Sam Kolton
Differential Revision: http://reviews.llvm.org/D16723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261185
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Kostya Serebryany [Thu, 18 Feb 2016 02:02:40 +0000 (02:02 +0000)]
[libFuzzer] fix the libFuzzer bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261184
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Amaury Sechet [Wed, 17 Feb 2016 23:55:59 +0000 (23:55 +0000)]
Add upport for bitcast in the C API echo test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261177
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Derek Schuff [Wed, 17 Feb 2016 23:20:43 +0000 (23:20 +0000)]
[WebAssembly] Disable register stackification and coloring when not optimizing
These passes are optimizations, and should be disabled when not
optimizing.
Also create an MCCodeGenInfo so the opt level is correctly plumbed to
the backend pass manager.
Also remove the command line flag for disabling register coloring;
running llc with -O0 should now be useful for debugging, so it's not
necessary.
Differential Revision: http://reviews.llvm.org/D17327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261176
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Tim Northover [Wed, 17 Feb 2016 23:07:04 +0000 (23:07 +0000)]
AArch64: always clear kill flags up to last eliminated copy
After r261154, we were only clearing flags if the known-zero register was
originally live-in to the basic block, but we have to do it even if not when
more than one COPY has been eliminated, otherwise the user of the first COPY
may still have <kill> marked.
E.g.
BB#N:
%X0 = COPY %XZR
STRXui %X0<kill>, <fi#0>
%X0 = COPY %XZR
STRXui %X0<kill>, <fi#1>
We can eliminate both copies, X0 is not live-in, but we must clear the kill on
the first store.
Unfortunately, I've been unable to come up with a non-fragile test for this.
I've only seen it in the wild with regalloc-created spills, and attempts to
reproduce that in a reasonable way run afoul of COPY coalescing. Even volatile
asm clobbers were moved around. Should fix the aarch64 bot though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261175
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Amaury Sechet [Wed, 17 Feb 2016 22:51:03 +0000 (22:51 +0000)]
Add support for memory operations (load/store/gep) in C API echo test
Summary: As per title.
Reviewers: bogner, chandlerc, echristo, dblaikie, joker.eph, Wallbraker
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261174
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Zachary Turner [Wed, 17 Feb 2016 22:46:33 +0000 (22:46 +0000)]
[DebugInfoPDB] A few cleanups on PDB Variant class.
Also implements the PDBSymbolCompilandEnv::getValue() method,
which until now had been unimplemented specifically because
variant did not support string values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261173
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Amaury Sechet [Wed, 17 Feb 2016 22:41:09 +0000 (22:41 +0000)]
Move LLVMCreateTargetData and LLVMDisposeTargetData together. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261172
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Michael J. Spencer [Wed, 17 Feb 2016 22:30:41 +0000 (22:30 +0000)]
[readobj] Remove uneeded braces in case statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261170
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Amaury Sechet [Wed, 17 Feb 2016 22:30:05 +0000 (22:30 +0000)]
Make sure functions are generated even there is no global in the C API echo test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261169
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Adrian Prantl [Wed, 17 Feb 2016 22:20:08 +0000 (22:20 +0000)]
DwarfDebug: Don't drop the DIExpression just because a variable is
described by an immediate.
Found via http://reviews.llvm.org/D16867
Thanks to Paul Robinson for pointing this out.
<rdar://problem/
24456528>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261168
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Adrian Prantl [Wed, 17 Feb 2016 22:19:59 +0000 (22:19 +0000)]
DbgVariable: Add an accessor for the common case of a single expression
belonging to a single DBG_VALUE instruction.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261167
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Amaury Sechet [Wed, 17 Feb 2016 22:13:33 +0000 (22:13 +0000)]
Add support for global variables in the C API echo test
Summary: As per title
Reviewers: bogner, chandlerc, echristo, dblaikie, joker.eph, Wallbraker
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261164
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Kostya Serebryany [Wed, 17 Feb 2016 21:34:43 +0000 (21:34 +0000)]
[sanitizer-coverage] implement -fsanitize-coverage=trace-pc. This is similar to trace-bb, but has a different API. We already use the equivalent flag in GCC for Linux kernel fuzzing. We may be able to use this flag with AFL too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261159
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Amaury Sechet [Wed, 17 Feb 2016 21:21:29 +0000 (21:21 +0000)]
NFC: Fix formating
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261156
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Tim Northover [Wed, 17 Feb 2016 21:16:59 +0000 (21:16 +0000)]
Fix warning on build without asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261155
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Tim Northover [Wed, 17 Feb 2016 21:16:53 +0000 (21:16 +0000)]
AArch64: improve redundant copy elimination.
Mostly, this fixes the bug that if the CBZ guaranteed Xn but Wn was used, we
didn't sort out the use-def chain properly.
I've also made it check more than just the last instruction for a compatible
CBZ (so it can cope without fallthroughs). I'd have liked to do that
separately, but it's helps writing the test.
Finally, I removed some custom loops in favour of MachineInstr helpers and
refactored the control flow to flatten it and avoid possibly quadratic
iterations in blocks with many copies. NFC for these, just a general tidy-up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261154
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Zachary Turner [Wed, 17 Feb 2016 21:13:34 +0000 (21:13 +0000)]
[DebugInfoPDB] Raise getSymIndexId() up to PDBSymbol
Every symbol, no matter what it's tag is, supports the method
getSymIndexId(). However, this was being forwarded on every
concrete symbol type, so if someone had a PDBSymbol that they
didn't know what type it was (or simply didn't have an instance
of the concrete symbol type), they would not be able to get its
index id. This patch moves the method up to PDBSymbol, so that
no matter what type of object you have, you can always get its
id.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261153
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Zachary Turner [Wed, 17 Feb 2016 21:13:15 +0000 (21:13 +0000)]
[DebugInfoPDB] Teach Variant to support string types.
The IDiaSymbol::getValue() method returns a variant. Until now,
I had never encountered a string value, so the Variant wrapper
did not support VT_BSTR. Now we have need to support string
values, so this patch just adds support for one extra type to
Variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261152
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Haicheng Wu [Wed, 17 Feb 2016 21:00:06 +0000 (21:00 +0000)]
[LIR] Avoid turning non-temporal stores into memset
This is to fix PR26645.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261149
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Adrian Prantl [Wed, 17 Feb 2016 20:02:25 +0000 (20:02 +0000)]
Debug Info: Teach LdStHasDebugValue() (Local.cpp) about DIExpressions.
This function is used to check whether a dbg.value intrinsic has already
been inserted, but without comparing the DIExpression, it would erroneously
fire on split aggregates and only the first scalar would survive.
Found via http://reviews.llvm.org/D16867.
<rdar://problem/
24456528>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261145
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George Burgess IV [Wed, 17 Feb 2016 19:59:32 +0000 (19:59 +0000)]
Add static/const qualifiers to methods. NFC.
Split out this change as requested in D14933.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261144
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Kostya Serebryany [Wed, 17 Feb 2016 19:42:34 +0000 (19:42 +0000)]
[libFuzzer] don't timeout when loading the corpus. Be a bit more verbose when loading large corpus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261143
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Akira Hatanaka [Wed, 17 Feb 2016 19:35:47 +0000 (19:35 +0000)]
Mention 'notail' attribute in 3.9 release notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261141
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Elena Demikhovsky [Wed, 17 Feb 2016 19:23:04 +0000 (19:23 +0000)]
Create masked gather and scatter intrinsics in Loop Vectorizer.
Loop vectorizer now knows to vectorize GEP and create masked gather and scatter intrinsics for random memory access.
The feature is enabled on AVX-512 target.
Differential Revision: http://reviews.llvm.org/D15690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261140
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Amaury Sechet [Wed, 17 Feb 2016 19:21:28 +0000 (19:21 +0000)]
Fix load alignement when unpacking aggregates structs
Summary: Store and loads unpacked by instcombine do not always have the right alignement. This explicitely compute the alignement and set it.
Reviewers: dblaikie, majnemer, reames, hfinkel, joker.eph
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261139
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David Majnemer [Wed, 17 Feb 2016 19:02:36 +0000 (19:02 +0000)]
Revert "Reapply commit r258404 with fix."
This reverts commit r259357, it caused PR26629.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261137
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Frederic Riss [Wed, 17 Feb 2016 18:51:27 +0000 (18:51 +0000)]
[ObjCARC] Handle ARCInstKind::ClaimRV in OptimizeIndividualCalls.
When support for objc_unsafeClaimAutoreleasedReturnValue has been added to the
ARC optimizer in r258970, one case was missed which would lead the optimizer
to execute an llvm_unreachable. In this case, just handle ClaimRV in the same
way we handle RetainRV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261134
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Colin LeMahieu [Wed, 17 Feb 2016 18:50:21 +0000 (18:50 +0000)]
[Hexagon] Replacing reference/dereference with reference cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261133
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Nico Weber [Wed, 17 Feb 2016 18:48:08 +0000 (18:48 +0000)]
Remove superfluous semicolon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261128
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Nico Weber [Wed, 17 Feb 2016 18:47:29 +0000 (18:47 +0000)]
Revert r261070, it caused PR26652 / PR26653.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261127
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David Majnemer [Wed, 17 Feb 2016 18:37:11 +0000 (18:37 +0000)]
[WinEH] Optimize WinEH state stores
32-bit x86 Windows targets use a linked-list of nodes allocated on the
stack, referenced to via thread-local storage. The personality routine
interprets one of the fields in the node as a 'state number' which
indicates where the personality routine should transfer control.
State transitions are possible only before call-sites which may throw
exceptions. Our previous scheme had us update the state number before
all call-sites which may throw.
Instead, we can try to minimize the number of times we need to store by
reasoning about the nearest store which dominates the current call-site.
If the last store agrees with the current call-site, then we know that
the state-update is redundant and can be elided.
This is largely straightforward: an RPO walk of the blocks allows us to
correctly forward propagate the information when the function is a DAG.
Currently, loops are not handled optimally and may trigger superfluous
state stores.
Differential Revision: http://reviews.llvm.org/D16763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261122
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Easwaran Raman [Wed, 17 Feb 2016 18:18:47 +0000 (18:18 +0000)]
Add a profile summary class specific to instrumentation profiles.
Modify ProfileSummary class to make it not instrumented profile specific.
Add a new InstrumentedProfileSummary class that inherits from ProfileSummary.
Differential Revision: http://reviews.llvm.org/D17310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261119
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Colin LeMahieu [Wed, 17 Feb 2016 18:14:05 +0000 (18:14 +0000)]
[Hexagon] Loop instructions don't need special processing. Extension and fitting is performed by generic code and the comment is incorrect, loops don't have a separate extended opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261118
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Justin Lebar [Wed, 17 Feb 2016 17:46:54 +0000 (17:46 +0000)]
[NVPTX] Annotate convergent intrinsics as convergent.
Summary:
Previously the machine instructions for bar.sync &co. were not marked as
convergent. This resulted in some MI passes (such as TailDuplication,
fixed in an upcoming patch) doing unsafe things to these instructions.
Reviewers: jingyue
Subscribers: llvm-commits, tra, jholewinski, hfinkel
Differential Revision: http://reviews.llvm.org/D17318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261115
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Justin Lebar [Wed, 17 Feb 2016 17:46:52 +0000 (17:46 +0000)]
[NVPTX] Test that MachineSink won't sink across llvm.cuda.syncthreads.
Summary:
The syncthreads MI is modeled as mayread/maywrite -- convergence doesn't
even come into play here. Nonetheless this property is highly implicit
in the tablegen files, so a test seems appropriate.
Reviewers: jingyue
Subscribers: llvm-commits, jholewinski
Differential Revision: http://reviews.llvm.org/D17319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261114
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Justin Lebar [Wed, 17 Feb 2016 17:46:50 +0000 (17:46 +0000)]
[NVPTX] Annotate call machine instructions as calls.
Summary:
Otherwise we'll try to do unsafe optimizations on these MIs, such as
sinking loads below calls.
(I suspect that this is not the only bug in the NVPTX instruction
tablegen files; I need to comb through them.)
Reviewers: jholewinski, tra
Subscribers: jingyue, jhen, llvm-commits
Differential Revision: http://reviews.llvm.org/D17315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261113
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Justin Lebar [Wed, 17 Feb 2016 17:46:47 +0000 (17:46 +0000)]
[IR] Add {is,set,setNot}Convergent() functions to CallSite, CallInstr, and InvokeInstr.
Summary:
(CallSite already has isConvergent() and setConvergent().)
No functional changes.
Reviewers: reames
Subscribers: llvm-commits, jingyue, arsenm
Differential Revision: http://reviews.llvm.org/D17316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261112
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Justin Lebar [Wed, 17 Feb 2016 17:46:41 +0000 (17:46 +0000)]
Update langref to indicate that calls may be convergent.
Summary:
As previously written, only functions could be convergent. But calls
need to have a notion of convergence as well.
To see why this is important, consider an indirect call. We may or may
not want to disable optimizations around it and behave as though we're
calling a convergent function -- it depends on the semantics of the
language we're compiling. Thus the need for this attr on the call.
Reviewers: jingyue, joker.eph
Subscribers: llvm-commits, tra, jhen, arsenm, chandlerc, hfinkel, resistor
Differential Revision: http://reviews.llvm.org/D17314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261111
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Justin Lebar [Wed, 17 Feb 2016 17:46:39 +0000 (17:46 +0000)]
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261110
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Rafael Espindola [Wed, 17 Feb 2016 16:48:00 +0000 (16:48 +0000)]
Represent the dynamic table itself with a DynRegionInfo.
The dynamic table is also an array of a fixed structure, so it can be
represented with a DynReginoInfo.
No major functionality change. The extra error checking is covered by
existing tests with a broken dynamic program header.
Idea extracted from r260488. I did the extra cleanups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261107
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Mitch Bodart [Wed, 17 Feb 2016 16:35:18 +0000 (16:35 +0000)]
Fix some erroneous lit test failures due to unlucky name of working directory.
Differential Revision: http://reviews.llvm.org/D17044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261104
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Rafael Espindola [Wed, 17 Feb 2016 16:21:49 +0000 (16:21 +0000)]
Add a unwrapOrError utility and use it to simplify ELFDumper.cpp.
Utility extracted from r260488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261103
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Simon Pilgrim [Wed, 17 Feb 2016 15:52:39 +0000 (15:52 +0000)]
[X86][SSE] Update pshufb mask tests.
We are getting better at combining constant pshufb masks - use a real input instead of undef.
Add test for decoding multi-use bitcasted masks as well (actual support will come soon).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261101
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Rafael Espindola [Wed, 17 Feb 2016 15:38:21 +0000 (15:38 +0000)]
Change how readobj stores info about dynamic symbols.
We used to keep both a section and a pointer to the first symbol.
The oddity of keeping a section for dynamic symbols is because there is
a DT_SYMTAB but no DT_SYMTABZ, so to print the table we have to find the
size via a section table.
The reason for still keeping a pointer to the first symbol is because we
want to be able to print relocation tables even if the section table is
missing (it is mandatory only for files used in linking).
With this patch we keep just a DynRegionInfo. This then requires
changing a few places that were asking for a Elf_Shdr but actually just
needed the first symbol.
The test change is to delete the program header pointer.
Now that we use the information of both DT_SYMTAB and .dynsym, we don't
depend on the sh_entsize of .dynsym if we see DT_SYMTAB.
Note: It is questionable if it is worth it putting the effort to report
broken sh_entsize given that in files with no section table we have to
assume it is sizeof(Elf_Sym), but that is for another change.
Extracted from r260488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261099
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Krzysztof Parzyszek [Wed, 17 Feb 2016 15:02:07 +0000 (15:02 +0000)]
[Hexagon] Fold object construction into map::insert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261096
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Simon Pilgrim [Wed, 17 Feb 2016 14:56:58 +0000 (14:56 +0000)]
[X86][SSE] Update pshufb mask test to use a real input instead of undef
We are getting better at combining constant pshufb masks - this test would've failed once we decode bitcasted masks as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261095
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Chad Rosier [Wed, 17 Feb 2016 14:45:36 +0000 (14:45 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261093
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Igor Breger [Wed, 17 Feb 2016 14:04:33 +0000 (14:04 +0000)]
AVX512: Fix LowerMSCATTER() return value.
Bug description:
The bug was discovered when test was compiled with -O0.
In case scatter result is DAG root , VectorLegalizer failed (assert) due to LowerMSCATTER() return kmask as result.
Change LowerMSCATTER() to return chain as original node do.
Differential Revision: http://reviews.llvm.org/D17331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261090
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Scott Egerton [Wed, 17 Feb 2016 11:15:16 +0000 (11:15 +0000)]
[mips] Removed the SHF_ALLOC flag and the SHT_REL flag from the .pdr section.
This section is used for debug information and has no need to be
in memory at runtime. This patch also fixes an error when compiling
the Linux kernel. The error is that there are relocations within the
.pdr section in a VDSO. SHT_REL was removed as it is a section type
and not a section flag, therefore it does not make sense for it to
be there. With this patch, LLVM now emits the same flags as
the GNU assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261083
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Simon Pilgrim [Wed, 17 Feb 2016 10:50:06 +0000 (10:50 +0000)]
[X86][AVX] Support bit-blend integer shuffles for 256-bit integer vectors
AVX1 doesn't support the shuffling of 256-bit integer vectors. For 32/64-bit elements we get around this by shuffling as float/double but for 8/16-bit elements (assuming they can't widen) we currently just split, shuffle as 128-bit vectors and concatenate the results back.
This patch adds the ability to lower using the bit-blend patterns before defaulting to the splitting behaviour.
Part 2 of 2
Differential Revision: http://reviews.llvm.org/D17292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261082
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Simon Pilgrim [Wed, 17 Feb 2016 10:37:49 +0000 (10:37 +0000)]
[X86][AVX] Support bit-mask integer shuffles for 256-bit integer vectors
AVX1 doesn't support the shuffling of 256-bit integer vectors. For 32/64-bit elements we get around this by shuffling as float/double but for 8/16-bit elements (assuming they can't widen) we currently just split, shuffle as 128-bit vectors and concatenate the results back.
This patch adds the ability to lower using the bit-mask patterns before defaulting to the splitting behaviour. In some cases this ends up matching what AVX2 would do anyhow or what AVX1 does on the split vectors.
Part 1 of 2
Differential Revision: http://reviews.llvm.org/D17292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261081
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Simon Pilgrim [Wed, 17 Feb 2016 10:12:30 +0000 (10:12 +0000)]
[X86][SSE] Tidyup BUILD_VECTOR operand collection. NFCI.
Avoid reuse of operand variables, keep them local to a particular lowering - the operand collection is unique to each case anyhow.
Renamed from V to Ops to more closely match their purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261078
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Benjamin Kramer [Wed, 17 Feb 2016 09:28:45 +0000 (09:28 +0000)]
[Hexagon] cast<> a reference instead of referencing + dereferencing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261077
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David Blaikie [Wed, 17 Feb 2016 07:00:24 +0000 (07:00 +0000)]
llvm-dwp: Support for type units when merging DWPs into larger DWPs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261072
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David Blaikie [Wed, 17 Feb 2016 07:00:22 +0000 (07:00 +0000)]
Fix the hash function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261071
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Cong Hou [Wed, 17 Feb 2016 06:37:04 +0000 (06:37 +0000)]
Detecte vector reduction operations just before instruction selection.
This patch detects vector reductions before instruction selection. Vector
reductions are vectorized reduction operations, and for such operations we have
freedom to reorganize the elements of the result as long as the reduction of them
stay unchanged. This will enable some reduction pattern recognition during
instruction combine such as SAD/dot-product on X86. A flag is added to
SDNodeFlags to mark those vector reduction nodes to be checked during instruction
combine.
To detect those vector reductions, we search def-use chains starting from the
given instruction, and check if all uses fall into two categories:
1. Reduction with another vector.
2. Reduction on all elements.
in which 2 is detected by recognizing the pattern that the loop vectorizer
generates to reduce all elements in the vector outside of the loop, which
includes several ShuffleVector and one ExtractElement instructions.
Differential revision: http://reviews.llvm.org/D15250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261070
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Hans Wennborg [Wed, 17 Feb 2016 02:49:59 +0000 (02:49 +0000)]
Revert r260979 "[X86] Enable the LEA optimization pass by default."
Asserts are still firing in Chromium builds. PR26575.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261058
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Xinliang David Li [Wed, 17 Feb 2016 02:39:34 +0000 (02:39 +0000)]
revert r261038: arm/aarch64 bot failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261057
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Mehdi Amini [Wed, 17 Feb 2016 02:18:58 +0000 (02:18 +0000)]
Revert "Query the StringMap only once when creating MDString (NFC)"
This reverts commit r261030 and r261036.
(The revision was marked "approved" on phabricator, but some concerns
were raised on the mailing list. Thanks D. Blaikie for notifying me.)
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261055
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Haicheng Wu [Wed, 17 Feb 2016 02:01:50 +0000 (02:01 +0000)]
[AliasSetTracker] Teach AliasSetTracker about MemSetInst
This change is to fix the problem discussed in
http://lists.llvm.org/pipermail/llvm-dev/2016-February/095446.html.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261052
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JF Bastien [Wed, 17 Feb 2016 01:59:23 +0000 (01:59 +0000)]
WebAssembly: update expected failures
r261050 seems to inadvertently fix the assertion failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261051
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Dan Gohman [Wed, 17 Feb 2016 01:43:37 +0000 (01:43 +0000)]
[WebAssembly] Call memcpy for large byval copies.
This fixes very slow compilation on
test/CodeGen/Generic/2010-11-04-BigByval.ll . Note that MaxStoresPerMemcpy
and friends are not yet carefully tuned so the cutoff point is currently
somewhat arbitrary. However, it's important that there be a cutoff point
so that we don't emit unbounded quantities of loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261050
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JF Bastien [Wed, 17 Feb 2016 00:34:15 +0000 (00:34 +0000)]
WebAssembly: update expected test failures
r261032 adds frame address support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261044
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Chandler Carruth [Wed, 17 Feb 2016 00:18:16 +0000 (00:18 +0000)]
[LCG] Construct an actual call graph with call-edge SCCs nested inside
reference-edge SCCs.
This essentially builds a more normal call graph as a subgraph of the
"reference graph" that was the old model. This allows both to exist and
the different use cases to use the aspect which addresses their needs.
Specifically, the pass manager and other *ordering* constrained logic
can use the reference graph to achieve conservative order of visit,
while analyses reasoning about attributes and other properties derived
from reachability can reason about the direct call graph.
Note that this isn't necessarily complete: it doesn't model edges to
declarations or indirect calls. Those can be found by scanning the
instructions of the function if desirable, and in fact every user
currently does this in order to handle things like calls to instrinsics.
If useful, we could consider caching this information in the call graph
to save the instruction scans, but currently that doesn't seem to be
important.
An important realization for why the representation chosen here works is
that the call graph is a formal subset of the reference graph and thus
both can live within the same data structure. All SCCs of the call graph
are necessarily contained within an SCC of the reference graph, etc.
The design is to build 'RefSCC's to model SCCs of the reference graph,
and then within them more literal SCCs for the call graph.
The formation of actual call edge SCCs is not done lazily, unlike
reference edge 'RefSCC's. Instead, once a reference SCC is formed, it
directly builds the call SCCs within it and stores them in a post-order
sequence. This is used to provide a consistent platform for mutation and
update of the graph. The post-order also allows for very efficient
updates in common cases by bounding the number of nodes (and thus edges)
considered.
There is considerable common code that I'm still looking for the best
way to factor out between the various DFS implementations here. So far,
my attempts have made the code harder to read and understand despite
reducing the duplication, which seems a poor tradeoff. I've not given up
on figuring out the right way to do this, but I wanted to wait until
I at least had the system working and tested to continue attempting to
factor it differently.
This also requires introducing several new algorithms in order to handle
all of the incremental update scenarios for the more complex structure
involving two edge colorings. I've tried to comment the algorithms
sufficiently to make it clear how this is expected to work, but they may
still need more extensive documentation.
I know that there are some changes which are not strictly necessarily
coupled here. The process of developing this started out with a very
focused set of changes for the new structure of the graph and
algorithms, but subsequent changes to bring the APIs and code into
consistent and understandable patterns also ended up touching on other
aspects. There was no good way to separate these out without causing
*massive* merge conflicts. Ultimately, to a large degree this is
a rewrite of most of the core algorithms in the LCG class and so I don't
think it really matters much.
Many thanks to the careful review by Sanjoy Das!
Differential Revision: http://reviews.llvm.org/D16802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261040
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Reid Kleckner [Wed, 17 Feb 2016 00:17:33 +0000 (00:17 +0000)]
[X86] Fix a shrink-wrapping miscompile around __chkstk
__chkstk clobbers EAX. If EAX is live across the prologue, then we have
to take extra steps to save it. We already had code to do this if EAX
was a register parameter. This change adapts it to work when shrink
wrapping is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261039
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Xinliang David Li [Wed, 17 Feb 2016 00:14:52 +0000 (00:14 +0000)]
New test case: make sure alloc bit is not set for covmap section on Linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261038
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Dan Gohman [Wed, 17 Feb 2016 00:14:03 +0000 (00:14 +0000)]
[WebAssembly] Use SDValue::getConstantOperandVal. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261037
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Mehdi Amini [Wed, 17 Feb 2016 00:11:59 +0000 (00:11 +0000)]
Fix MSVC bot: apparently visual studio does not like explicitly defaulted move ctor
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261036
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Andrew Kaylor [Tue, 16 Feb 2016 23:52:18 +0000 (23:52 +0000)]
Fix build LLVM with -D LLVM_USE_INTEL_JITEVENTS:BOOL=ON on Windows
Differential Revision: http://reviews.llvm.org/D16940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261033
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Dan Gohman [Tue, 16 Feb 2016 23:48:04 +0000 (23:48 +0000)]
[WebAssembly] Implement __builtin_frame_address.
Differential Revision: http://reviews.llvm.org/D17307
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261032
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Mehdi Amini [Tue, 16 Feb 2016 23:05:56 +0000 (23:05 +0000)]
Query the StringMap only once when creating MDString (NFC)
Summary: Loading IR with debug info improves MDString::get() from 19ms to 10ms.
Reviewers: dexonsmith
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D16597
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261030
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Mehdi Amini [Tue, 16 Feb 2016 23:02:29 +0000 (23:02 +0000)]
Define the ThinLTO Pipeline (experimental)
Summary:
On the contrary to Full LTO, ThinLTO can afford to shift compile time
from the frontend to the linker: both phases are parallel (even if
it is not totally "free": projects like clang are reusing product
from the "compile phase" for multiple link, think about
libLLVMSupport reused for opt, llc, etc.).
This pipeline is based on the proposal in D13443 for full LTO. We
didn't move forward on this proposal because the LTO link was far too
long after that. We believe that we can afford it with ThinLTO.
The ThinLTO pipeline integrates in the regular O2/O3 flow:
- The compile phase perform the inliner with a somehow lighter
function simplification. (TODO: tune the inliner thresholds here)
This is intendend to simplify the IR and get rid of obvious things
like linkonce_odr that will be inlined.
- The link phase will run the pipeline from the start, extended with
some specific passes that leverage the augmented knowledge we have
during LTO. Especially after the inliner is done, a sequence of
globalDCE/globalOpt is performed, followed by another run of the
"function simplification" passes. It is not clear if this part
of the pipeline will stay as is, as the split model of ThinLTO
does not allow the same benefit as FullLTO without added tricks.
The measurements on the public test suite as well as on our internal
suite show an overall net improvement. The binary size for the clang
executable is reduced by 5%. We're still tuning it with the bringup
of ThinLTO and it will evolve, but this should provide a good starting
point.
Reviewers: tejohnson
Differential Revision: http://reviews.llvm.org/D17115
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261029
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Mehdi Amini [Tue, 16 Feb 2016 22:54:27 +0000 (22:54 +0000)]
Refactor the PassManagerBuilder: extract a "addFunctionSimplificationPasses()" (NFC)
It is intended to contains the passes run over a function after the
inliner is done with a function and before it moves to its callers.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261028
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Adam Nemet [Tue, 16 Feb 2016 22:50:19 +0000 (22:50 +0000)]
Fix test from r261013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261027
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Simon Pilgrim [Tue, 16 Feb 2016 22:33:27 +0000 (22:33 +0000)]
[X86][AVX] Regenerated vselect tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261026
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Ahmed Bougacha [Tue, 16 Feb 2016 22:14:12 +0000 (22:14 +0000)]
[X86] Remove the now-unused X86ISD::PSIGN. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261025
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Ahmed Bougacha [Tue, 16 Feb 2016 22:14:07 +0000 (22:14 +0000)]
[X86] Generalize logic blend of (x, -x) combine to match (-x, x).
I suspect this is what let PR26110 lie dormant for so long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261024
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Ahmed Bougacha [Tue, 16 Feb 2016 22:14:03 +0000 (22:14 +0000)]
[X86] Don't turn (c?-v:v) into (c?-v:0) by blindly using PSIGN.
Currently, we sometimes miscompile this vector pattern:
(c ? -v : v)
We lower it to (because "c" is <4 x i1>, lowered as a vector mask):
(~c & v) | (c & -v)
When we have SSSE3, we incorrectly lower that to PSIGN, which does:
(c < 0 ? -v : c > 0 ? v : 0)
in other words, when c is either all-ones or all-zero:
(c ? -v : 0)
While this is an old bug, it rarely triggers because the PSIGN combine
is too sensitive to operand order. This will be improved separately.
Note that the PSIGN tests are also incorrect. Consider:
%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
%sub = sub nsw <4 x i32> zeroinitializer, %a
%0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
%1 = and <4 x i32> %a, %0
%2 = and <4 x i32> %b.lobit, %sub
%cond = or <4 x i32> %1, %2
ret <4 x i32> %cond
if %b is zero:
%b.lobit = <4 x i32> zeroinitializer
%sub = sub nsw <4 x i32> zeroinitializer, %a
%0 = <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
%1 = <4 x i32> %a
%2 = <4 x i32> zeroinitializer
%cond = or <4 x i32> %a, zeroinitializer
ret <4 x i32> %a
whereas we currently generate:
psignd %xmm1, %xmm0
retq
which returns 0, as %xmm1 is 0.
Instead, use a pure logic sequence, as described in:
https://graphics.stanford.edu/~seander/bithacks.html#ConditionalNegate
Fixes PR26110.
Differential Revision: http://reviews.llvm.org/D17181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261023
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Ahmed Bougacha [Tue, 16 Feb 2016 22:13:59 +0000 (22:13 +0000)]
[X86] Extract PSIGN/BLENDVP tests into vector-blend.ll. NFC.
We're going to stop generating PSIGN, so calling a test "psign"
isn't ideal. Instead, call these tests what they really are:
variable blends using logic.
Also add a test to exhibit a case we're currently missing in
the PSIGN combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261022
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Ahmed Bougacha [Tue, 16 Feb 2016 22:13:55 +0000 (22:13 +0000)]
[X86] Extract PSIGN/BLENDVP combine. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261021
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Ahmed Bougacha [Tue, 16 Feb 2016 22:13:49 +0000 (22:13 +0000)]
[X86] Extract ANDNP combine. NFC.
This makes it IMO more readable and reduces indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261020
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Mehdi Amini [Tue, 16 Feb 2016 22:07:03 +0000 (22:07 +0000)]
Bitcode writer: fix a typo, using getName() instead of getSourceFileName()
When emitting the source filename, the encoding of the string
was checked against the name instead of the filename.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261019
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Derek Schuff [Tue, 16 Feb 2016 21:52:06 +0000 (21:52 +0000)]
[WebAssembly] Update torture test expectations
These were fixed with r260978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261017
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Reid Kleckner [Tue, 16 Feb 2016 21:49:26 +0000 (21:49 +0000)]
[codeview] Bail on a DBG_VALUE register operand with no register
This apparently comes up when the register allocator decides that a
variable will become undef along a certain path.
Also improve the error message we emit when we can't map from LLVM
register number to CV register number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261016
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Derek Schuff [Tue, 16 Feb 2016 21:44:19 +0000 (21:44 +0000)]
[WebAssemly] Don't move calls or stores past intervening loads
The register stackifier currently checks for intervening stores (and
loads that may alias them) but doesn't account for the fact that the
instruction being moved may affect intervening loads.
Differential Revision: http://reviews.llvm.org/D17298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261014
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Adam Nemet [Tue, 16 Feb 2016 21:41:51 +0000 (21:41 +0000)]
[LTO] Support Statistics
Summary:
I thought -Xlinker -mllvm -Xlinker -stats worked at some point but maybe
it never did.
For clang, I believe that stats are printed from cc1_main. This patch
also prints them for LTO, specifically right after codegen happens.
I only looked at the C API for LTO briefly to see if this is a good
place. Probably there are still cases where this wouldn't be printed
but it seems to be working for the common case. I also experimented
putting this in the LTOCodeGenerator destructor but that didn't trigger
for me because ld64 does not destroy the LTOCodeGenerator.
Reviewers: dexonsmith, joker.eph
Subscribers: rafael, joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D17302
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261013
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Reid Kleckner [Tue, 16 Feb 2016 21:14:51 +0000 (21:14 +0000)]
[codeview] Fix assertion on non-memory, non-register DBG_VALUE instructions
Eventually we should find a way to describe constant variables, but it
is not obvious how to do this at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261010
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Colin LeMahieu [Tue, 16 Feb 2016 20:38:17 +0000 (20:38 +0000)]
[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.
The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.
Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.
This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261006
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Jun Bum Lim [Tue, 16 Feb 2016 20:02:39 +0000 (20:02 +0000)]
[AArch64] Add pass to remove redundant copy after RA
Summary:
This change will add a pass to remove unnecessary zero copies in target blocks
of cbz/cbnz instructions. E.g., the copy instruction in the code below can be
removed because the cbz jumps to BB1 when x0 is zero :
BB0:
cbz x0, .BB1
BB1:
mov x0, xzr
Jun
Reviewers: gberry, jmolloy, HaoLiu, MatzeB, mcrosier
Subscribers: mcrosier, mssimpso, haicheng, bmakam, llvm-commits, aemerson, rengolin
Differential Revision: http://reviews.llvm.org/D16203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261004
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Quentin Colombet [Tue, 16 Feb 2016 19:26:02 +0000 (19:26 +0000)]
[GlobalISel] Re-apply r260922-260923 with MSVC-friendly code.
Original message:
Get rid of the ifdefs in TargetLowering.
Introduce a new API used only by GlobalISel: CallLowering.
This API will contain target hooks dedicated to call lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260998
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Rafael Espindola [Tue, 16 Feb 2016 18:50:12 +0000 (18:50 +0000)]
Pass a std::unique_ptr to IRMover::move.
It was already the one "destroying" the source module, now the API
reflects that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260989
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Derek Schuff [Tue, 16 Feb 2016 18:18:36 +0000 (18:18 +0000)]
[WebAssembly] Insert COPY_LOCAL between CopyToReg and FrameIndex DAG nodes
CopyToReg nodes don't support FrameIndex operands. Other targets select
the FI to some LEA-like instruction, but since we don't have that, we
need to insert some kind of instruction that can take an FI operand and
produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
copy_local between Op and its FI operand. This results in a redundant
copy which we should optimize away later (maybe in the post-FI-lowering
peephole pass).
Differential Revision: http://reviews.llvm.org/D17213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260987
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