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Hal Finkel [Sat, 19 Jul 2014 13:33:16 +0000 (13:33 +0000)]
[LoopVectorize] Propagate known metadata to vectorized instructions
There are some kinds of metadata that are safe to propagate from the scalar
instructions to the vector instructions (fpmath and tbaa currently).
Regarding TBAA, one might worry about propagating it on if-converted loads and
stores, because the metadata might have had a control dependency on the
condition, and thus actually aliased with some other non-speculated memory
access when the condition was false. However, this would be caught by the
runtime overlap checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213452
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Andrea Di Biagio [Sat, 19 Jul 2014 07:52:58 +0000 (07:52 +0000)]
[x86] Fix wrong shuffle mask in test 'combine-vec-shuffle-3.ll'. No functional change.
Function @test3c should check that the DAGCombiner is able to fold a pair of
shuffles into a new shuffle with a permute mask of <6,7,2,3>. However, one of
the shuffles in @test3c had a wrong permute mask; this prevented the DAGCombiner
from folding the shuffles into the expected result.
Now that the shuffle mask is fixed, the backend correctly folds the two shuffles
in function @test3c into a single movhlps instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213451
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Hal Finkel [Sat, 19 Jul 2014 03:32:02 +0000 (03:32 +0000)]
Handle AddrSpaceCast in stripAndAccumulateInBoundsConstantOffsets
All of the other similar functions in that part of the file look through
addrspacecast in addition to bitcast, and I see no reason why
stripAndAccumulateInBoundsConstantOffsets shouldn't do so also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213449
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NAKAMURA Takumi [Sat, 19 Jul 2014 03:29:25 +0000 (03:29 +0000)]
MergedLoadStoreMotion.cpp: Fix msc17 build. Member initializer is unavailable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213448
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Hal Finkel [Sat, 19 Jul 2014 03:25:16 +0000 (03:25 +0000)]
Make Value::isDereferenceablePointer handle offsets to pointer types with dereferenceable attributes
When we have a parameter (or call site return) with a dereferenceable
attribute, it can specify the size of an array pointed to by that parameter. If
we have a value for which we can accumulate a constant offset to such a
parameter, then we can use that offset in a direct comparison with the size
specified by the dereferenceable attribute.
This enables us to handle cases like this:
int foo(int a[static 3]) {
return a[2]; /* this is always dereferenceable */
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213447
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Saleem Abdulrasool [Sat, 19 Jul 2014 01:29:51 +0000 (01:29 +0000)]
ARM: correct WoA __builtin_alloca handling on O0
When performing a dynamic stack adjustment without optimisations, we would mark
SP as def and R4 as kill. This occurred as part of the expansion of a
WIN__CHKSTK SDNode which indicated the proper handling of SP and R4. The result
would be that we would double define SP as part of an operation, which is
obviously incorrect.
Furthermore, the VTList for the chain had an incorrect parameter type of i32
instead of Other.
Correct these to permit proper lowering of __builtin_alloca at -O0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213442
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David Blaikie [Sat, 19 Jul 2014 01:05:11 +0000 (01:05 +0000)]
Remove uses of the redundant ".reset(nullptr)" of unique_ptr, in favor of ".reset()"
It's also possible to just write "= nullptr", but there's some question
of whether that's as readable, so I leave it up to authors to pick which
they prefer for now. If we want to discuss standardizing on one or the
other, we can do that at some point in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213438
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Lang Hames [Sat, 19 Jul 2014 00:19:17 +0000 (00:19 +0000)]
[MCJIT] Add a 'decodeAddend' method to RuntimeDyldMachO and teach
getBasicRelocationEntry to use this rather than 'memcpy' to get the
relocation addend. Targets with non-trivial addend encodings (E.g. AArch64) can
override decodeAddend to handle immediates with interesting encodings.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213435
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Eric Christopher [Fri, 18 Jul 2014 23:57:20 +0000 (23:57 +0000)]
Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself.""""
After a successful build it seems to have come back on a later build.
This reverts commit r213391.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213432
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Eric Christopher [Fri, 18 Jul 2014 23:41:32 +0000 (23:41 +0000)]
Fundamentally change the MipsSubtarget replacement machinery:
a) Move the replacement level decision to the target machine.
b) Create additional subtargets at the TargetMachine level to
cache and make replacement easy.
c) Make the mips16 features obvious.
d) Remove the override logic as it no longer does anything.
e) Have MipsModuleDAGToDAGISel take only the target machine.
f) Have the constant islands pass grab the current subtarget
from the MachineFunction (via the TargetMachine) instead
of caching it.
g) Unconditionally initialize TLOF.
h) Remove the old complicated subtarget based resetting and
replace it with simple conditionals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213430
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Eric Christopher [Fri, 18 Jul 2014 23:33:47 +0000 (23:33 +0000)]
FrameLowering depends only upon the Subtarget, so only take a subtarget
during initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213429
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Hal Finkel [Fri, 18 Jul 2014 23:29:49 +0000 (23:29 +0000)]
[PowerPC] 32-bit ELF PIC support
This adds initial support for PPC32 ELF PIC (Position Independent Code; the
-fPIC variety), thus rectifying a long-standing deficiency in the PowerPC
backend.
Patch by Justin Hibbits!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213427
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Eric Christopher [Fri, 18 Jul 2014 23:25:04 +0000 (23:25 +0000)]
In preparation for replacing the whole subtarget on the target machine,
have target lowering take the subtarget explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213426
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Eric Christopher [Fri, 18 Jul 2014 23:25:00 +0000 (23:25 +0000)]
Make InstrInfo depend only upon the Subtarget getting passed in
rather than the TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213425
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Eric Christopher [Fri, 18 Jul 2014 22:55:25 +0000 (22:55 +0000)]
The subtarget in MipsTargetLowering isn't going to change and
so doesn't need to be a pointer, but a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213422
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Eric Christopher [Fri, 18 Jul 2014 22:34:20 +0000 (22:34 +0000)]
Avoid caching the relocation model on the subtarget, this is for
two reasons:
a) we're already caching the target machine which contains it,
b) which relocation model you get is dependent upon whether or
not you ask before MCCodeGenInfo is constructed on the target
machine, so avoid any latent issues there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213420
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Eric Christopher [Fri, 18 Jul 2014 22:34:18 +0000 (22:34 +0000)]
Remove commented out code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213419
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Eric Christopher [Fri, 18 Jul 2014 22:34:14 +0000 (22:34 +0000)]
Clean up some style and formatting issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213418
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David Blaikie [Fri, 18 Jul 2014 22:26:59 +0000 (22:26 +0000)]
DebugInfo: Assert that all abstract scopes are subprograms, rather than conditionalizing.
There's nothing else these should ever be...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213417
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Mark Heffernan [Fri, 18 Jul 2014 21:29:41 +0000 (21:29 +0000)]
Fix build breakage introduced with r213412.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213414
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Mark Heffernan [Fri, 18 Jul 2014 21:04:33 +0000 (21:04 +0000)]
Remove unroll pragma metadata after it is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213412
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Eric Christopher [Fri, 18 Jul 2014 20:35:49 +0000 (20:35 +0000)]
Fix a couple of formatting and style issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213409
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Lang Hames [Fri, 18 Jul 2014 20:29:36 +0000 (20:29 +0000)]
[MCJIT] [AArch64] Make sure to propegate ARM64_RELOC_ADDEND values into the
RelocationEntry.
No test case yet, as this primarily hits GOT entries, which RuntimeDyldChecker
can't examine yet. I'm actively working on features that will enable us to
test this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213408
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Eric Christopher [Fri, 18 Jul 2014 20:29:02 +0000 (20:29 +0000)]
Make non-module passes unconditionally added in the pass
manager for mips, and early exit if we don't want to do
anything because of the current subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213407
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Eli Bendersky [Fri, 18 Jul 2014 20:11:26 +0000 (20:11 +0000)]
Add tests for atomic adds on floats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213406
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Tyler Nowicki [Fri, 18 Jul 2014 19:36:04 +0000 (19:36 +0000)]
Rename DiagnosticInfoOptimizationWarning to DiagnosticInfoOptimizationFailure
so the severity of the message is not part of the type name.
Reviewed by Alp Toker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213399
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Eli Bendersky [Fri, 18 Jul 2014 19:32:09 +0000 (19:32 +0000)]
Use CHECK-LABEL where appropriate in this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213398
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Mark Heffernan [Fri, 18 Jul 2014 19:24:51 +0000 (19:24 +0000)]
Add loop unrolling metadata descriptions to docs/LangRef.rst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213397
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Gerolf Hoflehner [Fri, 18 Jul 2014 19:13:09 +0000 (19:13 +0000)]
MergedLoadStoreMotion pass
Merges equivalent loads on both sides of a hammock/diamond
and hoists into into the header.
Merges equivalent stores on both sides of a hammock/diamond
and sinks it to the footer.
Can enable if conversion and tolerate better load misses
and store operand latencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213396
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David Blaikie [Fri, 18 Jul 2014 17:49:10 +0000 (17:49 +0000)]
Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself."""
Recommits 212776 which was reverted in r212793. This has been committed
and recommitted a few times as I try to test it harder and find/fix more
issues. The most recent revert was due to an asan bot failure which I
can't seem to reproduce locally, though I believe I'm following all the
steps the buildbot does.
So I'm going to recommit this in the hopes of investigating the failure
on the buildbot itself... apologies in advance for the bot noise. If
anyone sees failures with this /please/ provide me with any
reproductions, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213391
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David Peixotto [Fri, 18 Jul 2014 16:41:58 +0000 (16:41 +0000)]
Fix build failure on windows
Add explicit constructor to struct instead of using brace initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213389
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David Peixotto [Fri, 18 Jul 2014 16:05:14 +0000 (16:05 +0000)]
MC: support different sized constants in constant pools
On AArch64 the pseudo instruction ldr <reg>, =... supports both
32-bit and 64-bit constants. Add support for 64 bit constants for
the pools to support the pseudo instruction fully.
Changes the AArch64 ldr-pseudo tests to use 32-bit registers and
adds tests with 64-bit registers.
Patch by Janne Grunau!
Differential Revision: http://reviews.llvm.org/D4279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213387
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Hal Finkel [Fri, 18 Jul 2014 15:51:28 +0000 (15:51 +0000)]
Add a dereferenceable attribute
This attribute indicates that the parameter or return pointer is
dereferenceable. Practically speaking, loads from such a pointer within the
associated byte range are safe to speculatively execute. Such pointer
parameters are common in source languages (C++ references, for example).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213385
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Daniel Sanders [Fri, 18 Jul 2014 14:28:19 +0000 (14:28 +0000)]
Add MIPS Technologies to the vendors in llvm::Triple.
This is a prerequisite for checking for 'mti' and 'img' in a consistent way in
clang. Previously 'img' could use Triple::getVendor() but 'mti' could only use
Triple::getVendorName().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213381
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Tim Northover [Fri, 18 Jul 2014 13:07:05 +0000 (13:07 +0000)]
AArch64: implement efficient f16 bitcasts
Because i16 is illegal, there's no native DAG method to
represent a bitcast to or from an f16 type. This meant LLVM was
inserting a stack store/load pair which is really not ideal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213378
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Tim Northover [Fri, 18 Jul 2014 13:01:43 +0000 (13:01 +0000)]
NVPTX: support fpext/fptrunc to and from f16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213377
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Tim Northover [Fri, 18 Jul 2014 13:01:37 +0000 (13:01 +0000)]
R600: support fpext/fptrunc operations to and from f16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213376
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Tim Northover [Fri, 18 Jul 2014 13:01:31 +0000 (13:01 +0000)]
AArch64: support f16 extend/trunc operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213375
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Tim Northover [Fri, 18 Jul 2014 13:01:25 +0000 (13:01 +0000)]
X86: support fpext/fptrunc operations to and from 16-bit floats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213374
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Tim Northover [Fri, 18 Jul 2014 13:01:19 +0000 (13:01 +0000)]
ARM: support legalisation of "fptrunc ... to half" operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213373
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Tim Northover [Fri, 18 Jul 2014 12:41:46 +0000 (12:41 +0000)]
CodeGen: soften f16 type by default instead of marking legal.
Actual support for softening f16 operations is still limited, and can be added
when it's needed. But Soften is much closer to being a useful thing to try
than keeping it Legal when no registers can actually hold such values.
Longer term, we probably want something between Soften and Promote semantics
for most targets, it'll be more efficient to promote the 4 basic operations to
f32 than libcall them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213372
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Renato Golin [Fri, 18 Jul 2014 12:13:04 +0000 (12:13 +0000)]
Suppress 'not handled in switch' warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213371
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Tilmann Scheller [Fri, 18 Jul 2014 12:05:49 +0000 (12:05 +0000)]
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STR instructions.
The post-indexed instructions were missing the constraint, causing unpredictable STR instructions to be emitted.
The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed.
This fixes PR20323.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213369
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Renato Golin [Fri, 18 Jul 2014 12:00:48 +0000 (12:00 +0000)]
Refactor ARM subarchitecture parsing
Re-commit of a patch to rework the triple parsing on ARM to a more sane
model.
Patch by Gabor Ballabas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213367
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Artyom Skrobov [Fri, 18 Jul 2014 09:26:16 +0000 (09:26 +0000)]
extracting swapStruct into include/llvm/Support/MachO.h (no functional change)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213361
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Tim Northover [Fri, 18 Jul 2014 08:43:30 +0000 (08:43 +0000)]
R600: rename misleading fp16 test.
This test is actually going in the opposite direction to what the
filename and function name suggested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213358
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Tim Northover [Fri, 18 Jul 2014 08:43:24 +0000 (08:43 +0000)]
R600: support f16 -> f64 conversion intrinsic.
Unfortunately, we don't seem to have a direct truncation, but the
extension can be legally split into two operations so we should
support that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213357
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Tim Northover [Fri, 18 Jul 2014 08:30:10 +0000 (08:30 +0000)]
NVPTX: support direct f16 <-> f64 conversions via intrinsics.
Clang may well start emitting these soon, and while it may not be
directly relevant for OpenCL or GLSL, the instructions were just
sitting there waiting to be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213356
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Hal Finkel [Fri, 18 Jul 2014 06:51:55 +0000 (06:51 +0000)]
Rename AlignAttribute to IntAttribute
Currently the only kind of integer IR attributes that we have are alignment
attributes, and so the attribute kind that takes an integer parameter is called
AlignAttr, but that will change (we'll soon be adding a dereferenceable
attribute that also takes an integer value). Accordingly, rename AlignAttribute
to IntAttribute (class names, enums, etc.).
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213352
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Matt Arsenault [Fri, 18 Jul 2014 06:07:13 +0000 (06:07 +0000)]
R600: Implement TTI:getPopcntSupport
The test is just copied from X86, and I don't know of a better
way to test it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213351
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Jim Grosbach [Fri, 18 Jul 2014 00:40:56 +0000 (00:40 +0000)]
X86: Constant fold converting vector setcc results to float.
Since the result of a SETCC for X86 is 0 or -1 in each lane, we can
move unary operations, in this case [su]int_to_fp through the mask
operation and constant fold the operation away. Generally speaking:
UNARYOP(AND(VECTOR_CMP(x,y), constant))
--> AND(VECTOR_CMP(x,y), constant2)
where constant2 is UNARYOP(constant).
This implements the transform where UNARYOP is [su]int_to_fp.
For example, consider the simple function:
define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
%cmp = fcmp oeq <4 x float> %val, %test
%ext = zext <4 x i1> %cmp to <4 x i32>
%result = sitofp <4 x i32> %ext to <4 x float>
ret <4 x float> %result
}
Before this change, the SSE code is generated as:
LCPI0_0:
.long 1 ## 0x1
.long 1 ## 0x1
.long 1 ## 0x1
.long 1 ## 0x1
.section __TEXT,__text,regular,pure_instructions
.globl _foo
.align 4, 0x90
_foo: ## @foo
cmpeqps %xmm1, %xmm0
andps LCPI0_0(%rip), %xmm0
cvtdq2ps %xmm0, %xmm0
retq
After, the code is improved to:
LCPI0_0:
.long
1065353216 ## float 1.
000000e+00
.long
1065353216 ## float 1.
000000e+00
.long
1065353216 ## float 1.
000000e+00
.long
1065353216 ## float 1.
000000e+00
.section __TEXT,__text,regular,pure_instructions
.globl _foo
.align 4, 0x90
_foo: ## @foo
cmpeqps %xmm1, %xmm0
andps LCPI0_0(%rip), %xmm0
retq
The cvtdq2ps has been constant folded away and the floating point 1.0f
vector lanes are materialized directly via the ModRM operand of andps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213342
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Jim Grosbach [Fri, 18 Jul 2014 00:40:52 +0000 (00:40 +0000)]
AArch64: Constant fold converting vector setcc results to float.
Since the result of a SETCC for AArch64 is 0 or -1 in each lane, we can
move unary operations, in this case [su]int_to_fp through the mask
operation and constant fold the operation away. Generally speaking:
UNARYOP(AND(VECTOR_CMP(x,y), constant))
--> AND(VECTOR_CMP(x,y), constant2)
where constant2 is UNARYOP(constant).
This implements the transform where UNARYOP is [su]int_to_fp.
For example, consider the simple function:
define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
%cmp = fcmp oeq <4 x float> %val, %test
%ext = zext <4 x i1> %cmp to <4 x i32>
%result = sitofp <4 x i32> %ext to <4 x float>
ret <4 x float> %result
}
Before this change, the code is generated as:
fcmeq.4s v0, v0, v1
movi.4s v1, #0x1 // Integer splat value.
and.16b v0, v0, v1 // Mask lanes based on the comparison.
scvtf.4s v0, v0 // Convert each lane to f32.
ret
After, the code is improved to:
fcmeq.4s v0, v0, v1
fmov.4s v1, #1.
00000000 // f32 splat value.
and.16b v0, v0, v1 // Mask lanes based on the comparison.
ret
The svvtf.4s has been constant folded away and the floating point 1.0f
vector lanes are materialized directly via fmov.4s.
Rather than do the folding manually in the target code, teach getNode()
in the generic SelectionDAG to handle folding constant operands of
vector [su]int_to_fp nodes. It is reasonable (as noted in a FIXME) to do
additional constant folding there as well, but I don't have test cases
for those operations, so leaving them for another time when it becomes
appropriate.
rdar://
17693791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213341
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Michael J. Spencer [Fri, 18 Jul 2014 00:15:50 +0000 (00:15 +0000)]
Revert "[x86] Fold extract_vector_elt of a load into the Load's address computation."
There's a bug where this can create cycles in the DAG. It will take a bit
to fix, so I'm backing it out for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213339
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Eric Christopher [Fri, 18 Jul 2014 00:08:53 +0000 (00:08 +0000)]
Reset the Subtarget in the AsmPrinter for each machine function
and add explanatory comment about dual initialization. Fix
use of the Subtarget to grab the information off of the target machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213336
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Eric Christopher [Fri, 18 Jul 2014 00:08:50 +0000 (00:08 +0000)]
Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachine
Options struct and move the comment to inMips16HardFloat. Use the
fact that we now know whether or not we cared about soft float to
set the libcalls.
Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and
propagate since it's no longer CPU specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213335
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Lang Hames [Thu, 17 Jul 2014 23:11:30 +0000 (23:11 +0000)]
[MCJIT] Fix the alignment requirements for ARM and AArch64 which were mistakenly
relaxed in the big RuntimeDyldMachO cleanup of r213293.
No test case yet - this was found via inspection and there's no easy way to test
GOT alignment in RuntimeDyldChecker at the moment. I'm working on adding support
for this now, and hope to have a test case for this soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213331
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Kevin Enderby [Thu, 17 Jul 2014 22:56:27 +0000 (22:56 +0000)]
Tweak formating to match what clang-format would be for llvm-nm.cpp .
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213330
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Kevin Enderby [Thu, 17 Jul 2014 22:47:16 +0000 (22:47 +0000)]
Add printing of Mach-O stabs in llvm-nm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213327
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Reid Kleckner [Thu, 17 Jul 2014 22:43:00 +0000 (22:43 +0000)]
Remove rules against std::function from the programmer's manual
Clarify that llvm::function_ref is like StringRef for callables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213326
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Nico Weber [Thu, 17 Jul 2014 20:24:55 +0000 (20:24 +0000)]
ms inline asm: Don't add x86 segment registers to the clobber list.
Clang tries to check the clobber list but doesn't list segment registers in its
x86 register list. This fixes PR20343.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213303
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Lang Hames [Thu, 17 Jul 2014 20:23:31 +0000 (20:23 +0000)]
Make myself code owner of MCJIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213302
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Alp Toker [Thu, 17 Jul 2014 20:05:29 +0000 (20:05 +0000)]
Drop the udis86 wrapper from llvm::sys
This optional dependency on the udis86 library was added some time back to aid
JIT development, but doesn't make much sense to link into LLVM binaries these
days.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213300
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Reid Kleckner [Thu, 17 Jul 2014 19:43:40 +0000 (19:43 +0000)]
TableGen: Add 'static' to a large array to avoid a huge stack allocation
Speculative fix for a -Wframe-larger-than warning from gcc. Clang will
implicitly promote such constant arrays to globals, so in theory it
won't hit this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213298
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Arnaud A. de Grandmaison [Thu, 17 Jul 2014 19:08:14 +0000 (19:08 +0000)]
[AArch64] Cleanup AsmParser: no need to use dyn_cast + assert. cast does it for us.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213296
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Suyog Sarda [Thu, 17 Jul 2014 19:07:00 +0000 (19:07 +0000)]
Rectify r213231. Use proper version of 'ComputeNumSignBits'.
Earlier when the code was in InstCombine, we were calling the version of ComputeNumSignBits in InstCombine.h
that automatically added the DataLayout* before calling into ValueTracking.
When the code moved to InstSimplify, we are calling into ValueTracking directly without passing in the DataLayout*.
This patch rectifies the same by passing DataLayout in ComputeNumSignBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213295
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Lang Hames [Thu, 17 Jul 2014 18:54:50 +0000 (18:54 +0000)]
[MCJIT] Significantly refactor the RuntimeDyldMachO class.
The previous implementation of RuntimeDyldMachO mixed logic for all targets
within a single class, creating problems for readability, maintainability, and
performance. To address these issues, this patch strips the RuntimeDyldMachO
class down to just target-independent functionality, and moves all
target-specific functionality into target-specific subclasses RuntimeDyldMachO.
The new class hierarchy is as follows:
class RuntimeDyldMachO
Implemented in RuntimeDyldMachO.{h,cpp}
Contains logic that is completely independent of the target. This consists
mostly of MachO helper utilities which the derived classes use to get their
work done.
template <typename Impl>
class RuntimeDyldMachOCRTPBase<Impl> : public RuntimeDyldMachO
Implemented in RuntimeDyldMachO.h
Contains generic MachO algorithms/data structures that defer to the Impl class
for target-specific behaviors.
RuntimeDyldMachOARM : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOARM>
RuntimeDyldMachOARM64 : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOARM64>
RuntimeDyldMachOI386 : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOI386>
RuntimeDyldMachOX86_64 : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOX86_64>
Implemented in their respective *.h files in lib/ExecutionEngine/RuntimeDyld/MachOTargets
Each of these contains the relocation logic specific to their target architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213293
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Alexey Samsonov [Thu, 17 Jul 2014 18:48:12 +0000 (18:48 +0000)]
[ASan] Don't instrument load/stores with !nosanitize metadata.
This is used to avoid instrumentation of instructions added by UBSan
in Clang frontend (see r213291). This fixes PR20085.
Reviewed in http://reviews.llvm.org/D4544.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213292
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Hans Wennborg [Thu, 17 Jul 2014 18:33:44 +0000 (18:33 +0000)]
Typo: exists -> exits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213290
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Justin Holewinski [Thu, 17 Jul 2014 18:10:09 +0000 (18:10 +0000)]
[NVPTX] Improve handling of FP fusion
We now consider the FPOpFusion flag when determining whether
to fuse ops. We also explicitly emit add.rn when fusion is
disabled to prevent ptxas from fusing the operations on its
own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213287
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Matt Arsenault [Thu, 17 Jul 2014 17:50:22 +0000 (17:50 +0000)]
Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213285
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Zinovy Nis [Thu, 17 Jul 2014 17:14:35 +0000 (17:14 +0000)]
[BUG] Due to a typo introduced in r199933 and r200027 two tests for FMA were never even started.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213283
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Adam Nemet [Thu, 17 Jul 2014 17:04:56 +0000 (17:04 +0000)]
[X86] AVX512: Add disassembler support for compressed displacement
There are two parts here. First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.
The second is to use the new encoding types to compute the correct
displacement in the decoder.
Fixes <rdar://problem/
17608489>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281
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Adam Nemet [Thu, 17 Jul 2014 17:04:52 +0000 (17:04 +0000)]
[X86] AVX512: Rename EVEX_CD8V to CD8_Form
This is to match the naming of CD8_EltSize, CD8_Scale, etc.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213280
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Adam Nemet [Thu, 17 Jul 2014 17:04:50 +0000 (17:04 +0000)]
[X86] AVX512: Use the TD version of CD8_Scale in the assembler
Passes the computed scaling factor in TSFlags rather than the old attributes.
Also removes the C++ version of computing the scaling factor (MemObjSize)
along with the asserts added by the previous patch.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213279
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Adam Nemet [Thu, 17 Jul 2014 17:04:34 +0000 (17:04 +0000)]
[X86] AVX512: Move compressed displacement logic to TD
This does not actually move the logic yet but reimplements it in the Tablegen
language. Then asserts that the new implementation results in the same value.
The next patch will remove the assert and the temporary use of the TSFlags and
remove the C++ implementation.
The formula requires a limited form of the logical left and right operators.
I implemented these with the bit-extract/insert operator (i.e. blah{bits}).
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213278
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Adam Nemet [Thu, 17 Jul 2014 17:04:27 +0000 (17:04 +0000)]
[TableGen] Allow shift operators to take bits<n>
Convert the operand to int if possible, i.e. if the value is properly
initialized. (I suppose there is further room for improvement here to also
peform the shift if the uninitialized bits are shifted out.)
With this little change we can now compute the scaling factor for compressed
displacement with pure tablegen code in the X86 backend. This is useful
because both the X86-disassembler-specific part of tablegen and the assembler
need this and TD is the natural sharing place.
The patch also adds the missing documentation for the shift and add operator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213277
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Justin Holewinski [Thu, 17 Jul 2014 16:58:56 +0000 (16:58 +0000)]
[NVPTX] Add missing .v4 qualifier on vector store instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213276
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Saleem Abdulrasool [Thu, 17 Jul 2014 16:27:44 +0000 (16:27 +0000)]
MC: correct DWARF header for PE/COFF assembly input
The header contains an offset to the DWARF abbreviations for the CU. The offset
must be section relative for COFF and absolute for others. The non-assembly
code path for the DWARF header generation already had the correct emission for
the headers. This corrects just the assembly path. Due to the invalid
relocation, processing of the debug information would halt previously on the
first assembly input as the associated abbreviations would be out of range as
they would have the location increased by image base and the section offset.
This address PR20332.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213275
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Saleem Abdulrasool [Thu, 17 Jul 2014 16:27:40 +0000 (16:27 +0000)]
MC: fix MCAsmInfo usage for windows-itanium
Windows itanium uses the GNUCOFF assmebly format, not ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213274
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Saleem Abdulrasool [Thu, 17 Jul 2014 16:27:35 +0000 (16:27 +0000)]
MC: collapse emission of producer
Rather than use three EmitBytes, concatenate the string at compile time,
constructing a single StringRef and emitting the data in one shot. This also
creates nicer assembly output. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213273
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Justin Holewinski [Thu, 17 Jul 2014 14:51:33 +0000 (14:51 +0000)]
[NVPTX] Flag surface/texture query instructions with IsTexSurfQuery
Also, add some tests to make sure we can handle surface/texture
queries on both Fermi and Kepler+.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213268
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Justin Holewinski [Thu, 17 Jul 2014 11:59:04 +0000 (11:59 +0000)]
[NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch
This also uses TSFlags to mark machine instructions that are surface/texture
accesses, as well as the vector width for surface operations. This is used
to simplify some of the switch statements that need to detect surface/texture
instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213256
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Tim Northover [Thu, 17 Jul 2014 11:27:04 +0000 (11:27 +0000)]
ARM: support direct f16 <-> f64 conversions
ARMv8 has instructions to handle it, otherwise a libcall is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213254
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Justin Holewinski [Thu, 17 Jul 2014 11:23:29 +0000 (11:23 +0000)]
[TABLEGEN] Do not crash on intrinsics with names longer than 40 characters
Differential Revision: http://reviews.llvm.org/D4537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213253
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Tim Northover [Thu, 17 Jul 2014 11:12:12 +0000 (11:12 +0000)]
CodeGen: generate single libcall for fptrunc -> f16 operations.
Previously we asserted on this code. Currently compiler-rt doesn't
actually implement any of these new libcalls, but external help is
pretty much the only viable option for LLVM.
I've followed the much more generic "__truncST2" naming, as opposed to
the odd name for f32 -> f16 truncation. This can obviously be changed
later, or overridden by any targets that need to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213252
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Tim Northover [Thu, 17 Jul 2014 11:04:04 +0000 (11:04 +0000)]
X86: support double extension of f16 type.
x86 has no native ability to extend an f16 to f64, but the same result
is obtained if we expand it into two separate extensions: f16 -> f32
-> f64.
Unfortunately the same is not true for truncate, so that still results
in a compilation failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213251
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Tim Northover [Thu, 17 Jul 2014 10:51:23 +0000 (10:51 +0000)]
CodeGen: extend f16 conversions to permit types > float.
This makes the two intrinsics @llvm.convert.from.f16 and
@llvm.convert.to.f16 accept types other than simple "float". This is
only strictly needed for the truncate operation, since otherwise
double rounding occurs and there's no way to represent the strict IEEE
conversion. However, for symmetry we allow larger types in the extend
too.
During legalization, we can expand an "fp16_to_double" operation into
two extends for convenience, but abort when the truncate isn't legal. A new
libcall is probably needed here.
Even after this commit, various target tweaks are needed to actually use the
extended intrinsics. I've put these into separate commits for clarity, so there
are no actual tests of f64 conversion here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248
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Yi Kong [Thu, 17 Jul 2014 10:50:20 +0000 (10:50 +0000)]
Port memory barriers intrinsics to AArch64
Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to
implement their corresponding ACLE and MSVC intrinsics.
This patch ports ARM dmb, dsb, isb intrinsic to AArch64.
Differential Revision: http://reviews.llvm.org/D4520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213247
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Daniel Sanders [Thu, 17 Jul 2014 10:10:04 +0000 (10:10 +0000)]
[mips] .reginfo is 8 byte aligned on N32.
Differential Revision: http://reviews.llvm.org/D4540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213246
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Daniel Sanders [Thu, 17 Jul 2014 10:02:08 +0000 (10:02 +0000)]
[mips] Correct ELF e_flags for the N32 ABI when using a mips-* triple rather than a mips64-* triple
Summary:
Generally speaking, mips-* vs mips64-* should not be used to make decisions
about the content or format of the ELF. This should be based on the ABI
and CPU in use. For example, `mips-linux-gnu-clang -mips64r2 -mabi=64`
should produce an ELF64 as should `mips64-linux-gnu-clang -mabi=64`.
Conversely, `mips64-linux-gnu-clang -mabi=n32` should produce an ELF32 as
should `mips-linux-gnu-clang -mips64r2 -mabi=n32`.
This patch fixes the e_flags but leaves the ELF32 vs ELF64 issue for now
since there is no apparent way to base this decision on the ABI and CPU.
Differential Revision: http://reviews.llvm.org/D4539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213244
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Daniel Sanders [Thu, 17 Jul 2014 09:57:23 +0000 (09:57 +0000)]
[mips] Correct .MIPS.abiflags for -mfpxx on MIPS32r6
Summary:
The cpr1_size field describes the minimum register width to run the program
rather than the size of the registers on the target. MIPS32r6 was acting
as if -mfp64 has been given because it starts off with 64-bit FPU registers.
Differential Revision: http://reviews.llvm.org/D4538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213243
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Daniel Sanders [Thu, 17 Jul 2014 09:52:56 +0000 (09:52 +0000)]
[mips] Fix ELF e_flags related to -mabicalls and -mplt.
Summary:
These options are not implemented yet but we act as if they are always
given.
The integrated assembler is driven by the clang driver so the e_flag test
cases should match the e_flags emitted by GCC+GAS rather than GAS
by itself.
Differential Revision: http://reviews.llvm.org/D4536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213242
91177308-0d34-0410-b5e6-
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Yi Kong [Thu, 17 Jul 2014 09:43:27 +0000 (09:43 +0000)]
Fix the prefix for arm64 triple
Triple.cpp still returns "arm64" as prefix for arm64 triple, causing Clang not
being able to select the correct GCCBuiltin IR.
This patch changes the value to correct prefix "aarch64". Regression test will
be added in the coming patch.
Differential Revision: http://reviews.llvm.org/D4516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213240
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Evgeniy Stepanov [Thu, 17 Jul 2014 09:10:37 +0000 (09:10 +0000)]
[msan] Avoid redundant origin stores.
Origin is meaningless for fully initialized values. Avoid
storing origin for function arguments that are known to
be always initialized (i.e. shadow is a compile-time null
constant).
This is not about correctness, but purely an optimization.
Seems to affect compilation time of blacklisted functions
significantly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213239
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Suyog Sarda [Thu, 17 Jul 2014 06:28:15 +0000 (06:28 +0000)]
Move ashr optimization from InstCombineShift to InstSimplify.
Refactor code, no functionality change, test case moved from instcombine to instsimplify.
Differential Revision: http://reviews.llvm.org/D4102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213231
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Matt Arsenault [Thu, 17 Jul 2014 06:19:06 +0000 (06:19 +0000)]
Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213230
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Matt Arsenault [Thu, 17 Jul 2014 06:13:41 +0000 (06:13 +0000)]
R600: Short circuit alloca check if address space isn't private.
Skip calling GetUnderlyingObject in cases where it obviously
isn't from an alloca. This should only be a compile time improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213229
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Suyog Sarda [Thu, 17 Jul 2014 06:09:34 +0000 (06:09 +0000)]
Fix Typo (first commit to test commit access)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213228
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Eric Fiselier [Thu, 17 Jul 2014 05:53:00 +0000 (05:53 +0000)]
[lit] Add --show-unsupported flag to LIT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213227
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Saleem Abdulrasool [Thu, 17 Jul 2014 03:08:50 +0000 (03:08 +0000)]
MC: make WinEH opcode an opaque value
This makes the opcode an opaque value (unsigned int) rather than the
enumeration. This permits the use of target specific operands.
Split out the generic type into a MCWinEH header and add a supporting
MCWin64EH::Instruction to abstract out the selection of the opcode and
construction of the actual instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213221
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