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Nicolai Haehnle [Sun, 1 Apr 2018 17:09:14 +0000 (17:09 +0000)]
AMDGPU: Make isIntrinsicSourceOfDivergence table-driven
Summary:
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: Iaa16e3a635a11283918ce0d9e1e618591b0bf6fa
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328939
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Nicolai Haehnle [Sun, 1 Apr 2018 17:09:07 +0000 (17:09 +0000)]
AMDGPU: Make getTgtMemIntrinsic table-driven for resource-based intrinsics
Summary:
Avoids having to list all intrinsics manually.
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: If7ced04998397ef68c4cb8f7de66b5050fb767e5
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328938
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Nicolai Haehnle [Sun, 1 Apr 2018 17:08:58 +0000 (17:08 +0000)]
TableGen: Support Intrinsic values in SearchableTable
Summary:
We will use this in the AMDGPU backend in a subsequent patch
in the stack to lookup target-specific per-intrinsic information.
The generic CodeGenIntrinsic machinery is used to ensure that,
even though we don't calculate actual enum values here, we do
get the intrinsics in the right order for the binary search
index.
Change-Id: If61cd5587963a4c5a1cc53df1e59c5e4dec1f9dc
Reviewers: arsenm, rampitec, b-sumner
Subscribers: wdng, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D44935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328937
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Nicolai Haehnle [Sun, 1 Apr 2018 17:08:49 +0000 (17:08 +0000)]
TableGen: More helpful error messages
Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe
Reviewers: arsenm, rampitec, b-sumner
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44936
Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328936
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Mandeep Singh Grang [Sun, 1 Apr 2018 16:18:49 +0000 (16:18 +0000)]
[DebugInfo] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: echristo, zturner, samsonov
Reviewed By: echristo
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D45134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328935
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Teresa Johnson [Sun, 1 Apr 2018 15:54:40 +0000 (15:54 +0000)]
[ThinLTO] Add an import cutoff for debugging/triaging
Summary:
Adds -import-cutoff=N which will stop importing during the thin link
after N imports. Default is -1 (no limit).
Reviewers: wmi
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D45127
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328934
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David Green [Sun, 1 Apr 2018 12:48:24 +0000 (12:48 +0000)]
[LoopRotate] Rotate loops with loop exiting latches
If a loop has a loop exiting latch, it can be profitable
to rotate the loop if it leads to the simplification of
a phi node. Perform rotation in these cases even if loop
rotate itself didnt simplify the loop to get there.
Differential Revision: https://reviews.llvm.org/D44199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328933
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Craig Topper [Sun, 1 Apr 2018 06:29:32 +0000 (06:29 +0000)]
[X86] Don't check for folding into a store when deciding if we can promote an i16 mul.
There's no RMW mul operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328931
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Craig Topper [Sun, 1 Apr 2018 06:29:28 +0000 (06:29 +0000)]
[X86] Check if the load and store are to the same pointer before preventing i16 RMW shifts and subtracts from being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328930
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Craig Topper [Sun, 1 Apr 2018 06:29:27 +0000 (06:29 +0000)]
[X86] Add test case to show failure to promote i16 subtract when the LHS is a load and the result is stored to a different address.
We mistakenly believe we might be able to fold this as a RMW operation, but that doesn't end up happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328929
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Craig Topper [Sun, 1 Apr 2018 06:29:25 +0000 (06:29 +0000)]
[X86] Allow i16 subtracts to be promoted if the load is on the LHS and its not being stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328928
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Craig Topper [Sun, 1 Apr 2018 06:29:23 +0000 (06:29 +0000)]
[X86] Add test case to show failure to promote i16 subtract because we mistakenly believe the load can be folded. NFC
The left hand side of the subtract is a load, but we cna't fold those unless we also have a store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328927
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Craig Topper [Sun, 1 Apr 2018 06:29:21 +0000 (06:29 +0000)]
[X86] Remove unneeded temporary variable. NFC
This Promote flag was alwasys set to true except in the default case. But in the default case we don't need to set PVT and can just return false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328926
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Mandeep Singh Grang [Sun, 1 Apr 2018 01:46:51 +0000 (01:46 +0000)]
[Analysis] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.
Reviewers: sanjoy, dexonsmith, hfinkel, RKSimon
Reviewed By: dexonsmith
Subscribers: david2050, llvm-commits
Differential Revision: https://reviews.llvm.org/D44944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328925
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Sanjay Patel [Sat, 31 Mar 2018 17:55:44 +0000 (17:55 +0000)]
[DAGCombine] (float)((int) f) --> ftrunc (PR36617)
fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,
so replace a pair of casts with the equivalent node. We don't have to account for
special cases (NaN, INF) because out-of-range casts are undefined.
Differential Revision: https://reviews.llvm.org/D44909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328921
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Lang Hames [Sat, 31 Mar 2018 16:01:01 +0000 (16:01 +0000)]
[llvm-rtdyld] Fix the InputFileList cl::opt description: it accepts multiple
input files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328920
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Simon Pilgrim [Sat, 31 Mar 2018 09:15:54 +0000 (09:15 +0000)]
[X86][Btver2] Add MMX_PSHUFB to the JWritePSHUFB InstRW entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328918
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Simon Pilgrim [Sat, 31 Mar 2018 09:14:14 +0000 (09:14 +0000)]
Fix trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328917
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Benjamin Kramer [Sat, 31 Mar 2018 07:41:25 +0000 (07:41 +0000)]
Unbreak the build of the go bindings after r328839.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328916
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Puyan Lotfi [Sat, 31 Mar 2018 05:48:51 +0000 (05:48 +0000)]
[MIR-Canon] Adding support for local idempotent instruction hoisting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328915
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Craig Topper [Sat, 31 Mar 2018 04:54:32 +0000 (04:54 +0000)]
[X86] Add SchedRW for PMULLD
Summary:
It seems many CPUs don't implement this instruction as well as the other vector multiplies. Often using a multi uop flow. Silvermont in particular has a 7 uop flow with 11 cycle throughput. Sandy Bridge implements it as a single uop with 5 cycle latency and 1 cycle throughput. But Haswell and later use 2 uops with 10 cycle latency and 2 cycle throughput.
This patch adds a new X86SchedWritePair we can use to tag this instruction separately. I've provided correct information for Silvermont, Btver2, and Sandy Bridge. I've removed the InstRWs for SandyBridge. I've left Haswell/Broadwell/Skylake InstRWs in place because I wasn't sure how to account for the different load latency between 128 and 256 bits. I also left Znver1 InstRWs in place because the existing values don't match Agner's spreadsheet.
I also left a FIXME in the SandyBridge model because it being used for the "generic" model is too optimistic for the 256/512-bit versions since those are multiple uops on all known CPUs.
Reviewers: RKSimon, GGanesh, courbet
Reviewed By: RKSimon
Subscribers: gchatelet, gbedwell, andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D44972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328914
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Teresa Johnson [Sat, 31 Mar 2018 00:18:08 +0000 (00:18 +0000)]
[ThinLTO] Add an option to force summary call edges cold for debugging
Summary:
Useful to selectively disable importing into specific modules for
debugging/triaging/workarounds.
Reviewers: eraman
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D45062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328909
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Fangrui Song [Fri, 30 Mar 2018 22:22:31 +0000 (22:22 +0000)]
Fix a bunch of typoes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328907
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Ekaterina Romanova [Fri, 30 Mar 2018 21:35:42 +0000 (21:35 +0000)]
Prevent data races in concurrent ThinLTO processes.
Make sure ThinLTO with caching doesn't use non-atomic writes to the cache file (to prevent data races and cache files corruption).
1. Place temp file to the same place where the caching directory is (instead of creating it the directory pointed to by TMP/TEMP variable). This will help to prevent using non-atomic rename and falling back to non-atomic "direct" write to the cache file.
2. if rename failed do not write to the cache file directly (direct write to the file is non-atomic and could cause data race conditions).
3. if cache file doesn't exist (e.g., because 'rename' failed or because some other reasons), bypass using the cache altogether.
Differential Revision: https://reviews.llvm.org/D45076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328904
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Jacob Gravelle [Fri, 30 Mar 2018 20:36:58 +0000 (20:36 +0000)]
[WebAssembly] Register wasm passes with the PassRegistry
Summary:
This exposes WebAssembly passes for use on the command line (as
arguments to -print-before and the like).
Reviewers: dschuff, sunfish
Subscribers: MatzeB, jfb, sbc100, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D45103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328901
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Krzysztof Parzyszek [Fri, 30 Mar 2018 19:46:28 +0000 (19:46 +0000)]
[Hexagon] Fix testcase
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328899
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Krzysztof Parzyszek [Fri, 30 Mar 2018 19:30:28 +0000 (19:30 +0000)]
[Hexagon] Reduce excessive indentation in .s output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328898
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Krzysztof Parzyszek [Fri, 30 Mar 2018 19:28:37 +0000 (19:28 +0000)]
[Hexagon] Avoid creating invalid offsets in packetizer
Two memory instructions with a dependency only on the address register
between the two (the first one of them being post-incrememnt) can be
packetized together after the offset on the second was updated to the
incremement value. Make sure that the new offset is valid for the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328897
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Andrea Di Biagio [Fri, 30 Mar 2018 18:53:47 +0000 (18:53 +0000)]
[X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts and
VSQRT instructions.
There were still a few AVX instructions with an incorrect number of opcodes.
These should be fixed now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328892
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Peter Collingbourne [Fri, 30 Mar 2018 18:37:55 +0000 (18:37 +0000)]
DataFlowSanitizer: wrappers of functions with local linkage should have the same linkage as the function being wrapped
This patch resolves link errors when the address of a static function is taken, and that function is uninstrumented by DFSan.
This change resolves bug 36314.
Patch by Sam Kerner!
Differential Revision: https://reviews.llvm.org/D44784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328890
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Puyan Lotfi [Fri, 30 Mar 2018 18:15:54 +0000 (18:15 +0000)]
[MIR] Adding support for Named Virtual Registers in MIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328887
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Andrea Di Biagio [Fri, 30 Mar 2018 18:15:30 +0000 (18:15 +0000)]
[X86][BtVer2] Fix the number of uOps for horizontal operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328886
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Tim Shen [Fri, 30 Mar 2018 17:51:03 +0000 (17:51 +0000)]
[NVPTX] Enable StructuredCFG for NVPTX
Summary:
Make NVPTX require structured CFG. Added a temporary flag to
"roll back" the behavior for easy deployment.
Combined with D45008, this fixes several internal Nvidia GPU test
failures that we suspect to be ptxas miscompiles (PR27738).
Reviewers: jlebar
Subscribers: jholewinski, sanjoy, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D45070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328885
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Tim Shen [Fri, 30 Mar 2018 17:51:00 +0000 (17:51 +0000)]
[BlockPlacement] Disable block placement tail duplciation in structured CFG.
Summary:
Tail duplication easily breaks the structure of CFG, e.g. duplicating on
a region entry. If the structure is intended to be preserved, then we
may want to configure tail duplication, or disable it for structured
CFG. From our benchmark results disabling it doesn't cause performance
regression.
Notice that this currently affects AMDGPU backend. In the next patch, I
also plan to turn on requiresStructuredCFG for NVPTX.
All unit tests still pass.
Reviewers: jlebar, arsenm
Subscribers: jholewinski, sanjoy, wdng, tpr, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328884
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Robert Widmann [Fri, 30 Mar 2018 17:49:53 +0000 (17:49 +0000)]
[LLVM-C] Finish exception instruction bindings - Round 2
Summary:
Previous revision caused a leak in the echo test that got caught by the ASAN bots because of missing free of the handlers array and was reverted in r328759. Resubmitting the patch with that correction.
Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors.
Test is modified from SimplifyCFG because it contains many diverse usages of these instructions.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits, vlad.tsyrklevich
Differential Revision: https://reviews.llvm.org/D45100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328883
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Zachary Turner [Fri, 30 Mar 2018 17:28:35 +0000 (17:28 +0000)]
Fix some signed / unsigned conversion problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328881
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Zachary Turner [Fri, 30 Mar 2018 17:16:50 +0000 (17:16 +0000)]
[llvm-pdbutil] Dig deeper into the PDB and DBI streams when explaining.
This will show more detail when using `llvm-pdbutil explain` on an
offset in the DBI or PDB streams. Specifically, it will dig into
individual header fields and substreams to give a more precise
description of what the byte represents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328878
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Derek Schuff [Fri, 30 Mar 2018 17:02:50 +0000 (17:02 +0000)]
[WebAssembly] Refactor tablegen for store instructions (NFC)
Summary: Add patterns similar to loads.
Differential Revision: https://reviews.llvm.org/D45064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328876
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Krzysztof Parzyszek [Fri, 30 Mar 2018 16:55:44 +0000 (16:55 +0000)]
Revert "peel loops with runtime small trip counts"
This reverts commit r328854, it breaks some Hexagon tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328875
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Stanislav Mekhanoshin [Fri, 30 Mar 2018 16:19:13 +0000 (16:19 +0000)]
[AMDGPU] Fixed some instructions latencies
Differential Revision: https://reviews.llvm.org/D45073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328874
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Sanjay Patel [Fri, 30 Mar 2018 15:42:52 +0000 (15:42 +0000)]
[SelectionDAG] Removing FABS folding from DAGCombiner
The code has bugs dealing with -0.0.
Since D44550 introduced FABS pattern folding in InstCombine,
this patch removes the now-redundant code that causes
https://bugs.llvm.org/show_bug.cgi?id=36600.
Patch by Mikhail Dvoretckii!
Differential Revision: https://reviews.llvm.org/D44683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328872
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Krzysztof Parzyszek [Fri, 30 Mar 2018 15:29:47 +0000 (15:29 +0000)]
[Hexagon] Recognize and handle :endloop01
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328870
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Krzysztof Parzyszek [Fri, 30 Mar 2018 15:09:05 +0000 (15:09 +0000)]
[Hexagon] Fix printing :mem_noshuf on compiler-generated packets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328869
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Krzysztof Parzyszek [Fri, 30 Mar 2018 14:57:01 +0000 (14:57 +0000)]
[Hexagon] Fix flags for store-related intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328868
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Andrea Di Biagio [Fri, 30 Mar 2018 14:48:08 +0000 (14:48 +0000)]
[X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds and
most vector logic instructions.
Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328867
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Krzysztof Parzyszek [Fri, 30 Mar 2018 14:34:32 +0000 (14:34 +0000)]
[Hexagon] Remove unused scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328866
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Andrea Di Biagio [Fri, 30 Mar 2018 14:29:33 +0000 (14:29 +0000)]
[X86][BtVer2] Add tests that show how ReadAfterLd is missing for some
instructions.
In the Btver2 model, there are a few InstRW overrides that don't specify a
ReadAfterLd for the register input operand.
As a result, a few AVX variants of horizontal operations and most vector logic
operations with a folded memory operand don't have a ReadAdvance info associated
to their input register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328865
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Krzysztof Parzyszek [Fri, 30 Mar 2018 14:29:15 +0000 (14:29 +0000)]
[Hexagon] Pass pointer to SelectionDAG to dump functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328864
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Andrea Di Biagio [Fri, 30 Mar 2018 13:38:37 +0000 (13:38 +0000)]
[X86] Add llvm-mca tests for r328834.
Verify that the ReadAfterLd is correctly applied to FMA and 4-ops variable blend
instructions.
As Craig pointed out in D44726, some Intel models still have to be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328861
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Andrea Di Biagio [Fri, 30 Mar 2018 11:44:48 +0000 (11:44 +0000)]
[X86] Add tests to verify the presence of "ReadAfterLd" after r328823.
This change adds a couple of tests to verify the change introduced by revision
328823 ([X86] Correct the placement of ReadAfterLd in BEXTR and BZHI).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328859
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Vlad Tsyrklevich [Fri, 30 Mar 2018 06:21:28 +0000 (06:21 +0000)]
Revert "[LLVM-C] Finish exception instruction bindings"
This reverts commit r328759. It was causing LSan failures on sanitizer-x86_64-linux-bootstrap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328858
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Michael Bedy [Fri, 30 Mar 2018 05:03:36 +0000 (05:03 +0000)]
[AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.
Summary:
The phase attempts to transform operations that extract a portion of a value
into an SDWA src operand in cases where that value is used only once. It
was not prepared for this use to be the preserved portion of a value for
dst:UNUSED_PRESERVE, resulting in a crash or assert.
This change either rejects the illegal SDWA attempt, or in the case where
dst:WORD_1 and the src_sel would be WORD_0, removes the unneeded
extract instruction.
Reviewers: arsenm, #amdgpu
Reviewed By: arsenm, #amdgpu
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D44364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328856
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Ikhlas Ajbar [Fri, 30 Mar 2018 03:32:24 +0000 (03:32 +0000)]
[Hexagon] add missing lit config file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328855
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Ikhlas Ajbar [Fri, 30 Mar 2018 03:05:34 +0000 (03:05 +0000)]
peel loops with runtime small trip counts
For Hexagon, peeling loops with small runtime trip count is beneficial for our
benchmarks. We set PeelCount in HexagonTargetInfo.cpp and we use PeelCount set
by the target for computing the desired peel count.
Differential Revision: https://reviews.llvm.org/D44880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328854
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Eli Friedman [Fri, 30 Mar 2018 00:56:03 +0000 (00:56 +0000)]
[MachineCopyPropagation] Handle COPY with overlapping source/dest.
MachineCopyPropagation::CopyPropagateBlock has a bunch of special
handling for COPY instructions. This handling assumes that COPY
instructions do not modify the source of the copy; this is wrong if
the COPY destination overlaps the source.
To fix the bug, check explicitly for this situation, and fall back to
the generic instruction handling.
This bug can't happen for most register classes because they don't
have this sort of overlap, but there are a few register classes
where this is possible. The testcase uses the AArch64 QQQQ register
class.
Differential Revision: https://reviews.llvm.org/D44911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328851
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Eugene Zelenko [Fri, 30 Mar 2018 00:47:31 +0000 (00:47 +0000)]
[IR] Fix some Clang-tidy modernize-use-auto warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328850
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Rafael Espindola [Thu, 29 Mar 2018 23:32:54 +0000 (23:32 +0000)]
Style update. NFC.
Rename 3 functions to start with lowercase letters. Don't repeat the
name in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328848
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David Blaikie [Thu, 29 Mar 2018 22:42:08 +0000 (22:42 +0000)]
Fix some layering in StripNonLineTableDebugInfo, moving its declaration from IPO.h to Utils.h to match its implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328844
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David Blaikie [Thu, 29 Mar 2018 22:35:59 +0000 (22:35 +0000)]
Remove unused header to fix layering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328842
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David Blaikie [Thu, 29 Mar 2018 22:31:39 +0000 (22:31 +0000)]
Remove unused headers to fix layering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328840
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David Blaikie [Thu, 29 Mar 2018 22:31:38 +0000 (22:31 +0000)]
llvm-c: Split Utils out of Scalar.h
To fix layering (so that Scalar.h, a libScalarOpts header, isn't
included from Utils - which libScalarOpts depends on).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328839
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David Blaikie [Thu, 29 Mar 2018 22:31:36 +0000 (22:31 +0000)]
Remove some unneeded #includes to fix layering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328838
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Craig Topper [Thu, 29 Mar 2018 22:03:05 +0000 (22:03 +0000)]
[X86] Add ReadAfterLds to some 3 src instructions
Sometimes the operand comes after the memory operand so we need 5 ReadDefaults first.
I suspect we also need to do something for the mask operand for masked avx512 instructions? I'm not sure if the mask should be ReadAfterLd or not since it can mask faults. If it shouldn't be ReadAfterLd then we're probably wrong for zero masking instructions already.
Differential Revision: https://reviews.llvm.org/D44726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328834
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Eric Christopher [Thu, 29 Mar 2018 21:59:04 +0000 (21:59 +0000)]
Typo fix: epilouge->epilogue. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328833
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Matt Arsenault [Thu, 29 Mar 2018 21:44:44 +0000 (21:44 +0000)]
AMDGPU: Fix build warning in release
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328832
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Matt Arsenault [Thu, 29 Mar 2018 21:30:06 +0000 (21:30 +0000)]
AMDGPU: Support realigning stack
While the stack access instructions don't care about
alignment > 4, some transformations on the pointer calculation
do make assumptions based on knowing the low bits of a pointer
are 0. If a stack object ends up being accessed through its
absolute address (relative to the kernel scratch wave offset),
the addressing expression may depend on the stack frame being
properly aligned. This was breaking in a testcase due to the
add->or combine.
I think some of the SP/FP handling logic is still backwards,
and overly simplistic to support all of the stack features.
Code which tries to modify the SP with inline asm for example
or variable sized objects will probably require redoing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328831
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Evgeniy Stepanov [Thu, 29 Mar 2018 21:18:17 +0000 (21:18 +0000)]
Add msan custom mapping options.
Similarly to https://reviews.llvm.org/D18865 this adds options to provide custom mapping for msan.
As discussed in http://lists.llvm.org/pipermail/llvm-dev/2018-February/121339.html
Patch by vit9696(at)avp.su.
Differential Revision: https://reviews.llvm.org/D44926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328830
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Craig Topper [Thu, 29 Mar 2018 21:03:53 +0000 (21:03 +0000)]
[X86] Remove ReadAfterLd from BMI and TBM instructions that don't have a register operand in their memory form
The memory form of these instructions only read an input from memory. They don't have any register operands.
Differential Revision: https://reviews.llvm.org/D44836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328828
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Kevin Enderby [Thu, 29 Mar 2018 20:49:24 +0000 (20:49 +0000)]
Try to fix sanitizer-x86_64-linux-fast bot due to change in r328820.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328824
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Craig Topper [Thu, 29 Mar 2018 20:41:39 +0000 (20:41 +0000)]
[X86] Correct the placement of ReadAfterLd in BEXTR and BZHI. Add dedicated SchedRW for BEXTR/BZHI.
These instructions have the memory operand before the register operand. So we need to put ReadDefault for all the load ops first. Then the ReadAfterLd
Differential Revision: https://reviews.llvm.org/D44838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328823
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Philip Reames [Thu, 29 Mar 2018 20:32:15 +0000 (20:32 +0000)]
[NFC][LICM] Rearrange checks to have the cheap bail out first
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328822
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Matt Arsenault [Thu, 29 Mar 2018 20:22:04 +0000 (20:22 +0000)]
AMDGPU: Increase default stack alignment
8 and 16-byte values are common, so increase the default
alignment to avoid realigning the stack in most functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328821
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Kevin Enderby [Thu, 29 Mar 2018 20:04:29 +0000 (20:04 +0000)]
For llvm-nm and Mach-O files that are fully stripped, special case a redacted LC_MAIN
As a further refinement on:
r328274 - For llvm-nm and Mach-O files also use function starts info in some cases when printing symbols
we want to special case a redacted LC_MAIN so it is easier to find.
rdar://
38978929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328820
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Matt Arsenault [Thu, 29 Mar 2018 19:59:28 +0000 (19:59 +0000)]
AMDGPU: Fix selection error on constant loads with < 4 byte alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328818
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Philip Reames [Thu, 29 Mar 2018 19:22:12 +0000 (19:22 +0000)]
Fix an accidental circular dependence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328816
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Mandeep Singh Grang [Thu, 29 Mar 2018 19:05:26 +0000 (19:05 +0000)]
[Mips] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: sdardis, RKSimon, dsanders, atanasyan
Reviewed By: atanasyan
Subscribers: atanasyan, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D44869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328815
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Paul Robinson [Thu, 29 Mar 2018 18:59:33 +0000 (18:59 +0000)]
Try to fix a couple tests for Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328814
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Dinar Temirbulatov [Thu, 29 Mar 2018 18:57:03 +0000 (18:57 +0000)]
[SLPVectorizer] Add tests related to PR30787, NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328813
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Zachary Turner [Thu, 29 Mar 2018 18:34:15 +0000 (18:34 +0000)]
[MSF] Default to FPM2, and always mark FPM pages allocated.
There are two FPMs in an MSF file, the idea being that for
incremental updates you can write to the alternate one and then
atomically swap them on commit. LLVM defaulted to using FPM1
on the first commit, but this differs from Microsoft's behavior
which is to default to using FPM2 on the first commit. To
eliminate some byte-level file differences, this patch changes
LLVM's default to also be FPM2.
Additionally, LLVM was trying to be "smart" about marking FPM
pages allocated. In addition to marking every page belonging
to the alternate FPM as unallocated, LLVM also marked pages at
the end of the main FPM which were not needed as unallocated.
In order to match the behavior of Microsoft-generated PDBs, we
now always mark every FPM block as allocated, regardless of
whether it is in the main FPM or the alt FPM, and regardless of
whether or not it describes blocks which are actually in the file.
This has the side benefit of simplifying our code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328812
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Zachary Turner [Thu, 29 Mar 2018 17:45:34 +0000 (17:45 +0000)]
[PDB] Print some more details when explaining MSF fields.
When we determine that a field belongs to an MSF super block or
the free page map, we wouldn't print any additional information.
With this patch, we now print the value of the field (for super
block fields) or the allocation status of the specified byte (in
the case of offsets in the FPM).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328808
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Craig Topper [Thu, 29 Mar 2018 17:21:10 +0000 (17:21 +0000)]
[IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to CodeGen layer.
Currently EVT is in the IR layer only because of Function.cpp needing a very small piece of the functionality of EVT::getEVTString(). The rest of EVT is used in codegen making CodeGen a better place for it.
The previous code converted a Type* to EVT and then called getEVTString. This was only expected to handle the primitive types from Type*. Since there only a few primitive types, we can just print them as strings directly.
Differential Revision: https://reviews.llvm.org/D45017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328806
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Paul Robinson [Thu, 29 Mar 2018 17:16:41 +0000 (17:16 +0000)]
Reapply "[DWARFv5] Emit file 0 to the line table."
DWARF v5 specifies that the root file (also given in the DW_AT_name
attribute of the compilation unit DIE) should be emitted explicitly to
the line table's list of files. This makes the line table more
independent of the .debug_info section.
We emit the new syntax only for DWARF v5 and later.
Fixes the bug found by asan. Also XFAIL the new test for Darwin, which
is stuck on DWARF v2, and fix up other tests so they stop failing on
Windows. Last but not least, don't break "clang -g" of an assembler
file that has .file directives in it.
Differential Revision: https://reviews.llvm.org/D44054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328805
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Zachary Turner [Thu, 29 Mar 2018 17:11:14 +0000 (17:11 +0000)]
[PDB] Fix a bug in the explain subcommand.
We were trying to dig into the super block fields and print a
description of the field at the specified offset, but we were
printing the wrong field due to an off-by-one-field-error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328804
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David Zarzycki [Thu, 29 Mar 2018 16:51:28 +0000 (16:51 +0000)]
[ADT] NFC: Fix bogus StringSwitch rule-of-five boilerplate
Now that 'Str' is constant, the rule-of-file logic needs updating.
Reported by: vit9696@avp.su
Reviewed by: jordan_rose@apple.com
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328803
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Zachary Turner [Thu, 29 Mar 2018 16:46:47 +0000 (16:46 +0000)]
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328802
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Zachary Turner [Thu, 29 Mar 2018 16:28:20 +0000 (16:28 +0000)]
[PDB] Add an explain subcommand.
When investigating various things, we often have a file offset
and what to know what's in the PDB at that address. For example
we may be doing a binary comparison of two LLD-generated PDBs
to look for sources of non-determinism, or we may wish to compare
an LLD-generated PDB with a Microsoft generated PDB for sources
of byte-for-byte incompatibility. In these cases, we can do a
binary diff of the two files, and once we find a mismatched byte
we can use explain to figure out what that byte is, immediately
honining in on the problem.
This patch implements this by trying to narrow the meaning of
a particular file offset down as much as possible.
Differential Revision: https://reviews.llvm.org/D44959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328799
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Haicheng Wu [Thu, 29 Mar 2018 16:01:26 +0000 (16:01 +0000)]
[JumpThreading] Don't select an edge that we know we can't thread
In r312664 (D36404), JumpThreading stopped threading edges into
loop headers. Unfortunately, I observed a significant performance
regression as a result of this change. Upon further investigation,
the problematic pattern looked something like this (after
many high level optimizations):
while (true) {
bool cond = ...;
if (!cond) {
<body>
}
if (cond)
break;
}
Now, naturally we want jump threading to essentially eliminate the
second if check and hook up the edges appropriately. However, the
above mentioned change, prevented it from doing this because it would
have to thread an edge into the loop header.
Upon further investigation, what is happening is that since both branches
are threadable, JumpThreading picks one of them at arbitrarily. In my
case, because of the way that the IR ended up, it tended to pick
the one to the loop header, bailing out immediately after. However,
if it had picked the one to the exit block, everything would have
worked out fine (because the only remaining branch would then be folded,
not thraded which is acceptable).
Thus, to fix this problem, we can simply eliminate loop headers from
consideration as possible threading targets earlier, to make sure that
if there are multiple eligible branches, we can still thread one of
the ones that don't target a loop header.
Patch by Keno Fischer!
Differential Revision: https://reviews.llvm.org/D42260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328798
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Pavel Labath [Thu, 29 Mar 2018 15:12:45 +0000 (15:12 +0000)]
.debug_names: Correctly align the AugmentationStringSize field
We should align the value of the field, not the overall section offset.
This distinction matters if one of the debug_names contributions is not
of size which is a multiple of four. The dwarf producers may choose to
emit rounded contributions, but they are not required to do so. In the
latter case, without this patch we would corrupt the parsing state, as
we would adjust the offset even if subsequent contributions contained
correctly rounded augmentation strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328796
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Andrea Di Biagio [Thu, 29 Mar 2018 14:26:56 +0000 (14:26 +0000)]
[llvm-mca] Correctly set the ReadAdvance information for register use operands.
The tool was passing the wrong operand index to method
MCSubtargetInfo::getReadAdvanceCycles(). That method requires a "UseIdx", and
not the operand index. This was found when testing X86 code where instructions
had a memory folded operand.
This patch fixes the issue and adds test read-advance-1.s to ensure that
the ReadAfterLd (a ReadAdvance of 3cy) information is correctly used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328790
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Krzysztof Parzyszek [Thu, 29 Mar 2018 13:52:46 +0000 (13:52 +0000)]
[Hexagon] Add support to handle bit-reverse load intrinsics
Patch by Sumanth Gundapaneni.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328774
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Pavel Labath [Thu, 29 Mar 2018 13:47:57 +0000 (13:47 +0000)]
.debug_names: Parse DW_IDX_die_offset as a reference
Before this patch we were parsing the attributes as section offsets, as
that is what apple_names is doing. However, this is not correct as DWARF
v5 specifies that this attribute should use the Reference form class.
This also updates all the testcases (except the ones that deliberately
pass a different form) to use the correct form class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328773
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Sjoerd Meijer [Thu, 29 Mar 2018 12:31:06 +0000 (12:31 +0000)]
[Kaleidoscope] Tiny typo fixes
Fixes for "lets" references which should be "let's" in the Kaleidoscope
tutorial.
Patch by: Robin Dupret
Differential Revision: https://reviews.llvm.org/D44990
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328772
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Simon Pilgrim [Thu, 29 Mar 2018 11:18:41 +0000 (11:18 +0000)]
[X86][SSE] Don't bother re-adding combined target shuffles to the work list
We are re-adding all the bitcasts, constant masks and target shuffles to the work list for no apparent gain.
Found while investigating adding SimplifyDemandedVectorElts to target shuffles.
Differential Revision: https://reviews.llvm.org/D44942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328771
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Sylvestre Ledru [Thu, 29 Mar 2018 09:44:09 +0000 (09:44 +0000)]
Rename llvm library from libLLVM-X.Y to libLLVM-X
Summary:
As we are only doing X.0.Z releases (not using the minor version), there is no need to keep -X.Y in the version.
Like patch https://reviews.llvm.org/D41808, I propose that we rename libLLVM-7.0svn.so to libLLVM-7svn.so
This patch will also rename downstream libraries like liblldb-7.0 to liblldb-7
Reviewers: axw, beanz, dim, hans
Reviewed By: dim, hans
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D41869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328768
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Simon Dardis [Thu, 29 Mar 2018 09:21:20 +0000 (09:21 +0000)]
[Mips] Remove dead code
I believe the role of ehDataReg has been replaced by MipsABIInfo::GetEhDataReg, thus removing the dead code.
Patch By: Wei-Ren Chen.
Reviewers: ehostunreach, sdardis
Differential Revision: https://reviews.llvm.org/D44867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328767
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David Green [Thu, 29 Mar 2018 08:48:15 +0000 (08:48 +0000)]
[LoopRotate] Restructuring LoopRotation.cpp to create Loop Rotation Pass with Loop Rotation Utility Interface
The existing LoopRotation.cpp is implemented as one of loop passes instead of
being a utility. The user cannot easily perform the loop rotation selectively
(or on demand) under different optimization level. For example, the loop
rotation is needed as part of the logic to convert a loop into a loop with
bottom test for a transformation. If the loop rotation is simply added as a
loop pass before the transformation, the pass is skipped if it is compiled at
–O0 or if it is explicitly disabled by the user, causing the compiler to
generate incorrect code. Furthermore, as a loop pass it will rotate all loops
instead of just the relevant loops.
We provide a utility interface for the loop rotation so that the loop rotation
can be called on demand. The changeset is as follows:
- Create a new file lib/Transforms/Utils/LoopRotationUtils.cpp and move the main
implementation of class LoopRotate into this file.
- Create a new file llvm/include/Transform/Utils/LoopRotationUtils.h with the
interface LoopRotation(...).
- Original LoopRotation.cpp is changed to use the utility function LoopRotation
in LoopRotationUtils.cpp. This is done in the same way community did for
mem-to-reg implementation.
Patch by Jin Lin!
Differential Revision: https://reviews.llvm.org/D44595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328766
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Benjamin Kramer [Thu, 29 Mar 2018 07:56:53 +0000 (07:56 +0000)]
[Transforms] Make sure to include the c binding header when defining c binding functions
Otherwise the definitions can't see the extern C declarations and get
name mangled, making it impossible for users to call them. This breaks
the Go bindings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328765
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Max Kazantsev [Thu, 29 Mar 2018 07:54:59 +0000 (07:54 +0000)]
[NFC] Fix meaningless assert in SCEV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328764
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Craig Topper [Thu, 29 Mar 2018 04:14:04 +0000 (04:14 +0000)]
[X86] Don't pass getRegisterName from the InstPrinters into EmitAnyX86InstComments. Just always use the function from the ATTPrinter. NFC
The IntelPrinter and the ATTPrinter produce the same strings for the same input. We already use the ATTPrinter explicitly in several other places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328762
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Robert Widmann [Thu, 29 Mar 2018 03:43:15 +0000 (03:43 +0000)]
[LLVM-C] Finish exception instruction bindings
Summary:
Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors.
Test is modified from SimplifyCFG because it contains many diverse usages of these instructions.
Reviewers: whitequark, deadalnix, echristo
Reviewed By: echristo
Subscribers: llvm-commits, harlanhaskins
Differential Revision: https://reviews.llvm.org/D44496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328759
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