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Jake Ehrlich [Mon, 27 Nov 2017 18:56:01 +0000 (18:56 +0000)]
[llvm-objcopy] Add --strip-all-gnu and change --strip-all
GNU's --strip-all doesn't strip as aggressively as it could in general.
Currently llvm-objcopy copies the exact behavoir of GNU's --strip-all.
eu-strip is used as a drop in replacement for GNU strip/objcopy in many many
places without issue. eu-strip removes non-allocated sections and keeps
.gnu.warning* sections. Because --strip-all will likely be the most widely
used stripping option we should make --strip-all as aggressive as it can safely
be. Since we have evidence from eu-strip that this is a safe option we should
allow it. For those that might still have an issue afterwards I've added
--strip-all-gnu as an exact drop in replacement for GNU's --strip-all as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319071
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Zachary Turner [Mon, 27 Nov 2017 18:48:37 +0000 (18:48 +0000)]
[BinaryStream] Support growable streams.
The existing library assumed that a stream's length would never
change. This makes some things simpler, but it's not flexible
enough for what we need, especially for writable streams where
what you really want is for each call to write to actually append.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319070
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Michal Gorny [Mon, 27 Nov 2017 18:34:52 +0000 (18:34 +0000)]
[cmake] Pass -Wl,-z,nodelete on Linux to prevent unloading
Prevent unloading shared libraries on Linux when dlclose() is called.
This is necessary since command-line option parsing API relies on
registering the global option instances in the option parser instance
which can be loaded in a different shared library.
Given that we can't reliably remove those options when a library is
unloaded, the parser ends up containing dangling references. Since glibc
has relatively complex library unloading rules, some of the LLVM
libraries can be unloaded while others (including the Support library)
stay loaded causing quite a mayhem. To reliably prevent that, just
forbid unloading all libraries -- it's a very bad idea anyway.
While the issue arguably happens only with BUILD_SHARED_LIBS, it may
affect any library reusing llvm::cl interface.
Based on patch provided Ross Hayward on https://bugs.gentoo.org/617154.
Previously hit by Fedora back in Feb 2016:
https://lists.freedesktop.org/archives/mesa-dev/2016-February/107242.html
Differential Revision: https://reviews.llvm.org/D40459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319069
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Craig Topper [Mon, 27 Nov 2017 18:25:54 +0000 (18:25 +0000)]
[X86] Remove an unused isel pattern that looked for pshufd with v4f32 type.
I don't believe our current lowering/combining would ever produce such a node. We only produce integer typed pshufds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319068
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Sanjay Patel [Mon, 27 Nov 2017 18:19:32 +0000 (18:19 +0000)]
[InstCombine] use 'auto' with 'dyn_cast'; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319067
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Craig Topper [Mon, 27 Nov 2017 18:15:14 +0000 (18:15 +0000)]
[X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.
I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319066
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Simon Pilgrim [Mon, 27 Nov 2017 18:14:18 +0000 (18:14 +0000)]
[X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with SSE_PACK/SSE_PMADD schedule classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319065
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Krzysztof Parzyszek [Mon, 27 Nov 2017 18:12:16 +0000 (18:12 +0000)]
[Hexagon] Implement HexagonSubtarget::isHVXVectorType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319064
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Craig Topper [Mon, 27 Nov 2017 18:00:49 +0000 (18:00 +0000)]
[X86] Add avx512bw command lines to vselect-packss.ll
This shows several places where we fail to use masked move or blendm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319063
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Jonas Hahnfeld [Mon, 27 Nov 2017 17:55:47 +0000 (17:55 +0000)]
Delete obsolete function mergeUseListsImpl
mergeUseLists is implemented iteratively since r243590.
Differential Revision: https://reviews.llvm.org/D40491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319061
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Craig Topper [Mon, 27 Nov 2017 17:51:55 +0000 (17:51 +0000)]
[X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over 512 bits long when AVX512 is enabled.
Similar for vXi16/vXi8 with BWI.
Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319059
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Simon Pilgrim [Mon, 27 Nov 2017 17:29:49 +0000 (17:29 +0000)]
[X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319054
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Dmitry Preobrazhensky [Mon, 27 Nov 2017 17:14:35 +0000 (17:14 +0000)]
[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433
Differential Revision: https://reviews.llvm.org/D40493
Reviewers: artem.tamazov, SamWot, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319050
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Zaara Syeda [Mon, 27 Nov 2017 17:11:03 +0000 (17:11 +0000)]
[Power9] Improvements to vector extract with variable index exploitation
This patch extends on to rL307174 to not use the power9 vector extract with
variable index instructions when extracting word element 1. For such cases,
the existing selection of MFVSRWZ provides a better sequence.
Differential Revision: https://reviews.llvm.org/D38287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319049
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Fangrui Song [Mon, 27 Nov 2017 16:59:26 +0000 (16:59 +0000)]
[XRay] Fix typo in docs. NFC
Reviewers: dberris
Differential Revision: https://reviews.llvm.org/D40461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319047
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Simon Pilgrim [Mon, 27 Nov 2017 16:43:18 +0000 (16:43 +0000)]
[X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319045
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Jonas Devlieghere [Mon, 27 Nov 2017 16:40:46 +0000 (16:40 +0000)]
[llvm-dwarfdump] Display DW_AT_high_pc as absolute value
DWARF4 relative DW_AT_high_pc values are now displayed as absolute
addresses. The relative value is only shown when explicitly dumping the
forms, i.e. in show-form or verbose mode.
```
DW_AT_low_pc (0x0000000000000049)
DW_AT_high_pc (0x00000019)
```
becomes
```
DW_AT_low_pc (0x0000000000000049)
DW_AT_high_pc (0x0000000000000062)
```
Differential revision: https://reviews.llvm.org/D40317
rdar://
35416943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319044
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Sanjay Patel [Mon, 27 Nov 2017 16:37:09 +0000 (16:37 +0000)]
[InstSimplify] use m_APFloat to simplify fcmp folds; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319043
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Sanjay Patel [Mon, 27 Nov 2017 16:08:34 +0000 (16:08 +0000)]
[InstSimplify] add fcmp with negative constant tests; NFC
This is a superset of the tests proposed with D40012 to show another potential improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319041
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Nirav Dave [Mon, 27 Nov 2017 15:28:15 +0000 (15:28 +0000)]
[DAG] Do MergeConsecutiveStores again before Instruction Selection
Summary:
Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.
Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036
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Simon Pilgrim [Mon, 27 Nov 2017 14:39:50 +0000 (14:39 +0000)]
[X86] Add INVLPGA to the existing INVLPG scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319031
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Petar Jovanovic [Mon, 27 Nov 2017 14:25:36 +0000 (14:25 +0000)]
[mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRC
Make the print format consistent with other assembler instructions.
Adding a tab character instead of space in asmstring of Ext and Ins
instructions.
Removing space around the tab character for JALRC and replacing space with
tab in JRC.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D38144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319030
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Simon Pilgrim [Mon, 27 Nov 2017 14:23:55 +0000 (14:23 +0000)]
[X86] Add scheduling tests for invlpg/invlpga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319029
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Jan Korous [Mon, 27 Nov 2017 13:42:03 +0000 (13:42 +0000)]
[Support] Fix locking of shared variable in threadpool
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319027
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Vedran Miletic [Mon, 27 Nov 2017 13:26:38 +0000 (13:26 +0000)]
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
AMDGPU backend errors with "unsupported call to function" upon
encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch
adds custom lowering to avoid that error on both R600 and SI.
Reviewers: arsenm, jvesely
Subscribers: tstellar
Differential Revision: https://reviews.llvm.org/D29942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319025
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John Brawn [Mon, 27 Nov 2017 11:29:15 +0000 (11:29 +0000)]
[CGP] Fix handling of null pointer values in optimizeMemoryInst
The current way that trivial addressing modes are detected incorrectly thinks
that null pointers are non-trivial, leading to an infinite loop where we keep
duplicating the same select. Fix this by aware of null when deciding if an
addressing mode is trivial.
Differential Revision: https://reviews.llvm.org/D40447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319019
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Max Kazantsev [Mon, 27 Nov 2017 11:20:58 +0000 (11:20 +0000)]
[NFC] Add missing unit tests for EquivalenceClasses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319018
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Simon Pilgrim [Mon, 27 Nov 2017 10:41:32 +0000 (10:41 +0000)]
[X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class
As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general).
Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes.
Differential Revision: https://reviews.llvm.org/D40351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319016
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Momchil Velikov [Mon, 27 Nov 2017 10:13:14 +0000 (10:13 +0000)]
[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb
The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to
restore LR from.
The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) +
count of the popped registers. We need to load LR from just past the last
register, hence the correct offset should be either getNumOperands() - 4 and
getNumExplicitOperands() - 2 (multiplied by 4).
Differential revision: https://reviews.llvm.org/D40305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319014
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Andrew V. Tischenko [Mon, 27 Nov 2017 09:58:00 +0000 (09:58 +0000)]
Update BTVER2 sched numbers for SSE42 string instructions.
Differential Revision: https://reviews.llvm.org/D39846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319013
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Craig Topper [Mon, 27 Nov 2017 05:52:54 +0000 (05:52 +0000)]
[SelectionDAG] Teach SplitVecRes_SETCC to call GetSplitVector if the operands have already been split.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319010
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Craig Topper [Mon, 27 Nov 2017 05:52:52 +0000 (05:52 +0000)]
[SelectionDAG] Fix function name in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319009
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Craig Topper [Sun, 26 Nov 2017 21:14:48 +0000 (21:14 +0000)]
[X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.
The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319006
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Simon Pilgrim [Sun, 26 Nov 2017 20:50:29 +0000 (20:50 +0000)]
[X86][3DNow] Add 3DNow! instruction itinerary and scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319005
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Simon Pilgrim [Sun, 26 Nov 2017 20:03:53 +0000 (20:03 +0000)]
[X86][SSE] Add SSE42 tests to the clear upper tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319003
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Simon Dardis [Sun, 26 Nov 2017 19:22:44 +0000 (19:22 +0000)]
[utils][mips] Add support for mips for update_llc_checks.py
Add support for mips, particularly skipping the matching of .frame, .(f)mask
and LLVM's usage of the .set no(reorder|at|macro) directives.
Reviewers: spatel
Differential Revision: https://reviews.llvm.org/D40268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319001
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Simon Pilgrim [Sun, 26 Nov 2017 19:22:37 +0000 (19:22 +0000)]
[X86][3DNow] Remove unused I3DNow_binop_rm/I3DNow_conv_rm templates. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319000
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Simon Pilgrim [Sun, 26 Nov 2017 17:56:07 +0000 (17:56 +0000)]
[X86][MMX] Add IIC_MMX_MOVMSK instruction itinerary class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318999
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Jatin Bhateja [Sun, 26 Nov 2017 15:08:41 +0000 (15:08 +0000)]
[SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC.
Summary:
For a given loop, getLoopLatch returns a non-null value
when a loop has only one latch block. In the modified
context adding an assertion to check that both the outgoing branches of
a terminator instruction (of latch) does not target same header.
+
few minor code reorganization.
Reviewers: jbhateja
Reviewed By: jbhateja
Subscribers: sanjoy
Differential Revision: https://reviews.llvm.org/D40460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318997
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Oren Ben Simhon [Sun, 26 Nov 2017 13:02:45 +0000 (13:02 +0000)]
Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)
Shadow stack solution introduces a new stack for return addresses only.
The HW has a Shadow Stack Pointer (SSP) that points to the next return address.
If we return to a different address, an exception is triggered.
The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP).
The intrinsics are mapped to new instruction set that implements CET mechanism.
The patch also includes initial infrastructure support for IBT.
For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
Differential Revision: https://reviews.llvm.org/D40223
Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318996
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Coby Tayree [Sun, 26 Nov 2017 09:36:41 +0000 (09:36 +0000)]
[x86][icelake]GFNI
galois field arithmetic (GF(2^8)) insns:
gf2p8affineinvqb
gf2p8affineqb
gf2p8mulb
Differential Revision: https://reviews.llvm.org/D40373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318993
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Jatin Bhateja [Sun, 26 Nov 2017 02:01:01 +0000 (02:01 +0000)]
[SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr.
Summary:
For a given loop, getLoopLatch returns a non-null value
when a loop has only one latch block. In the modified
context a check on both the outgoing branches of a terminator instruction (of latch) to same header is redundant.
Reviewers: jbhateja
Reviewed By: jbhateja
Subscribers: sanjoy
Differential Revision: https://reviews.llvm.org/D40460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318991
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David Blaikie [Sat, 25 Nov 2017 20:06:04 +0000 (20:06 +0000)]
Remove dead code
(this header is not fully implemented (the out of line function
writeTypeRecordKind is called in an inline function but never
implemented - this fails to link under modular code generation) and not
included anywhere)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318987
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Craig Topper [Sat, 25 Nov 2017 20:00:37 +0000 (20:00 +0000)]
[X86] Remove GCCBuiltin from intrinsics that are no longer used by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318986
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Craig Topper [Sat, 25 Nov 2017 18:32:43 +0000 (18:32 +0000)]
[X86] Add separate intrinsics for scalar FMA4 instructions.
Summary:
These instructions zero the non-scalar part of the lower 128-bits which makes them different than the FMA3 instructions which pass through the non-scalar part of the lower 128-bits.
I've only added fmadd because we should be able to derive all other variants using operand negation in the intrinsic header like we do for AVX512.
I think there are still some missed negate folding opportunities with the FMA4 instructions in light of this behavior difference that I hadn't noticed before.
I've split the tests so that we can use different intrinsics for scalar testing between the two. I just copied the tests split the RUN lines and changed out the scalar intrinsics.
fma4-fneg-combine.ll is a new test to make sure we negate the fma4 intrinsics correctly though there are a couple TODOs in it.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318984
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Craig Topper [Sat, 25 Nov 2017 18:09:37 +0000 (18:09 +0000)]
[X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabled. Allow gather on SKX/CNL/ICL when AVX512 is disabled by using AVX2 instructions.
Summary:
This adds a new fast gather feature bit to cover all CPUs that support fast gather that we can use independent of whether the AVX512 feature is enabled. I'm only using this new bit to qualify AVX2 codegen. AVX512 is still implicitly assuming fast gather to keep tests working and to match the scatter behavior.
Test command lines have been added for these two cases.
Reviewers: magabari, delena, RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318983
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Craig Topper [Sat, 25 Nov 2017 17:59:00 +0000 (17:59 +0000)]
[SelectionDAG] Remove some dead code from vector scalaring
Summary:
Currently ScalarizeVecRes_SETCC checks for the result type being a vector and jumps to ScalarizeVecRes_VSETCC. But if we're scalarizing a vector result, aren't we guaranteed to be looking at a vector type?
This patch deletes the current ScalarizeVecRes_SETCC and renames ScalarizeVecRes_VSETCC to ScalarizeVecRes_SETCC.
Reviewers: RKSimon, arsenm, eladcohen, zvi
Reviewed By: RKSimon
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D40452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318982
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Andrew V. Tischenko [Sat, 25 Nov 2017 10:46:53 +0000 (10:46 +0000)]
Add BTVER2 sched support for SHLD/SHRD.
Differential Revision: https://reviews.llvm.org/D40124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318977
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Craig Topper [Sat, 25 Nov 2017 07:20:24 +0000 (07:20 +0000)]
[X86] Simplify some code in combineSetCC. NFCI
Make the condition for doing a std::swap simpler so we don't have to repeat the full checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318970
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Craig Topper [Sat, 25 Nov 2017 07:20:23 +0000 (07:20 +0000)]
[X86] Qualify some vector specific code with VT.isVector(). NFCI
Other checks inside require a build_vector, but we this lets us stop earlier and makes the code more clear.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318969
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Craig Topper [Sat, 25 Nov 2017 07:20:22 +0000 (07:20 +0000)]
[X86] Support folding to andnps with SSE1 only.
With SSE1 only, we emit FAND and FXOR nodes for v4f32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318968
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Craig Topper [Sat, 25 Nov 2017 07:20:21 +0000 (07:20 +0000)]
[X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into FAND/FOR/FXOR whe only SSE1 is available.
v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise.
This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318967
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Craig Topper [Fri, 24 Nov 2017 20:29:04 +0000 (20:29 +0000)]
Recommit r318963 "[APInt] Don't print debug messages from the APInt knuth division algorithm by default"
The previous commit had the condition in the do/while backwards.
Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log.
This adds a new preprocessor flag to enable the prints in the knuth division code in APInt.
Differential Revision: https://reviews.llvm.org/D40404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318966
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Craig Topper [Fri, 24 Nov 2017 19:57:48 +0000 (19:57 +0000)]
[X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.
This optimization can occur after type legalization and emit a vselect with v4i32 type. But that type is not legal with sse1. This ultimately gets scalarized by the second type legalization that runs after vector op legalization, but that's really intended to handle the scalar types that might be introduced by legalizing vector ops.
For now just stop this from happening by disabling the optimization with sse1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318965
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Craig Topper [Fri, 24 Nov 2017 19:32:34 +0000 (19:32 +0000)]
Revert 318963 "[APInt] Don't print debug messages from the APInt knuth division algorithm by default"
I seem to have botched the logic when switching to push_macro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318964
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Craig Topper [Fri, 24 Nov 2017 19:13:24 +0000 (19:13 +0000)]
[APInt] Don't print debug messages from the APInt knuth division algorithm by default
Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log.
This adds a new preprocessor flag to enable the prints in the knuth division code in APInt.
Differential Revision: https://reviews.llvm.org/D40404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318963
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Simon Dardis [Fri, 24 Nov 2017 16:45:28 +0000 (16:45 +0000)]
[CodeGenPrepare] Check that erased sunken address are not reused
CodeGenPrepare sinks address computations from one basic block to another
and attempts to reuse address computations that have already been sunk. If
the same address computation appears twice with the first instance as an
operand of a load whose result is an operand to a simplifable select,
CodeGenPrepare simplifies the select and recursively erases the now dead
instructions. CodeGenPrepare then attempts to use the erased address
computation for the second load.
Fix this by erasing the cached address value if it has zero uses before
looking for the address value in the sunken address map.
This partially resolves PR35209.
Thanks to Alexander Richardson for reporting the issue!
This fixed version relands r318032 which was reverted in r318049 due to
sanitizer buildbot failures.
Reviewers: john.brawn
Differential Revision: https://reviews.llvm.org/D39841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318956
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Dmitry Preobrazhensky [Fri, 24 Nov 2017 15:37:14 +0000 (15:37 +0000)]
[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629
Reviewers: artem.tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D39488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318955
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Dylan McKay [Fri, 24 Nov 2017 15:36:43 +0000 (15:36 +0000)]
[AVR] Use the short form of 'clr <reg>'
r318895 made it so that the simpler instruction aliases are printed
rather than their expanded form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318954
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Benjamin Kramer [Fri, 24 Nov 2017 14:55:41 +0000 (14:55 +0000)]
Make helpers static. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318953
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Javed Absar [Fri, 24 Nov 2017 14:35:38 +0000 (14:35 +0000)]
[SCEV] : Simplify loop to range-loop.NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318952
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John Brawn [Fri, 24 Nov 2017 14:10:45 +0000 (14:10 +0000)]
[CGP] Make optimizeMemoryInst able to combine more kinds of ExtAddrMode fields
This patch extends the recent work in optimizeMemoryInst to make it able to
combine more ExtAddrMode fields than just the BaseReg.
This fixes some benchmark regressions introduced by r309397, where GVN PRE is
hoisting a getelementptr such that it can no longer be combined into the
addressing mode of the load or store that uses it.
Differential Revision: https://reviews.llvm.org/D38133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318949
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Aleksandar Beserminji [Fri, 24 Nov 2017 14:00:47 +0000 (14:00 +0000)]
[mips] Set microMIPS ASE flag
This patch fixes an issue where microMIPS ASE flag is not set
when a function has micromips attribute or when .set micromips
directive is used.
Differential Revision: https://reviews.llvm.org/D40316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318948
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Dmitry Preobrazhensky [Fri, 24 Nov 2017 13:22:38 +0000 (13:22 +0000)]
[AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility with SP3
See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329
Reviewers: arsenm, vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D40350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318947
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Benjamin Kramer [Thu, 23 Nov 2017 21:07:11 +0000 (21:07 +0000)]
[YAMLParser] Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318936
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Benjamin Kramer [Thu, 23 Nov 2017 20:57:20 +0000 (20:57 +0000)]
[YAMLParser] Don't crash on null keys in KeyValueNodes.
Found by clangd-fuzzer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318935
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Craig Topper [Thu, 23 Nov 2017 19:25:45 +0000 (19:25 +0000)]
[X86] Don't invert NewCC variable while processing the jcc/setcc/cmovcc instructions in optimizeCompareInstr.
The NewCC variable is calculated outside of the loop that processes jcc/setcc/cmovcc instructions. If we invert it during the loop it can cause an incorrect value to be used by a later iteration. Instead only read it during the loop and use a new variable to store the possibly inverted value.
Fixes PR35399.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318934
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Craig Topper [Thu, 23 Nov 2017 18:41:21 +0000 (18:41 +0000)]
[X86] Teach isel that X86ISD::CMPM_RND zeros the upper bits of the mask register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318933
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Craig Topper [Thu, 23 Nov 2017 18:41:20 +0000 (18:41 +0000)]
[X86] Remove some unneeded opcodes from getVectorMaskingNode. NFC
We never reach here with these opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318932
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Craig Topper [Thu, 23 Nov 2017 18:41:19 +0000 (18:41 +0000)]
[X86] Add X86ISD::CMPM_RND to getVectorMaskingNode to select ISD::AND instead of ISD::VSELECT
A later DAG combine will turn the VSELECT into an AND, but we have the other mask compare opcodes here so add this one too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318931
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Craig Topper [Thu, 23 Nov 2017 18:41:18 +0000 (18:41 +0000)]
[X86] Remove some dead code leftover from when i1 was a legal type. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318930
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Craig Topper [Thu, 23 Nov 2017 18:41:17 +0000 (18:41 +0000)]
[X86] Remove some dead code. NFC
AVX512 code never reaches here so we don't need to handle X86ISD::CMPM as an opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318929
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Alexander Potapenko [Thu, 23 Nov 2017 15:06:51 +0000 (15:06 +0000)]
MSan: remove an unnecessary cast. NFC for userspace instrumenetation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318923
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Simon Pilgrim [Thu, 23 Nov 2017 13:50:27 +0000 (13:50 +0000)]
[X86][SSE] Use (V)PHMINPOSUW for vXi16 SMAX/SMIN/UMAX/UMIN horizontal reductions (PR32841)
(V)PHMINPOSUW determines the UMIN element in an v8i16 input, with suitable bit flipping it can also be used for SMAX/SMIN/UMAX cases as well.
This patch matches vXi16 SMAX/SMIN/UMAX/UMIN horizontal reductions and reduces the input down to a v8i16 vector before calling (V)PHMINPOSUW.
A later patch will use this for v16i8 reductions as well (PR32841).
Differential Revision: https://reviews.llvm.org/D39729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318917
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Diana Picus [Thu, 23 Nov 2017 13:26:07 +0000 (13:26 +0000)]
[ARM GlobalISel] Support G_FDIV for s32 and s64
TableGen already generates code for selecting a G_FDIV, so we only need
to add a test.
For the legalizer and reg bank select, we do the same thing as for the
other floating point binary operations: either mark as legal if we have
a FP unit or lower to a libcall, and map to the floating point
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318915
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Ying Yi [Thu, 23 Nov 2017 13:23:21 +0000 (13:23 +0000)]
Reverted rL318911 since it broke the sanitizer-windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318914
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Ying Yi [Thu, 23 Nov 2017 12:48:41 +0000 (12:48 +0000)]
[lit] Implement non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ commands internally
Summary:
The internal shell already supports 'cd', ‘export’ and ‘echo’ commands.
This patch adds implementation of non-pipelined ‘mkdir’, ‘diff’ and ‘rm’
commands as the internal shell builtins.
Reviewers: Zachary Turner, Reid Kleckner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318911
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Diana Picus [Thu, 23 Nov 2017 12:44:20 +0000 (12:44 +0000)]
[ARM GlobalISel] Support G_FMUL for s32 and s64
TableGen already generates code for selecting a G_FMUL, so we only need
to add a test for that part.
For the legalizer and reg bank select, we do the same thing as the other
floating point binary operators: either mark as legal if we have a FP
unit or lower to a libcall, and map to the floating point registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318910
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Simon Dardis [Thu, 23 Nov 2017 12:38:04 +0000 (12:38 +0000)]
[mips] Use the delay slot filler to convert branches for microMIPSR6.
The MIPS delay slot filler converts delay slot branches into compact
forms for the MIPS ISAs which support them. For branches that compare
(in)equality with with zero, it converts them into branches with implict
zero register operands. These branches have a slightly greater range
than normal two register operands branches.
Changing the branches at this point in the pipeline offers the long
branch pass the ability to mark better judgements if a long branch
sequence is required.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D40314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318908
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Coby Tayree [Thu, 23 Nov 2017 11:15:50 +0000 (11:15 +0000)]
[x86][icelake]BITALG
2/3
vpshufbitqmb encoding
3/3
vpshufbitqmb intrinsics
Differential Revision: https://reviews.llvm.org/D40222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318904
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Alexander Potapenko [Thu, 23 Nov 2017 08:34:32 +0000 (08:34 +0000)]
[MSan] Move the access address check before the shadow access for that address
MSan used to insert the shadow check of the store pointer operand
_after_ the shadow of the value operand has been written.
This happens to work in the userspace, as the whole shadow range is
always mapped. However in the kernel the shadow page may not exist, so
the bug may cause a crash.
This patch moves the address check in front of the shadow access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318901
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George Rimar [Thu, 23 Nov 2017 06:52:44 +0000 (06:52 +0000)]
Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper."
It reported to have problems with memory sanitizers and DBUILD_SHARED_LIBS=ON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318899
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Max Kazantsev [Thu, 23 Nov 2017 06:14:39 +0000 (06:14 +0000)]
[IRCE][NFC] Add no wrap flags to no-wrapping SCEV calculation
In a lambda where we expect to have result within bounds, add respective `nsw/nuw` flags to
help SCEV just in case if it fails to figure them out on its own.
Differential Revision: https://reviews.llvm.org/D40168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318898
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Leslie Zhai [Thu, 23 Nov 2017 04:11:11 +0000 (04:11 +0000)]
Add backend name to AVR Target to enable runtime info to be fed back into TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318895
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Craig Topper [Thu, 23 Nov 2017 03:24:01 +0000 (03:24 +0000)]
[X86] Turn an if condition that should always be true into an assert. NFCI
If Values.size() == 0, we should have returned 0 or undef earlier. If it was 1, it's a splat and we already handled that too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318894
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Craig Topper [Thu, 23 Nov 2017 03:24:00 +0000 (03:24 +0000)]
[X86] Remove unnecessary check for is128BitVector. NFC
256 and 512 bit vectors were picked off earlier in the function. Lots of code between there and here already assumed 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318893
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Craig Topper [Thu, 23 Nov 2017 03:23:59 +0000 (03:23 +0000)]
[X86] Simplify some bitmasking and use llvm_unreachable to mark an impossible case. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318892
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Craig Topper [Thu, 23 Nov 2017 03:23:58 +0000 (03:23 +0000)]
[X86] Remove a ternary operator that can only ever be false. NFC
We are checking for AVX512 in an SSE1 only block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318891
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Yaxun Liu [Thu, 23 Nov 2017 03:08:51 +0000 (03:08 +0000)]
[NFC] CodeGen: Handle shift amount type in DAGTypeLegalizer::SplitInteger
This patch reverts change to X86TargetLowering::getScalarShiftAmountTy in
rL318727 and move the logic to DAGTypeLegalizer::SplitInteger.
The reason is that getScalarShiftAmountTy returns a shift amount type that
is suitable for common use cases in CodeGen. DAGTypeLegalizer::SplitInteger
is a rare situation which requires a shift amount type larger than what
getScalarShiftAmountTy. In this case, it is more reasonable to do special
handling of shift amount type in DAGTypeLegalizer::SplitInteger only. If
similar situations arises the logic may be moved to a separate function.
Differential Revision: https://reviews.llvm.org/D40320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318890
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David Blaikie [Thu, 23 Nov 2017 00:08:40 +0000 (00:08 +0000)]
Instrumentation.h: Remove dead/untested code for DFSan JIT support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318887
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Craig Topper [Wed, 22 Nov 2017 23:35:12 +0000 (23:35 +0000)]
[X86] Regenerate the vector-popcnt and vector-tzcnt tests to get BITALG CHECK linse on all functions not just the vXi16/vXi8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318885
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Evandro Menezes [Wed, 22 Nov 2017 22:48:50 +0000 (22:48 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of some loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318884
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Fedor Sergeev [Wed, 22 Nov 2017 20:59:53 +0000 (20:59 +0000)]
IR printing improvement for loop passes
Summary:
Loop-pass printing is somewhat deficient since it does not provide the
context around the loop (e.g. preheader). This context information becomes
pretty essential when analyzing transformations that move stuff out of the loop.
Extending printLoop to cover preheader and exit blocks (if any).
Reviewers: sanjoy, silvas, weimingz
Reviewed By: sanjoy
Subscribers: apilipenko, skatkov, llvm-commits
Differential Revision: https://reviews.llvm.org/D40246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318878
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:56:23 +0000 (20:56 +0000)]
[Hexagon] Implement buildVector32 and buildVector64 as utility functions
Change LowerBUILD_VECTOR to use those functions. This commit will tempora-
rily affect constant vector generation (it will generate constant-extended
values instead of non-extended combines), but the code for the general case
should be better. The constant selection part will be fixed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318877
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:55:41 +0000 (20:55 +0000)]
[Hexagon] Add patterns to select A2_combine_ll and its variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318876
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:43:00 +0000 (20:43 +0000)]
[Hexagon] Remove trailing spaces, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318875
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Paul Robinson [Wed, 22 Nov 2017 20:31:39 +0000 (20:31 +0000)]
Add a missing include found by modules bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318873
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Craig Topper [Wed, 22 Nov 2017 20:05:57 +0000 (20:05 +0000)]
[X86] Support v32i16/v64i8 CTLZ using lookup table.
Had to tweak the setcc's used by the code to use a vXi1 result type with a sign extend back to vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318871
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Craig Topper [Wed, 22 Nov 2017 20:05:54 +0000 (20:05 +0000)]
[X86] Move the BITALG setOperationAction code into the hasBWI section to match what is done for VPOPCNTDQ in the AVX512F block. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318870
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Craig Topper [Wed, 22 Nov 2017 20:05:51 +0000 (20:05 +0000)]
[X86] Sink the MGATHER setOperationActions for AVX2 into the AVX block where most of the rest of the AVX2 legalization lives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318869
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