OSDN Git Service
Craig Topper [Sat, 10 Dec 2016 19:35:39 +0000 (19:35 +0000)]
[AVX-512] Add support for lowering (v2i64 (fp_to_sint (v2f32))) to vcvttps2uqq when AVX512DQ and AVX512VL are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289335
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Craig Topper [Sat, 10 Dec 2016 19:35:36 +0000 (19:35 +0000)]
[X86] Clarify indentation. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289334
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Craig Topper [Sat, 10 Dec 2016 19:35:33 +0000 (19:35 +0000)]
[X86] Combine LowerFP_TO_SINT and LowerFP_TO_UINT. They only differ by a single boolean flag passed to a helper function. Just check the opcode and create the flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289333
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Sanjay Patel [Sat, 10 Dec 2016 17:40:47 +0000 (17:40 +0000)]
[InstSimplify] improve function name; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289332
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Simon Atanasyan [Sat, 10 Dec 2016 17:30:09 +0000 (17:30 +0000)]
[mips] Eliminate else-after-return. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289331
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Simon Pilgrim [Sat, 10 Dec 2016 17:00:00 +0000 (17:00 +0000)]
[SelectionDAG] Add ability for computeKnownBits to peek through bitcasts from 'large element' scalar/vector to 'small element' vector.
Extension to D27129 which already supported bitcasts from 'small element' vector to 'large element' scalar/vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289329
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Simon Pilgrim [Sat, 10 Dec 2016 13:45:08 +0000 (13:45 +0000)]
[X86][XOP] Add permil2ps buildvector combine test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289327
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Dylan McKay [Sat, 10 Dec 2016 12:08:19 +0000 (12:08 +0000)]
[AVR] Add a stub README file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289326
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Dylan McKay [Sat, 10 Dec 2016 11:49:07 +0000 (11:49 +0000)]
[AVR] Fix and clean up the inline assembly tests
There was a bug where we would hit an assertion if 'Q' was used as a
constraint.
I also removed hardcoded register names to prefer regexes so the tests
don't break when the register allocator changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289325
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Dylan McKay [Sat, 10 Dec 2016 11:23:16 +0000 (11:23 +0000)]
[AVR] Explicitly set the target in all CodeGen tests
This seems to have caused failures on the buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289324
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Dylan McKay [Sat, 10 Dec 2016 11:18:37 +0000 (11:18 +0000)]
[AVR] Fix an inline asm assertion which would always trigger
It looks like some time in the past, constraint codes were changed from
chars being passed around to enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289323
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Dylan McKay [Sat, 10 Dec 2016 10:51:55 +0000 (10:51 +0000)]
[AVR] Use the register scavenger when expanding 'LDDW' instructions
Summary: This gets rid of the hardcoded 'r0' that was used previously.
Reviewers: asl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289322
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Dylan McKay [Sat, 10 Dec 2016 10:16:13 +0000 (10:16 +0000)]
[AVR] Support stores to undefined pointers
This would previously trigger an assertion error in AVRISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289321
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Chandler Carruth [Sat, 10 Dec 2016 07:59:59 +0000 (07:59 +0000)]
[PM] Further broaden this test's regex as both the CGSCC and Function
inner AM proxies are now being rendered differently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289319
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Chandler Carruth [Sat, 10 Dec 2016 07:46:51 +0000 (07:46 +0000)]
[PM] Try to support the new spelling of one of the proxy names that are
showing up on the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289318
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Chandler Carruth [Sat, 10 Dec 2016 06:34:44 +0000 (06:34 +0000)]
[PM] Support invalidation of inner analysis managers from a pass over the outer IR unit.
Summary:
This never really got implemented, and was very hard to test before
a lot of the refactoring changes to make things more robust. But now we
can test it thoroughly and cleanly, especially at the CGSCC level.
The core idea is that when an inner analysis manager proxy receives the
invalidation event for the outer IR unit, it needs to walk the inner IR
units and propagate it to the inner analysis manager for each of those
units. For example, each function in the SCC needs to get an
invalidation event when the SCC gets one.
The function / module interaction is somewhat boring here. This really
becomes interesting in the face of analysis-backed IR units. This patch
effectively handles all of the CGSCC layer's needs -- both invalidating
SCC analysis and invalidating function analysis when an SCC gets
invalidated.
However, this second aspect doesn't really handle the
LoopAnalysisManager well at this point. That one will need some change
of design in order to fully integrate, because unlike the call graph,
the entire function behind a LoopAnalysis's results can vanish out from
under us, and we won't even have a cached API to access. I'd like to try
to separate solving the loop problems into a subsequent patch though in
order to keep this more focused so I've adapted them to the API and
updated the tests that immediately fail, but I've not added the level of
testing and validation at that layer that I have at the CGSCC layer.
An important aspect of this change is that the proxy for the
FunctionAnalysisManager at the SCC pass layer doesn't work like the
other proxies for an inner IR unit as it doesn't directly manage the
FunctionAnalysisManager and invalidation or clearing of it. This would
create an ever worsening problem of dual ownership of this
responsibility, split between the module-level FAM proxy and this
SCC-level FAM proxy. Instead, this patch changes the SCC-level FAM proxy
to work in terms of the module-level proxy and defer to it to handle
much of the updates. It only does SCC-specific invalidation. This will
become more important in subsequent patches that support more complex
invalidaiton scenarios.
Reviewers: jlebar
Subscribers: mehdi_amini, mcrosier, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D27197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289317
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Craig Topper [Sat, 10 Dec 2016 06:02:48 +0000 (06:02 +0000)]
[X86] Use X86ISD::CVTTP2SI and X86ISD::CVTTP2UI for lowering 128-bit cvttps2qq and cvttps2uqq intrinsics since there is a mismatch between number of input and output elements.
Ideally ISD::FP_TO_SINT and ISD::FP_TO_UINT would only be used for cases with the same number of input and output elements.
Similar things have already been done for other convert intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289316
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Dylan McKay [Sat, 10 Dec 2016 05:48:48 +0000 (05:48 +0000)]
[AVR] Fix a bunch of incorrect assertion messages
These should've been checking whether the immediate is a 6-bit unsigned
integer.
If the immediate was '63', this would cause an assertion error which
shouldn't have occurred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289315
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Kostya Serebryany [Sat, 10 Dec 2016 02:48:42 +0000 (02:48 +0000)]
[libFuzzer] test cleanup (3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289314
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Kostya Serebryany [Sat, 10 Dec 2016 02:47:00 +0000 (02:47 +0000)]
[libFuzzer] test cleanup (2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289313
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Kostya Serebryany [Sat, 10 Dec 2016 02:45:56 +0000 (02:45 +0000)]
[libFuzzer] test cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289312
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Kostya Serebryany [Sat, 10 Dec 2016 02:26:23 +0000 (02:26 +0000)]
[libFuzzer] switch all libFuzzer tests to use -fsanitize-coverage=trace-pc-guard. Support for the previosly used instrumentation will be removed in the following changes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289311
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Kostya Serebryany [Sat, 10 Dec 2016 01:19:35 +0000 (01:19 +0000)]
[libFuzzer] use __sanitizer_get_module_and_offset_for_pc to get the module name while printing the coverage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289310
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Matt Arsenault [Sat, 10 Dec 2016 00:52:50 +0000 (00:52 +0000)]
AMDGPU: Fix AMDGPUPromoteAlloca breaking addrspacecasts
The users of the addrspacecast were having their types incorrectly
changed, producing invalid bitcasts between address spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289307
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Matt Arsenault [Sat, 10 Dec 2016 00:39:12 +0000 (00:39 +0000)]
AMDGPU: Fix handling of 16-bit immediates
Since 32-bit instructions with 32-bit input immediate behavior
are used to materialize 16-bit constants in 32-bit registers
for 16-bit instructions, determining the legality based
on the size is incorrect. Change operands to have the size
specified in the type.
Also adds a workaround for a disassembler bug that
produces an immediate MCOperand for an operand that
is supposed to be OPERAND_REGISTER.
The assembler appears to accept out of bounds immediates and
truncates them, but this seems to be an issue for 32-bit
already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289306
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Matt Arsenault [Sat, 10 Dec 2016 00:29:55 +0000 (00:29 +0000)]
AMDGPU: Fix vintrp disassembly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289292
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Matt Arsenault [Sat, 10 Dec 2016 00:23:12 +0000 (00:23 +0000)]
AMDGPU: Change vintrp printing to better match sc
Some of the immediates need to be printed differently
eventually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289291
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Paul Robinson [Fri, 9 Dec 2016 23:08:17 +0000 (23:08 +0000)]
Bigger-hammer REQUIRES to fix Windows bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289288
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Eugene Zelenko [Fri, 9 Dec 2016 22:06:55 +0000 (22:06 +0000)]
[AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289282
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Paul Robinson [Fri, 9 Dec 2016 21:59:00 +0000 (21:59 +0000)]
Speculative REQUIRES to fix Windows bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289281
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Simon Pilgrim [Fri, 9 Dec 2016 21:53:12 +0000 (21:53 +0000)]
[X86] Regenerate test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289279
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Matt Arsenault [Fri, 9 Dec 2016 21:10:41 +0000 (21:10 +0000)]
AMDGPU: Cleanup checks in sext_inreg test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289272
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Adrian Prantl [Fri, 9 Dec 2016 20:43:40 +0000 (20:43 +0000)]
Fix LLVM's use of DW_OP_bit_piece in DWARF expressions.
LLVM's use of DW_OP_bit_piece is incorrect and a based on a
misunderstanding of the wording in the DWARF specification. The offset
argument of DW_OP_bit_piece refers to the offset into the location
that is on the top of the DWARF expression stack, and not an offset
into the source variable. This has since also been clarified in the
DWARF specification.
This patch fixes all uses of DW_OP_bit_piece to emit the correct
offset and simplifies the DwarfExpression class to semi-automaticaly
emit empty DW_OP_pieces to adjust the offset of the source variable,
thus simplifying the code using DwarfExpression.
While this is an incompatible bugfix, in practice I don't expect this
to be much of a problem since LLVM's old interpretation and the
correct interpretation of DW_OP_bit_piece differ only when there are
gaps in the fragmented locations of the described variables or if
individual fragments are smaller than a byte. LLDB at least won't
interpret locations with gaps in them because is has no way to present
undefined bits in a variable, and there is a high probability that an
old-form expression will be malformed when interpreted correctly,
because the DW_OP_bit_piece offset will be outside of the location at
the top of the stack.
As a nice side-effect, this patch enables us to use a more efficient
encoding for subregisters: In order to express a sub-register at a
non-zero offset we now use a DW_OP_bit_piece instead of shifting the
value into place manually.
This patch also adds missing test coverage for code paths that weren't
exercised before.
<rdar://problem/
29335809>
Differential Revision: https://reviews.llvm.org/D27550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289266
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Matthias Braun [Fri, 9 Dec 2016 20:16:12 +0000 (20:16 +0000)]
Add README describing the intention of test/CodeGen/MIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289265
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Marek Olsak [Fri, 9 Dec 2016 19:49:58 +0000 (19:49 +0000)]
AMDGPU/SI: Remove XNACK feature from CI
Summary: CI doesn't have XNACK.
Reviewers: tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289263
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Marek Olsak [Fri, 9 Dec 2016 19:49:54 +0000 (19:49 +0000)]
AMDGPU/SI: Don't reserve XNACK when it's disabled
Summary:
This frees 2 additional scalar registers.
These are results from all of my 3 patches combined:
Polaris:
Spilled SGPRs: 2231 -> 1517 (-32.00 %)
Tonga:
Spilled SGPRs: 3829 -> 2608 (-31.89 %)
Spilled VGPRs: 100 -> 84 (-16.00 %)
Tonga even spills SGPRs via VGPRs to scratch. That's a compute shader
limited to 64 VGPRs.
Reviewers: tstellarAMD
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289262
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Marek Olsak [Fri, 9 Dec 2016 19:49:48 +0000 (19:49 +0000)]
AMDGPU/SI: Don't reserve FLAT_SCR on non-HSA targets & without stack objects
Summary: This frees 2 scalar registers.
Reviewers: tstellarAMD
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289261
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Marek Olsak [Fri, 9 Dec 2016 19:49:40 +0000 (19:49 +0000)]
AMDGPU/SI: Allow using SGPRs 96-101 on VI
Summary:
There is no point in setting SGPRS=104, because VI allocates SGPRs
in multiples of 16, so 104 -> 112. That enables us to use all 102 SGPRs
for general purposes.
Reviewers: tstellarAMD
Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289260
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Reid Kleckner [Fri, 9 Dec 2016 19:20:28 +0000 (19:20 +0000)]
Remove /Zc:sizedDealloc- from the MSVC build
According to the connect bug
(https://connect.microsoft.com/VisualStudio/feedback/details/
1351894),
this was only necessary with pre-release versions of MSVC 2015.
Fixes PR23513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289257
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Paul Robinson [Fri, 9 Dec 2016 19:15:32 +0000 (19:15 +0000)]
[DWARF] Suppress .loc directives from CFI instructions
Like DBG_VALUE, these emit nothing to the .text section, and sometimes
have no source location specified. Just ignore them.
Differential Revision: http://reviews.llvm.org/D27492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289256
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Matthias Braun [Fri, 9 Dec 2016 19:08:15 +0000 (19:08 +0000)]
Move .mir tests to appropriate directories
test/CodeGen/MIR should contain tests that intent to test the MIR
printing or parsing. Tests that test something else should be in
test/CodeGen/TargetName even when they are written in .mir.
As a rule of thumb, only tests using "llc -run-pass none" should be in
test/CodeGen/MIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289254
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Matt Arsenault [Fri, 9 Dec 2016 17:57:43 +0000 (17:57 +0000)]
AMDGPU: Fix isTypeDesirableForOp for i16
This should do nothing for targets without i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289235
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Simon Pilgrim [Fri, 9 Dec 2016 17:53:11 +0000 (17:53 +0000)]
[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes (REAPPLIED)
Reapplied with fix for PR31323 - X86 SSE2 vXi16 multiplies for illegal types were creating CONCAT_VECTORS nodes with vector inputs that might not total the number of elements in the result type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289232
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Matt Arsenault [Fri, 9 Dec 2016 17:49:14 +0000 (17:49 +0000)]
AMDGPU: Fix i128 mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289231
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Matt Arsenault [Fri, 9 Dec 2016 17:49:11 +0000 (17:49 +0000)]
AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions
Fixes assembler regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289230
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Matt Arsenault [Fri, 9 Dec 2016 17:49:08 +0000 (17:49 +0000)]
AMDGPU: Clean up instruction bits
Sort the instruction bits by type and make sure there is one
for each format.
Also cleanup namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289229
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Sean Fertile [Fri, 9 Dec 2016 17:21:42 +0000 (17:21 +0000)]
[PPC] Add intrinsics for vector extract word and vector insert word.
Revision: https://reviews.llvm.org/D26547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289227
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Nirav Dave [Fri, 9 Dec 2016 17:18:24 +0000 (17:18 +0000)]
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r289221 which appears to be triggering an assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289226
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Nirav Dave [Fri, 9 Dec 2016 16:15:12 +0000 (16:15 +0000)]
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Retrying after fixing overly aggressive load-store forwarding optimization.
Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search which only checks for parallel stores
through the chain subgraph. This is cleaner as the separation of
non-interfering loads/stores from the store-merging logic.
Whem merging stores, search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited. This improves the quality of the
output SelectionDAG and generally the output CodeGen (with some
exceptions).
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the the chain aggregation in the merged stores across
code paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seemed sufficient to not cause regressions in
tests.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable. Some tests relying on the order were changed to use
volatile memory operations
Noteworthy tests:
CodeGen/AArch64/argument-blocks.ll -
It's not entirely clear what the test_varargs_stackalign test is
supposed to be asserting, but the new code looks right.
CodeGen/AArch64/arm64-memset-inline.lli -
CodeGen/AArch64/arm64-stur.ll -
CodeGen/ARM/memset-inline.ll -
The backend now generates *worse* code due to store merging
succeeding, as we do do a 16-byte constant-zero store efficiently.
CodeGen/AArch64/merge-store.ll -
Improved, but there still seems to be an extraneous vector insert
from an element to itself?
CodeGen/PowerPC/ppc64-align-long-double.ll -
Worse code emitted in this case, due to the improved store->load
forwarding.
CodeGen/X86/dag-merge-fast-accesses.ll -
CodeGen/X86/MergeConsecutiveStores.ll -
CodeGen/X86/stores-merging.ll -
CodeGen/Mips/load-store-left-right.ll -
Restored correct merging of non-aligned stores
CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll -
Improved. Correctly merges buffer_store_dword calls
CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll -
Improved. Sidesteps loading a stored value and
merges two stores
CodeGen/X86/pr18023.ll -
This test has been removed, as it was asserting incorrect
behavior. Non-volatile stores *CAN* be moved past volatile loads,
and now are.
CodeGen/X86/vector-idiv.ll -
CodeGen/X86/vector-lzcnt-128.ll -
It's basically impossible to tell what these tests are actually
testing. But, looks like the code got better due to the memory
operations being recognized as non-aliasing.
CodeGen/X86/win32-eh.ll -
Both loads of the securitycookie are now merged.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
Subscribers: wdng, nhaehnle, nemanjai, arsenm, weimingz, niravd, RKSimon, aemerson, qcolombet, dsanders, resistor, tstellarAMD, t.p.northover, spatel
Differential Revision: https://reviews.llvm.org/D14834
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289221
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Simon Pilgrim [Fri, 9 Dec 2016 16:01:50 +0000 (16:01 +0000)]
Use SelectionDAG.getSplatBuildVector helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289220
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Tom Stellard [Fri, 9 Dec 2016 15:57:15 +0000 (15:57 +0000)]
AMDGPU/SI: Don't mark VINTRP instructions as mayLoad
Summary:
These instructions technically do read from memory, but the memory
is considered to be out of bounds for normal load/store instructions.
shader-db stats:
SGPRS:
1416075 ->
1413323 (-0.19 %)
VGPRS: 867413 -> 863935 (-0.40 %)
Spilled SGPRs: 1409 -> 1354 (-3.90 %)
Spilled VGPRs: 63 -> 63 (0.00 %)
Private memory VGPRs: 880 -> 880 (0.00 %)
Scratch size: 2648 -> 2632 (-0.60 %) dwords per thread
Code Size:
37889052 ->
37897340 (0.02 %) bytes
LDS: 2147 -> 2147 (0.00 %) blocks
Max Waves: 279243 -> 280369 (0.40 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: nhaehnle, mareko, arsenm
Subscribers: kzhuravl, wdng, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D27593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289219
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Simon Pilgrim [Fri, 9 Dec 2016 15:23:41 +0000 (15:23 +0000)]
[SelectionDAG] Use SelectionDAG.getBuildVector helper. NFCI.
Makes interception of BUILD_VECTOR creation easier for debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289218
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Sanjoy Das [Fri, 9 Dec 2016 14:42:14 +0000 (14:42 +0000)]
[SCEVExpander] Remove \brief, reflow comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289216
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Sanjoy Das [Fri, 9 Dec 2016 14:42:11 +0000 (14:42 +0000)]
[SCEVExpander] Use llvm data structures; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289215
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Simon Pilgrim [Fri, 9 Dec 2016 14:27:52 +0000 (14:27 +0000)]
[SelectionDAG] Add additional checks to CONCAT_VECTORS creation
Part of the work for PR31323 - add extra asserts checking that the input vectors are of consistent type and result in the correct number of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289214
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Benjamin Kramer [Fri, 9 Dec 2016 13:33:41 +0000 (13:33 +0000)]
Plug another leak in the DWARF unittests, DIEInlineStrings are never destroyed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289208
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Benjamin Kramer [Fri, 9 Dec 2016 13:12:30 +0000 (13:12 +0000)]
Fix memory leak in unit test.
The StringPool entries are destroyed with the allocator, the string pool
itself is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289207
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NAKAMURA Takumi [Fri, 9 Dec 2016 11:44:57 +0000 (11:44 +0000)]
llvm/test/Object/archive-thin-create.test: Make sure that %t is empty to stabilize the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289202
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Dylan McKay [Fri, 9 Dec 2016 11:22:26 +0000 (11:22 +0000)]
[AVR] Remove a set of redundant tests
This fixes the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289201
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Simon Pilgrim [Fri, 9 Dec 2016 10:13:45 +0000 (10:13 +0000)]
[SelectionDAG] Add partial BITCAST support to computeKnownBits
Adds support for bitcasting a little endian 'small element' vector to 'large element' scalar/vector (e.g. v16i8 to v4i32 or v2i32 to i64), which is required for PR30845. We extract the knownbits for each 'small element' part and concatenate the results together.
We can add support for big endian and 'large element' scalar/vector to 'small element' vector bitcasting once we have test cases for them.
Differential Revision: https://reviews.llvm.org/D27129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289200
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Malcolm Parsons [Fri, 9 Dec 2016 09:33:33 +0000 (09:33 +0000)]
Update Doxygen comment in StringSaver (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289196
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Daniel Jasper [Fri, 9 Dec 2016 09:04:51 +0000 (09:04 +0000)]
Revert "[SelectionDAG] Add knownbits support for EXTRACT_VECTOR_ELT opcodes"
This reverts commit r288916 as it is currently causing a crasher in
Halide. Reproducer on llvm.org/PR31323. While it might be that halide is
generating invalid IR, llc shouldn't crash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289194
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Craig Topper [Fri, 9 Dec 2016 07:57:21 +0000 (07:57 +0000)]
[X86] Modify patterns from memory form of RCP/RSQRT/SQRT intrinsics to only allow (scalar_to_vector (loadf32/load64)) instead of anything that sse_load_f32/f64 can match.
sse_load_f32/f64 can also match loads that are zero extended to vectors. We shouldn't match that because we wouldn't be able to get the instruction to zero the upper bits like the intrinsic semantics would require for such a case.
There is a test case that does depend on this behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289193
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Dylan McKay [Fri, 9 Dec 2016 07:49:14 +0000 (07:49 +0000)]
[AVR] Use a more appropriate integer type for wide IN/OUT instructions
We could previously select an integer which would hit an assertion error
in pseudo expansion.
The new type will also generate the appropriate fixups if needed, which
wasn't done beforehand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289192
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Dylan McKay [Fri, 9 Dec 2016 07:49:04 +0000 (07:49 +0000)]
[AVR] Add tests for a large number of pseudo instructions
This adds MIR tests for 24 pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289191
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Craig Topper [Fri, 9 Dec 2016 06:42:28 +0000 (06:42 +0000)]
[AVX-512] Correctly preserve the passthru semantics of the FMA scalar intrinsics
Summary:
Scalar intrinsics have specific semantics about the which input's upper bits are passed through to the output. The same input is also supposed to be the input we use for the lower element when the mask bit is 0 in a masked operation. We aren't currently keeping these semantics with instruction selection.
This patch corrects this by introducing new scalar FMA ISD nodes that indicate whether operand 1(one of the multiply inputs) or operand 3(the additon/subtraction input) should pass thru its upper bits.
We use this information to select 213/132 form for the operand 1 version and the 231 form for the operand 3 version.
We also use this information to suppress combining FNEG operations on the passthru input since semantically the passthru bits aren't negated. This is stronger than the earlier check added for a user being SELECTS so we can remove that.
This fixes PR30913.
Reviewers: delena, zvi, v_klochkov
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289190
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Matt Arsenault [Fri, 9 Dec 2016 06:19:12 +0000 (06:19 +0000)]
AMDGPU: Select i16 instructions to VOP3 forms
These were selecting directly to the VOP2 form instead
of VOP3 like the i32 instructions. Fixes regressions in
future commits where an immediate isn't folded because it was
initially used for the second operand.
Because uniform 16-bit operations are promoted to i32, it's
difficult to get a simple testcase where this matters. Fold
failures in SIFoldOperands here tend to be hidden by commute
and fold in SIShrinkInstructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289189
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Peter Collingbourne [Fri, 9 Dec 2016 05:20:43 +0000 (05:20 +0000)]
Re-commit r289184, "Support: Use a 64-bit seek in raw_fd_ostream::seek()." with a configure-time check for lseek64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289187
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Craig Topper [Fri, 9 Dec 2016 05:20:11 +0000 (05:20 +0000)]
[X86] Add masked versions of VPERMT2* and VPERMI2* to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289186
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Peter Collingbourne [Fri, 9 Dec 2016 05:04:30 +0000 (05:04 +0000)]
Revert r289184, we need more configury for Darwin and *BSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289185
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Peter Collingbourne [Fri, 9 Dec 2016 04:57:19 +0000 (04:57 +0000)]
Support: Use a 64-bit seek in raw_fd_ostream::seek().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289184
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Davide Italiano [Fri, 9 Dec 2016 03:49:20 +0000 (03:49 +0000)]
[SCCP] Make the test added in r289175 more meaningful.
Add a comment while here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289182
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Davide Italiano [Fri, 9 Dec 2016 03:08:42 +0000 (03:08 +0000)]
[SCCP] Teach the pass about `mul %x 0` even if %x is overdefined.
The motivating example is:
extern int patatino;
int goo() {
int x = 0;
for (int i = 0; i <
1000000; ++i) {
x *= patatino;
}
return x;
}
Currently SCCP will not realize that this function returns always zero,
therefore will try to unroll and vectorize the loop at -O3 producing an
awful lot of (useless) code. With this change, it will just produce:
0000000000000000 <g>:
xor %eax,%eax
retq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289175
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Craig Topper [Fri, 9 Dec 2016 02:18:11 +0000 (02:18 +0000)]
[AVX-512] Add vpermilps/pd to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289173
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Craig Topper [Fri, 9 Dec 2016 02:18:07 +0000 (02:18 +0000)]
[AVX-512] Move some floating point stack folding test cases out of the integer test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289172
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Craig Topper [Fri, 9 Dec 2016 02:18:04 +0000 (02:18 +0000)]
[Analysis] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289171
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Kostya Serebryany [Fri, 9 Dec 2016 01:17:24 +0000 (01:17 +0000)]
[libFuzzer] implement crash-resistant merge (https://github.com/google/sanitizers/issues/722). This is a first experimental variant that needs some more testing, thus not yet adding a lit test (but there are unit tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289166
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Peter Collingbourne [Fri, 9 Dec 2016 01:10:11 +0000 (01:10 +0000)]
WholeProgramDevirt: Teach the pass to handle structs of arrays.
This will become necessary in some cases once D22296 lands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289165
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Chandler Carruth [Fri, 9 Dec 2016 00:46:44 +0000 (00:46 +0000)]
[LCG] Minor cleanup to the LCG walk over a function, NFC.
This just hoists the check for declarations up a layer which allows
various sets used in the walk to be smaller. Also moves the relevant
comments to match, and catches a few other cleanups in this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289163
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Peter Collingbourne [Fri, 9 Dec 2016 00:33:27 +0000 (00:33 +0000)]
Make WholeProgramDevirt understand ConstStruct vtables.
Based on a patch by LemonBoy!
Differential Revision: https://reviews.llvm.org/D26581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289162
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Chris Bieneman [Fri, 9 Dec 2016 00:26:44 +0000 (00:26 +0000)]
[ObjectYAML] Support for DWARF debug_aranges
This patch adds support for round tripping DWARF debug_aranges in and out of YAML.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289161
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Sanjay Patel [Thu, 8 Dec 2016 23:44:58 +0000 (23:44 +0000)]
[InstCombine] add tests for umin+icmp; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289157
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Sanjay Patel [Thu, 8 Dec 2016 23:36:57 +0000 (23:36 +0000)]
[InstCombine] add tests for umax+icmp; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289156
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Zia Ansari [Thu, 8 Dec 2016 23:27:40 +0000 (23:27 +0000)]
[InstSimplify] Add "X / 1.0" to SimplifyFDivInst.
Differential Revision: https://reviews.llvm.org/D27587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289153
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Sanjay Patel [Thu, 8 Dec 2016 23:16:06 +0000 (23:16 +0000)]
[InstCombine] add tests for smax+icmp; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289151
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Tim Northover [Thu, 8 Dec 2016 22:44:13 +0000 (22:44 +0000)]
GlobalISel: fall back gracefully for debug intrinsics.
Supporting them properly is a reasonably complex chunk of work, so to allow bot
testing before then we should at least be able to fall back to DAG ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289150
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Tim Northover [Thu, 8 Dec 2016 22:44:00 +0000 (22:44 +0000)]
GlobalISel: factor overflow handling into separate function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289149
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Davide Italiano [Thu, 8 Dec 2016 22:28:53 +0000 (22:28 +0000)]
[SCCP] Make sure SCCP and ConstantFolding agree on undef >> a.
Currently SCCP folds the value to -1, while ConstantProp folds to
0. This changes SCCP to do what ConstantFolding does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289147
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:52 +0000 (22:10 +0000)]
[mips] Make the test case more specific and provide OS component of a triple. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289117
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:48 +0000 (22:10 +0000)]
[mips] Change instruction s/daddiu/addiu/ since O32 prohibits the use of 64-bit GPRs. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289115
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:44 +0000 (22:10 +0000)]
[mips] Change gnueabi to gnu in the triple because EABI has been removed recently. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289114
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Simon Atanasyan [Thu, 8 Dec 2016 22:10:38 +0000 (22:10 +0000)]
[mips] Remove N32 Android test because Android does not support N32 ABI. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289113
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Reid Kleckner [Thu, 8 Dec 2016 20:38:46 +0000 (20:38 +0000)]
Don't emit .seh_handler directives for any cleanup funclets
We were falsely claiming that we had an LSDA for the relevant EH
personality before this change, which could lead to the EH machinery
interpreting random adjacent data as an LSDA.
Fixes PR31317
This change is safe because cleanups can't contain exception handlers
today. We do these things to maintain that invariant:
- C++ destructors are naturally out-of-line
- __finally blocks are outlined in clang
- LLVM's inliner will not inline EH constructs into cleanups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289101
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Krzysztof Parzyszek [Thu, 8 Dec 2016 20:33:45 +0000 (20:33 +0000)]
[RDF] Fix incorrect lane mask calculation
This was exposed by some code that used more than one level of sub-
registers. There is no testcase, because there is no such code in the
Hexagon backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289099
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Sanjay Patel [Thu, 8 Dec 2016 20:23:56 +0000 (20:23 +0000)]
[InstSimplify] add fdiv x/1.0 test and update checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289098
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Matt Arsenault [Thu, 8 Dec 2016 20:14:46 +0000 (20:14 +0000)]
AMDGPU: Make f16 ConstantFP legal
Not having this legal led to combine failures, resulting
in dumb things like bitcasts of constants not being folded
away.
The only reason I'm leaving the v_mov_b32 hack that f32
already uses is to avoid madak formation test regressions.
PeepholeOptimizer has an ordering issue where the immediate
fold attempt is into the sgpr->vgpr copy instead of the actual
use. Running it twice avoids that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289096
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Stanislav Mekhanoshin [Thu, 8 Dec 2016 20:07:23 +0000 (20:07 +0000)]
[AMDGPU] Fix number of reserved SGPRs on CI to reflect flat scratch use
Differential Revision: https://reviews.llvm.org/D27225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289095
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Matt Arsenault [Thu, 8 Dec 2016 19:52:38 +0000 (19:52 +0000)]
AMDGPU: Fix commuting v_sub_u16
The correct commutable opcode was set to itself, so this
was simply swapping the operands to commute instead of also
changing the opcode to v_subrev_u16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289093
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Stanislav Mekhanoshin [Thu, 8 Dec 2016 19:46:04 +0000 (19:46 +0000)]
[AMDGPU] Add amdgpu-unify-metadata pass
Multiple metadata values for records such as opencl.ocl.version, llvm.ident
and similar are created after linking several modules. For some of them, notably
opencl.ocl.version, this creates semantic problem because we cannot tell which
version of OpenCL the composite module conforms.
Moreover, such repetitions of identical values often create a huge list of
unneeded metadata, which grows bitcode size both in memory and stored on disk.
It can go up to several Mb when linked against our OpenCL library. Lastly, such
long lists obscure reading of dumped IR.
The pass unifies metadata after linking.
Differential Revision: https://reviews.llvm.org/D25381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289092
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Peter Collingbourne [Thu, 8 Dec 2016 19:01:00 +0000 (19:01 +0000)]
IR, X86: Understand !absolute_symbol metadata on global variables.
Summary:
Attaching !absolute_symbol to a global variable does two things:
1) Marks it as an absolute symbol reference.
2) Specifies the value range of that symbol's address.
Teach the X86 backend to allow absolute symbols to appear in place of
immediates by extending the relocImm and mov64imm32 matchers. Start using
relocImm in more places where it is legal.
As previously proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-October/105800.html
Differential Revision: https://reviews.llvm.org/D25878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289087
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