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Fangrui Song [Mon, 24 Jun 2019 10:23:47 +0000 (10:23 +0000)]
[sancov] Avoid unnecessary unique_ptr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364175
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Simon Tatham [Mon, 24 Jun 2019 10:00:39 +0000 (10:00 +0000)]
[ARM] Add MVE interleaving load/store family.
This adds the family of loads and stores with names like VLD20.8 and
VST42.32, which load and store parts of multiple q-registers in such a
way that executing both VLD20 and VLD21, or all four of VLD40..VLD43,
will distribute 2 or 4 vectors' worth of memory data across the lanes
of the same number of registers but in a transposed order.
In addition to the Tablegen descriptions of the instructions
themselves, this patch also adds encode and decode support for the
QQPR and QQQQPR register classes (representing the range of loaded or
stored vector registers), and tweaks to the parsing system for lists
of vector registers to make it return the right format in this case
(since, unlike NEON, MVE regards q-registers as primitive, and not
just an alias for two d-registers).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364172
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James Henderson [Mon, 24 Jun 2019 09:53:02 +0000 (09:53 +0000)]
[docs][llvm-nm] Improve symbol code documentation
The existing symbol code documentation was very incomplete. This patch
adds the missing codes, and defines them based on the current code
behaviour.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42231.
Reviewed by: rupprecht, mtrent, MaskRay
Differential Revision: https://reviews.llvm.org/D63327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364171
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Pavel Labath [Mon, 24 Jun 2019 09:11:24 +0000 (09:11 +0000)]
[Support] Fix error handling in DataExtractor::get[US]LEB128
Summary:
These functions are documented as not modifying the offset argument if
the extraction fails (just like other DataExtractor functions). However,
while reviewing D63591 we discovered that this is not the case -- if the
function reaches the end of the data buffer, it will just return the
value parsed until that point and set offset to point to the end of the
buffer.
This fixes the functions to act as advertised, and adds a regression
test.
Reviewers: dblaikie, probinson, bkramer
Subscribers: kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364169
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Sjoerd Meijer [Mon, 24 Jun 2019 08:44:29 +0000 (08:44 +0000)]
Follow up of rL363913. NFC.
Minor reshuffle in AArch64 targetparser unittest, solving a potential problem
with querying iterators too early.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364168
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George Rimar [Mon, 24 Jun 2019 08:29:54 +0000 (08:29 +0000)]
[llvm-readobj/llvm-readelf] - Eliminate the elf-groups.x86_64 precompiled binary from the inputs.
We do not need the elf-groups.x86_64. In one of the tests, it was
used for no solid reason, and for the second test case we can use
YAML input with SHT_GROUP sections.
The patch performs a cleanup of one of the test cases, removes another
one completely (since during the review was found out it actually
duplicates one of the existent tests) and removes the precompiled binary.
Differential revision: https://reviews.llvm.org/D63647
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364167
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Craig Topper [Sun, 23 Jun 2019 23:51:21 +0000 (23:51 +0000)]
[X86] Turn v16i16->v16i8 truncate+store into a any_extend+truncstore if we avx512f, but not avx512bw.
Ideally we'd be able to represent this truncate as a any_extend to
v16i32 and a truncate, but SelectionDAG doens't know how to not
fold those together.
We have isel patterns to use a vpmovzxwd+vpdmovdb for the truncate,
but we aren't able to simultaneously fold the load and the store
from the isel pattern. By pulling the truncate into the store we
can successfully hide it from the DAG combiner. Then we can isel
pattern match the truncstore and load+any_extend separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364163
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Petr Hosek [Sun, 23 Jun 2019 23:12:10 +0000 (23:12 +0000)]
[GN] Generation failure caused by trailing space in file name
When I executed gn.py gen out/gn I got the following error:
ERROR at //compiler-rt/lib/builtins/BUILD.gn:162:7: Only source, header, and object files belong in the sources of a static_library. //compiler-rt/lib/builtins/emutls.c is not one of the valid types.
"emutls.c ",
^----------
See //compiler-rt/lib/BUILD.gn:3:5: which caused the file to be included.
"//compiler-rt/lib/builtins",
^---------------------------
It turns out to be that the latest gn doesn't accept ill-format file name. And the emutls.c above has a trailing space.
Remove the trailing space should work.
Patch By: myhsu
Differential Revision: https://reviews.llvm.org/D63449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364162
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Sanjoy Das [Sun, 23 Jun 2019 19:22:13 +0000 (19:22 +0000)]
Fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364159
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Craig Topper [Sun, 23 Jun 2019 19:17:50 +0000 (19:17 +0000)]
[X86] Fix isel pattern that was looking for a bitcasted load. Remove what appears to be a copy/paste mistake.
DAG combine should ensure bitcasts of loads don't exist.
Also remove 3 patterns that are identical to the block above them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364158
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Philip Reames [Sun, 23 Jun 2019 17:13:53 +0000 (17:13 +0000)]
[Tests] Autogen and improve test readability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364156
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Philip Reames [Sun, 23 Jun 2019 17:06:57 +0000 (17:06 +0000)]
[IndVars] Remove dead instructions after folding trivial loop exit
In rL364135, I taught IndVars to fold exiting branches in loops with a zero backedge taken count (i.e. loops that only run one iteration). This extends that to eliminate the dead comparison left around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364155
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Fangrui Song [Sun, 23 Jun 2019 16:05:29 +0000 (16:05 +0000)]
SlotIndexes: delete unused functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364154
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Sanjay Patel [Sun, 23 Jun 2019 14:22:37 +0000 (14:22 +0000)]
[InstCombine] squash is-power-of-2 that uses ctpop
This is another intermediate IR step towards solving PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
We can test if a value is power-of-2-or-0 using ctpop(X) < 2,
so combining that with a non-zero check of the input is the
same as testing if exactly 1 bit is set:
(X != 0) && (ctpop(X) u< 2) --> ctpop(X) == 1
Differential Revision: https://reviews.llvm.org/D63660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364153
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Fangrui Song [Sun, 23 Jun 2019 13:16:03 +0000 (13:16 +0000)]
SlotIndexes: simplify IdxMBBPair operators
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364152
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Craig Topper [Sun, 23 Jun 2019 07:00:46 +0000 (07:00 +0000)]
[SelectionDAG] Remove the code that attempts to calculate the alignment for the second half of a split masked load/store.
The code divides the alignment by 2 if the original alignment is
equal to the original VT size. But this wouldn't be correct
if the alignment was larger than the VT size.
The memory operand object already takes care of calling MinAlign
on the base alignment and the memory pointer offset. So we don't
need any special code at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364151
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Craig Topper [Sun, 23 Jun 2019 06:06:04 +0000 (06:06 +0000)]
[X86][SelectionDAG] Cleanup and simplify masked_load/masked_store in tablegen. Use more precise PatFrags for scalar masked load/store.
Rename masked_load/masked_store to masked_ld/masked_st to discourage
their direct use. We need to check truncating/extending and
compressing/expanding before using them. This revealed that
our scalar masked load/store patterns were misusing these.
With those out of the way, renamed masked_load_unaligned and
masked_store_unaligned to remove the "_unaligned". We didn't
check the alignment anyway so the name was somewhat misleading.
Make the aligned versions inherit from masked_load/store instead
from a separate identical version. Merge the 3 different alignments
PatFrags into a single version that uses the VT from the SDNode to
determine the size that the alignment needs to match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364150
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Keno Fischer [Sun, 23 Jun 2019 00:29:59 +0000 (00:29 +0000)]
[Support] Fix build under Emscripten
Summary:
Emscripten's libc doesn't define MNT_LOCAL, thus causing a build
failure in the fallback path. However, to the best of my knowledge,
it also doesn't support remote file system mounts, so we may simply
return `true` here (as we do for e.g. Fuchsia). With this fix, the
core LLVM libraries build correctly under emscripten (though some
of the tools and utils do not).
Reviewers: kripken
Differential Revision: https://reviews.llvm.org/D63688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364143
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Don Hinton [Sat, 22 Jun 2019 23:32:36 +0000 (23:32 +0000)]
Revert [CommandLine] Remove OptionCategory and SubCommand caches from the Option class.
This reverts r364134 (git commit
a5b83bc9e3b8e8945b55068c762bd6c73621a4b0)
Caused errors in the asan bot, so the GeneralCategory global needs to
be changed to ManagedStatic.
Differential Revision: https://reviews.llvm.org/D62105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364141
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Simon Pilgrim [Sat, 22 Jun 2019 17:57:01 +0000 (17:57 +0000)]
[X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vselect(extract_subvector(x,0),extract_subvector(y,0),extract_subvector(z,0))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364136
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Philip Reames [Sat, 22 Jun 2019 17:54:25 +0000 (17:54 +0000)]
Exploit a zero LoopExit count to eliminate loop exits
This turned out to be surprisingly effective. I was originally doing this just for completeness sake, but it seems like there are a lot of cases where SCEV's exit count reasoning is stronger than it's isKnownPredicate reasoning.
Once this is in, I'm thinking about trying to build on the same infrastructure to eliminate provably untaken checks. There may be something generally interesting here.
Differential Revision: https://reviews.llvm.org/D63618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364135
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Don Hinton [Sat, 22 Jun 2019 17:22:50 +0000 (17:22 +0000)]
[CommandLine] Remove OptionCategory and SubCommand caches from the Option class.
Summary:
This change processes `OptionCategory`s and `SubCommand`s as they
are seen instead of caching them in the Option class and processing
them later. Doing so simplifies the work needed to be done by the Global
parser and significantly reduces the size of the Option class to a mere 64
bytes.
Removing the `OptionCategory` cache saved 24 bytes, and removing
the `SubCommand` cache saved an additional 48 bytes, for a total of a
72 byte reduction.
Reviewers: beanz, zturner, MaskRay, serge-sans-paille
Reviewed By: serge-sans-paille
Subscribers: serge-sans-paille, tstellar, zturner, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364134
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Hubert Tong [Sat, 22 Jun 2019 16:03:29 +0000 (16:03 +0000)]
[NFC] Fix indentation in PPCAsmPrinter.cpp
After r248261, the indentation switches, inside a namespace definition,
between indenting and not indenting one level in for that namespace; the
abomination occurs in the middle of a class definition. Fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364133
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Hubert Tong [Sat, 22 Jun 2019 16:02:02 +0000 (16:02 +0000)]
[PowerPC][NFC] Move comment to the relevant function
A comment that applies to a virtual destructor was placed on a class
constructor. Move the comment to where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364132
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Nico Weber [Sat, 22 Jun 2019 11:23:01 +0000 (11:23 +0000)]
PDB docs: Delete trailing whitespace, wrap to 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364131
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Nikita Popov [Sat, 22 Jun 2019 10:20:13 +0000 (10:20 +0000)]
[NewGVN] Fix copy/paste mistake in cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364130
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Nikita Popov [Sat, 22 Jun 2019 10:20:07 +0000 (10:20 +0000)]
[NewGVN] Remove dead SwitchEdges variable; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364129
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Nikita Popov [Sat, 22 Jun 2019 09:57:59 +0000 (09:57 +0000)]
[LFTR] Add tests for PR41998; NFC
The limit for the pointer case is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364128
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Peter Collingbourne [Sat, 22 Jun 2019 03:03:25 +0000 (03:03 +0000)]
AArch64: Add support for reading pc using llvm.read_register.
This is useful for allowing code to efficiently take an address
that can be later mapped onto debug info. Currently the hwasan
pass achieves this by taking the address of the current function:
http://llvm-cs.pcc.me.uk/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp#921
but this costs two instructions (plus a GOT entry in PIC code) per function
with stack variables. This will allow the cost to be reduced to a single
instruction.
Differential Revision: https://reviews.llvm.org/D63471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364126
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Fangrui Song [Sat, 22 Jun 2019 01:50:21 +0000 (01:50 +0000)]
[CMake] Delete redundant DEPENDS/LINK_LIBS from LineEditor/XRay
The link dependencies are already specified in LLVMBuild.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364125
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Fangrui Song [Sat, 22 Jun 2019 01:30:17 +0000 (01:30 +0000)]
Make GlobalISel depend on SelectionDAG after D63169
GlobalISel/IRTranslator.cpp now references SelectionDAG/FunctionLoweringInfo.cpp.
This fixes a link error in -DBUILD_SHARED_LIBS=on builds:
ld.lld: error: undefined symbol: llvm::FunctionLoweringInfo::clear()
>>> referenced by IRTranslator.cpp:2198 (../lib/CodeGen/GlobalISel/IRTranslator.cpp:2198)
>>> lib/CodeGen/GlobalISel/CMakeFiles/LLVMGlobalISel.dir/IRTranslator.cpp.o:(llvm::IRTranslator::finalizeFunction())
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364124
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Douglas Yung [Sat, 22 Jun 2019 01:14:29 +0000 (01:14 +0000)]
Fix UNSUPPORTED attribute from windows to system-windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364122
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Yuanfang Chen [Sat, 22 Jun 2019 01:13:04 +0000 (01:13 +0000)]
[llvm-objdump] Allow --disassemble-functions to take demangled names
The --disassemble-functions switch takes demangled names when
--demangle is specified, otherwise the switch takes mangled names.
https://bugs.llvm.org/show_bug.cgi?id=41908
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Differential Revision: https://reviews.llvm.org/D63524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364121
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Yuanfang Chen [Sat, 22 Jun 2019 00:22:57 +0000 (00:22 +0000)]
[llvm-objdump] Move --start-address >= --stop-address check out of the
-d code.
Summary:
Move it into `main` function so the checking is effective for all actions
user may do with llvm-objdump; notably, -r and -s in addition to existing -d.
Match GNU behavior.
Reviewers: jhenderson, grimar, MaskRay, rupprecht
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364118
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Peter Collingbourne [Sat, 22 Jun 2019 00:06:51 +0000 (00:06 +0000)]
AArch64: Prefer FP-relative debug locations in HWASANified functions.
To help produce better diagnostics for stack use-after-return, we'd like
to be able to determine the addresses of each HWASANified function's local
variables given a small amount of information recorded on entry to the
function. Currently we require all HWASANified functions to use frame pointers
and record (PC, FP) on function entry. This works better than recording SP
because FP cannot change during the function, unlike SP which can change
e.g. due to dynamic alloca.
However, most variables currently end up using SP-relative locations in their
debug info. This prevents us from recomputing the address of most variables
because the distance between SP and FP isn't recorded in the debug info. To
address this, make the AArch64 backend prefer FP-relative debug locations
when producing debug info for HWASANified functions.
Differential Revision: https://reviews.llvm.org/D63300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364117
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Peter Collingbourne [Sat, 22 Jun 2019 00:03:53 +0000 (00:03 +0000)]
gn build: Merge r364046.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364116
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Tom Tan [Fri, 21 Jun 2019 23:38:05 +0000 (23:38 +0000)]
[COFF, ARM64] Fix encoding of debugtrap for Windows
On Windows ARM64, intrinsic __debugbreak is compiled into brk #0xF000 which is
mapped to llvm.debugtrap in Clang. Instruction brk #F000 is the defined break
point instruction on ARM64 which is recognized by Windows debugger and
exception handling code, so llvm.debugtrap should map to it instead of
redirecting to llvm.trap (brk #1) as the default implementation.
Differential Revision: https://reviews.llvm.org/D63635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364115
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Reid Kleckner [Fri, 21 Jun 2019 23:10:25 +0000 (23:10 +0000)]
Revert [SLP] Look-ahead operand reordering heuristic.
This reverts r364084 (git commit
5698921be2d567f6abf925479ac9f5a376d6d74f)
It caused crashes while compiling a file in Chrome. Reduction
forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364111
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Shoaib Meenai [Fri, 21 Jun 2019 21:59:01 +0000 (21:59 +0000)]
[llvm-lipo] Implement -thin
Creates thin output file of specified arch_type from the fat input file.
Patch by Anusha Basana <anushabasana@fb.com>
Differential Revision: https://reviews.llvm.org/D63341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364107
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Julian Lettner [Fri, 21 Jun 2019 21:01:39 +0000 (21:01 +0000)]
[ASan] Use dynamic shadow on 32-bit iOS and simulators
The VM layout on iOS is not stable between releases. On 64-bit iOS and
its derivatives we use a dynamic shadow offset that enables ASan to
search for a valid location for the shadow heap on process launch rather
than hardcode it.
This commit extends that approach for 32-bit iOS plus derivatives and
their simulators.
rdar://
50645192
rdar://
51200372
rdar://
51767702
Reviewed By: delcypher
Differential Revision: https://reviews.llvm.org/D63586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364105
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Craig Topper [Fri, 21 Jun 2019 20:16:26 +0000 (20:16 +0000)]
[X86] Add test cases for incorrect shrinking of volatile vector loads from 128-bits to 32 or 64 bits. NFC
This is caused by isel patterns that look for vzmovl+load and
treat it the same as vzload.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364101
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Matt Arsenault [Fri, 21 Jun 2019 20:04:02 +0000 (20:04 +0000)]
AMDGPU: Fix not using s33 for scratch wave offset in kernels
Fixes missing piece from r363990.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364099
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Craig Topper [Fri, 21 Jun 2019 19:10:21 +0000 (19:10 +0000)]
[X86] Add DAG combine to turn (vzmovl (insert_subvector undef, X, 0)) into (insert_subvector allzeros, (vzmovl X), 0)
128/256 bit scalar_to_vectors are canonicalized to (insert_subvector undef, (scalar_to_vector), 0). We have isel patterns that try to match this pattern being used by a vzmovl to use a 128-bit instruction and a subreg_to_reg.
This patch detects the insert_subvector undef portion of this and pulls it through the vzmovl, creating a narrower vzmovl and an insert_subvector allzeroes. We can then match the insertsubvector into a subreg_to_reg operation by itself. Then we can fall back on existing (vzmovl (scalar_to_vector)) patterns.
Note, while the scalar_to_vector case is the motivating case I didn't restrict to just that case. I'm also wondering about shrinking any 256/512 vzmovl to an extract_subvector+vzmovl+insert_subvector(allzeros) but I fear that would have bad implications to shuffle combining.
I also think there is more canonicalization we can do with vzmovl with loads or scalar_to_vector with loads to create vzload.
Differential Revision: https://reviews.llvm.org/D63512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364095
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Craig Topper [Fri, 21 Jun 2019 18:50:00 +0000 (18:50 +0000)]
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types.
We don't have any Custom handling during type legalization. Only
operation legalization.
Fixes PR42355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364093
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Craig Topper [Fri, 21 Jun 2019 18:49:42 +0000 (18:49 +0000)]
[X86] Add avx512bw command lines to avx512-select.ll
Prep for fixing PR42355 and ensuring we have coverage of
ISD::SELECT for v64i8/v32i16 on KNL and SKX configs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364092
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Craig Topper [Fri, 21 Jun 2019 18:49:21 +0000 (18:49 +0000)]
[X86] Add a debug print of the node in the default case for unhandled opcodes in ReplaceNodeResults.
This should be unreachable, but bugs can make it reachable. This
adds a debug print so we can see the bad node in the output when
the llvm_unreachable triggers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364091
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Simon Pilgrim [Fri, 21 Jun 2019 18:35:04 +0000 (18:35 +0000)]
[X86][AVX] Combine INSERT_SUBVECTOR(SRC0, EXTRACT_SUBVECTOR(SRC1)) as shuffle
Subvector shuffling often ends up as insert/extract subvector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364090
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Amara Emerson [Fri, 21 Jun 2019 18:10:41 +0000 (18:10 +0000)]
[AArch64][GlobalISel] Implement selection support for the new G_JUMP_TABLE and G_BRJT ops.
With this we can now fully code generate jump tables, which is important for code size.
Differential Revision: https://reviews.llvm.org/D63223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364086
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Amara Emerson [Fri, 21 Jun 2019 18:10:38 +0000 (18:10 +0000)]
[GlobalISel][IRTranslator] Change switch table translation to generate jump tables and range checks.
This change makes use of the newly refactored SwitchLoweringUtils code from
SelectionDAG to in order to generate jump tables and range checks where appropriate.
Much of this code is ported from SDAG with some modifications. We generate
G_JUMP_TABLE and G_BRJT instructions when JT opportunities are found. This means
that targets which previously relied on the naive one MBB per case stmt
translation will now start falling back until they add support for the new opcodes.
For range checks, we don't generate any previously unused operations. This
just recognizes contiguous ranges of case values and generates a single block per
range. Single case value blocks are just a special case of ranges so we get that
support almost for free.
There are still some optimizations missing that I haven't ported over, and
bit-tests are also unimplemented. This patch series is already complex enough.
Actual arm64 support for selection of jump tables is coming in a later patch.
Differential Revision: https://reviews.llvm.org/D63169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364085
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Simon Pilgrim [Fri, 21 Jun 2019 17:57:01 +0000 (17:57 +0000)]
[SLP] Look-ahead operand reordering heuristic.
This patch introduces a new heuristic for guiding operand reordering. The new "look-ahead" heuristic can look beyond the immediate predecessors. This helps break ties when the immediate predecessors have identical opcodes (see lit test for an example).
Committed on behalf of @vporpo (Vasileios Porpodas)
Differential Revision: https://reviews.llvm.org/D60897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364084
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David Bolvansky [Fri, 21 Jun 2019 17:51:18 +0000 (17:51 +0000)]
[NFC] Update shl-sub tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364083
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Sanjay Patel [Fri, 21 Jun 2019 17:44:09 +0000 (17:44 +0000)]
[InstCombine] add tests for ctpop folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364082
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Craig Topper [Fri, 21 Jun 2019 17:24:21 +0000 (17:24 +0000)]
[X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl.
We already use vmovq for v2i64/v2f64 vzmovl. But we were using a
blendpd+xorpd for v4i64/v4f64/v8i64/v8f64 under opt speed. Or
movsd+xorpd under optsize.
I think the blend with 0 or movss/d is only needed for
vXi32 where we don't have an instruction that can move 32
bits from one xmm to another while zeroing upper bits.
movq is no worse than blendpd on any known CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364079
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Simon Pilgrim [Fri, 21 Jun 2019 16:44:51 +0000 (16:44 +0000)]
[DAGCombine] narrowExtractedVectorBinOp - pull out repeated getOpcode(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364076
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Amara Emerson [Fri, 21 Jun 2019 16:43:50 +0000 (16:43 +0000)]
[AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal.
We sometimes get poor code size because constants of types < 32b are legalized
as 32 bit G_CONSTANTs with a truncate to fit. This works but means that the
localizer can no longer sink them (although it's possible to extend it to do so).
On AArch64 however s8 and s16 constants can be selected in the same way as s32
constants, with a mov pseudo into a W register. If we make s8 and s16 constants
legal then we can avoid unnecessary truncates, they can be CSE'd, and the
localizer can sink them as normal.
There is a caveat: if the user of a smaller constant has to widen the sources,
we end up with an anyext of the smaller typed G_CONSTANT. This can cause
regressions because of the additional extend and missed pattern matching. To
remedy this, there's a new artifact combiner to generate the wider G_CONSTANT
if it's legal for the target.
Differential Revision: https://reviews.llvm.org/D63587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364075
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Stanislav Mekhanoshin [Fri, 21 Jun 2019 16:30:14 +0000 (16:30 +0000)]
[AMDGPU] hazard recognizer for fp atomic to s_denorm_mode
This requires 3 wait states unless there is a wait or VALU in
between.
Differential Revision: https://reviews.llvm.org/D63619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364074
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David Bolvansky [Fri, 21 Jun 2019 16:25:32 +0000 (16:25 +0000)]
[InstCombine] (1 << (C - x)) -> ((1 << C) >> x) if C is bitwidth - 1
Summary:
```
%a = sub i32 31, %x
%r = shl i32 1, %a
=>
%d = shl i32 1, 31
%r = lshr i32 %d, %x
Done: 1
Optimization is correct!
```
https://rise4fun.com/Alive/btZm
Reviewers: spatel, lebedev.ri, nikic
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364073
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Simon Pilgrim [Fri, 21 Jun 2019 16:23:28 +0000 (16:23 +0000)]
[X86] isBinOp - move commutative ops to isCommutativeBinOp. NFCI.
TargetLoweringBase::isBinOp checks isCommutativeBinOp as a fallback, so don't duplicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364072
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David Bolvansky [Fri, 21 Jun 2019 16:14:13 +0000 (16:14 +0000)]
[NFC] Added more tests for D63652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364069
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Simon Pilgrim [Fri, 21 Jun 2019 16:11:18 +0000 (16:11 +0000)]
Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364068
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David Bolvansky [Fri, 21 Jun 2019 15:26:22 +0000 (15:26 +0000)]
[InstCombine] cttz(abs(x)) -> cttz(x)
Summary: Signedness does not change number of trailing zeros.
Reviewers: spatel, lebedev.ri, nikic
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D63546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364064
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Sanjay Patel [Fri, 21 Jun 2019 15:17:24 +0000 (15:17 +0000)]
[GVNSink] prevent crashing on mismatched instructions (PR42346)
Patch based on suggestion by James Molloy (@jmolloy) in:
https://bugs.llvm.org/show_bug.cgi?id=42346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364062
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David Bolvansky [Fri, 21 Jun 2019 15:00:31 +0000 (15:00 +0000)]
[NFC] Added tests for (1 << (C - x)) -> ((1 << C) >> x)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364060
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Simon Pilgrim [Fri, 21 Jun 2019 14:46:21 +0000 (14:46 +0000)]
[DAGCombine] narrowInsertExtractVectorBinOp - reuse "extract from insert" detection code.
Move the "extract from insert detection code" into a lambda helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364059
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James Henderson [Fri, 21 Jun 2019 14:41:36 +0000 (14:41 +0000)]
[docs][llvm-objdump] Fix bad merge of docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364056
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George Rimar [Fri, 21 Jun 2019 14:15:15 +0000 (14:15 +0000)]
[llvm-objcopy] - Get rid of dynrel.elf precompiled binary from inputs.
We do not have to spread using the precompiled binaries in the tests,
when we can use YAML. This patch removes the dynrel.elf binary and adds
a few comments to the test cases.
Differential revision: https://reviews.llvm.org/D63641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364052
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Jay Foad [Fri, 21 Jun 2019 14:10:18 +0000 (14:10 +0000)]
[Scalarizer] Propagate IR flags
Summary:
The motivation for this was to propagate fast-math flags like nnan and
ninf on vector floating point operations to the corresponding scalar
operations to take advantage of follow-on optimizations. But I think
the same argument applies to all of our IR flags: if they apply to the
vector operation then they also apply to all the individual scalar
operations, and they might enable follow-on optimizations.
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364051
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George Rimar [Fri, 21 Jun 2019 14:07:35 +0000 (14:07 +0000)]
[llvm-readobj] - Inline a few yaml inputs into test cases.
There are some test that are splitted into main part + input yaml for no visible reason.
This patch inines the yaml part for the 3 test cases I found.
Differential revision: https://reviews.llvm.org/D63644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364049
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Andrea Di Biagio [Fri, 21 Jun 2019 14:05:58 +0000 (14:05 +0000)]
Set an explicit x86 triple for test bottleneck-analysis.s added by my r364045. NFC
This should unbreak the ppc64 buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364048
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Sam Elliott [Fri, 21 Jun 2019 13:36:09 +0000 (13:36 +0000)]
[RISCV] Add RISCV-specific TargetTransformInfo
Summary:
LLVM Allows Targets to provide information that guides optimisations
made to LLVM IR. This is done with callbacks on a TargetTransformInfo object.
This patch adds a TargetTransformInfo class for RISC-V. This will allow us to
implement RISC-V specific callbacks as they become necessary.
This commit also adds the getIntImmCost callbacks, and tests them with a simple
constant hoisting test. Our immediate costs are on the conservative side, for
the moment, but we prevent hoisting in most circumstances anyway.
Previous review was on D63007
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: ributzka, MaskRay, llvm-commits, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya, mgorny
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364046
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Andrea Di Biagio [Fri, 21 Jun 2019 13:32:54 +0000 (13:32 +0000)]
[MCA][Bottleneck Analysis] Teach how to compute a critical sequence of instructions based on the simulation.
This patch teaches the bottleneck analysis how to identify and print the most
expensive sequence of instructions according to the simulation. Fixes PR37494.
The goal is to help users identify the sequence of instruction which is most
critical for performance.
A dependency graph is internally used by the bottleneck analysis to describe
data dependencies and processor resource interferences between instructions.
There is one node in the graph for every instruction in the input assembly
sequence. The number of nodes in the graph is independent from the number of
iterations simulated by the tool. It means that a single node of the graph
represents all the possible instances of a same instruction contributed by the
simulated iterations.
Edges are dynamically "discovered" by the bottleneck analysis by observing
instruction state transitions and "backend pressure increase" events generated
by the Execute stage. Information from the events is used to identify critical
dependencies, and materialize edges in the graph. A dependency edge is uniquely
identified by a pair of node identifiers plus an instance of struct
DependencyEdge::Dependency (which provides more details about the actual
dependency kind).
The bottleneck analysis internally ranks dependency edges based on their impact
on the runtime (see field DependencyEdge::Dependency::Cost). To this end, each
edge of the graph has an associated cost. By default, the cost of an edge is a
function of its latency (in cycles). In practice, the cost of an edge is also a
function of the number of cycles where the dependency has been seen as
'contributing to backend pressure increases'. The idea is that the higher the
cost of an edge, the higher is the impact of the dependency on performance. To
put it in another way, the cost of an edge is a measure of criticality for
performance.
Note how a same edge may be found in multiple iteration of the simulated loop.
The logic that adds new edges to the graph checks if an equivalent dependency
already exists (duplicate edges are not allowed). If an equivalent dependency
edge is found, field DependencyEdge::Frequency of that edge is incremented by
one, and the new cost is cumulatively added to the existing edge cost.
At the end of simulation, costs are propagated to nodes through the edges of the
graph. The goal is to identify a critical sequence from a node of the root-set
(composed by node of the graph with no predecessors) to a 'sink node' with no
successors. Note that the graph is intentionally kept acyclic to minimize the
complexity of the critical sequence computation algorithm (complexity is
currently linear in the number of nodes in the graph).
The critical path is finally computed as a sequence of dependency edges. For
edges describing processor resource interferences, the view also prints a
so-called "interference probability" value (by dividing field
DependencyEdge::Frequency by the total number of iterations).
Examples of critical sequence computations can be found in tests added/modified
by this patch.
On output streams that support colored output, instructions from the critical
sequence are rendered with a different color.
Strictly speaking the analysis conducted by the bottleneck analysis view is not
a critical path analysis. The cost of an edge doesn't only depend on the
dependency latency. More importantly, the cost of a same edge may be computed
differently by different iterations.
The number of dependencies is discovered dynamically based on the events
generated by the simulator. However, their number is not fixed. This is
especially true for edges that model processor resource interferences; an
interference may not occur in every iteration. For that reason, it makes sense
to also print out a "probability of interference".
By construction, the accuracy of this analysis (as always) is strongly dependent
on the simulation (and therefore the quality of the information available in the
scheduling model).
That being said, the critical sequence effectively identifies a performance
criticality. Instructions from that sequence are expected to have a very big
impact on performance. So, users can take advantage of this information to focus
their attention on specific interactions between instructions.
In my experience, it works quite well in practice, and produces useful
output (in a reasonable amount time).
Differential Revision: https://reviews.llvm.org/D63543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364045
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Simon Tatham [Fri, 21 Jun 2019 13:17:23 +0000 (13:17 +0000)]
[ARM] Add MVE 64-bit GPR <-> vector move instructions.
These instructions let you load half a vector register at once from
two general-purpose registers, or vice versa.
The assembly syntax for these instructions mentions the vector
register name twice. For the move _into_ a vector register, the MC
operand list also has to mention the register name twice (once as the
output, and once as an input to represent where the unchanged half of
the output register comes from). So we can conveniently assign one of
the two asm operands to be the output $Qd, and the other $QdSrc, which
avoids confusing the auto-generated AsmMatcher too much. For the move
_from_ a vector register, there's no way to get round the fact that
both instances of that register name have to be inputs, so we need a
custom AsmMatchConverter to avoid generating two separate output MC
operands. (And even that wouldn't have worked if it hadn't been for
D60695.)
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62679
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364041
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Simon Tatham [Fri, 21 Jun 2019 13:17:08 +0000 (13:17 +0000)]
[ARM] Add MVE vector instructions that take a scalar input.
This adds the `MVE_qDest_rSrc` superclass and all its instances, plus
a few other instructions that also take a scalar input register or two.
I've also belatedly added custom diagnostic messages to the operand
classes for odd- and even-numbered GPRs, which required matching
changes in two of the existing MVE assembly test files.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364040
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Paul Robinson [Fri, 21 Jun 2019 13:10:19 +0000 (13:10 +0000)]
Fix a crash with assembler source and -g.
llvm-mc or clang with -g normally produces debug info describing the
assembler source itself; however, if that source already contains some
.file/.loc directives, we should instead emit the debug info described
by those directives. For certain assembler sources seen in the wild
(particularly in the Chrome build) this was causing a crash due to
incorrect assumptions about legal sequences of assembler source text.
Fixes PR38994.
Differential Revision: https://reviews.llvm.org/D63573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364039
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Simon Pilgrim [Fri, 21 Jun 2019 12:42:39 +0000 (12:42 +0000)]
[X86] X86ISD::ANDNP is a (non-commutative) binop
The sat add/sub tests still have unnecessary extract_subvector((vandnps ymm, ymm), 0) uses that should be split to (vandnps (extract_subvector(ymm, 0), extract_subvector(ymm, 0)), but its getting better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364038
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Simon Tatham [Fri, 21 Jun 2019 12:13:59 +0000 (12:13 +0000)]
[ARM] Add a batch of similarly encoded MVE instructions.
Summary:
This adds the `MVE_qDest_qSrc` superclass and all instructions that
inherit from it. It's not the complete class of _everything_ with a
q-register as both destination and source; it's a subset of them that
all have similar encodings (but it would have been hopelessly unwieldy
to call it anything like MVE_111x11100).
This category includes add/sub with carry; long multiplies; halving
multiplies; multiply and accumulate, and some more complex
instructions.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364037
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James Henderson [Fri, 21 Jun 2019 11:49:20 +0000 (11:49 +0000)]
[binutils] Add response file option to help and docs
Many LLVM-based tools already support response files (i.e. files
containing a list of options, specified with '@'). This change simply
updates the documentation and help text for some of these tools to
include it. I haven't attempted to fix all tools, just a selection that
I am interested in.
I've taken the opportunity to add some tests for --help behaviour, where
they were missing. We could expand these tests, but I don't think that's
within scope of this patch.
This fixes https://bugs.llvm.org/show_bug.cgi?id=42233 and
https://bugs.llvm.org/show_bug.cgi?id=42236.
Reviewed by: grimar, MaskRay, jkorous
Differential Revision: https://reviews.llvm.org/D63597
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364036
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Simon Pilgrim [Fri, 21 Jun 2019 11:25:06 +0000 (11:25 +0000)]
[X86] createMMXBuildVector - call with BuildVectorSDNode directly. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364030
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James Henderson [Fri, 21 Jun 2019 11:22:20 +0000 (11:22 +0000)]
[llvm-dwarfdump] Remove unnecessary explicit -h behaviour
--help and -h are automatically supported by the command-line parser,
unless overridden by the tool. The behaviour of the PrintHelpMessage
being used for -h prior to this patch is subtly different to that
provided by --help automatically (it omits certain elements of help text
and options, such as --help-list), so overriding the default is not
desirable, without good reason. This patch removes the explicit
specification of -h and its behaviour, so that the default behaviour is
used.
Reviewed by: hintonda
Differential Revision: https://reviews.llvm.org/D63565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364029
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Fangrui Song [Fri, 21 Jun 2019 11:19:11 +0000 (11:19 +0000)]
[ARM] Fix -Wimplicit-fallthrough after D62675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364028
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Simon Tatham [Fri, 21 Jun 2019 11:14:51 +0000 (11:14 +0000)]
[ARM] Add MVE vector compare instructions.
Summary:
These take a pair of vector register to compare, and a comparison type
(written in the form of an Arm condition suffix); they output a vector
of booleans in the VPR register, where predication can conveniently
use them.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364027
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Simon Pilgrim [Fri, 21 Jun 2019 11:13:15 +0000 (11:13 +0000)]
[X86] combineAndnp - use isNOT instead of manually checking for (XOR x, -1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364026
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Fangrui Song [Fri, 21 Jun 2019 11:05:26 +0000 (11:05 +0000)]
[Symbolize] Avoid lifetime extension and simplify std::map find/insert. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364025
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Simon Pilgrim [Fri, 21 Jun 2019 10:54:30 +0000 (10:54 +0000)]
[X86] foldVectorXorShiftIntoCmp - use isConstOrConstSplat. NFCI.
Use the isConstOrConstSplat helper instead of inspecting the build vector manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364024
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Simon Pilgrim [Fri, 21 Jun 2019 10:44:15 +0000 (10:44 +0000)]
[X86][AVX] isNOT - handle concat_vectors(xor X, -1, xor Y, -1) pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364022
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James Henderson [Fri, 21 Jun 2019 10:12:53 +0000 (10:12 +0000)]
[docs][llvm-objdump] Improve llvm-objdump documentation
The llvm-objdump document was missing many options, and there were also
some style issues with it. This patches fixes all but the first issue
listed in https://bugs.llvm.org/show_bug.cgi?id=42249 by:
1. Adding missing options and commands.
2. Standardising on double dashes for long-options throughout.
3. Moving Mach-O specific options to a separate section.
4. Removing options that don't exist or aren't relevant to
llvm-objdump.
Reviewed by: MaskRay, mtrent, alexshap
Differential Revision: https://reviews.llvm.org/D63606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364019
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Vitaly Buka [Fri, 21 Jun 2019 09:54:32 +0000 (09:54 +0000)]
[GN] Fix check-clang by disabling plugins
We can't link Analysis/plugins without -fPIC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364016
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Vitaly Buka [Fri, 21 Jun 2019 09:54:31 +0000 (09:54 +0000)]
[GN] Put libcxx include into the same place as cmake to fix Driver/print-file-name.c test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364015
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Simon Tatham [Fri, 21 Jun 2019 09:35:07 +0000 (09:35 +0000)]
[ARM] Add a batch of MVE floating-point instructions.
Summary:
This includes floating-point basic arithmetic (add/sub/multiply),
complex add/multiply, unary negation and absolute value, rounding to
integer value, and conversion to/from integer formats.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364013
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Mehdi Amini [Fri, 21 Jun 2019 05:43:08 +0000 (05:43 +0000)]
Use std::iterator_traits to infer result type of llvm::enumerate iterator wrapper
Update the llvm::enumerate helper class result_pair<R> to use the 'iterator_traits<R>::reference'
type as the result of 'value()' instead 'ValueOfRange<R> &'. This enables support for iterators
that return value types, i.e. non reference. This is a common pattern for some classes of
iterators, e.g. mapped_iterator.
Patch by: River Riddle <riverriddle@google.com>
Differential Revision: https://reviews.llvm.org/D63632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364007
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Fangrui Song [Fri, 21 Jun 2019 05:40:31 +0000 (05:40 +0000)]
Simplify std::lower_bound with llvm::{bsearch,lower_bound}. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364006
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Yevgeny Rouban [Fri, 21 Jun 2019 04:49:40 +0000 (04:49 +0000)]
[LICM & MSSA] Fixed test to run only with assertions enabled as it uses -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364005
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Vitaly Buka [Fri, 21 Jun 2019 02:15:07 +0000 (02:15 +0000)]
[GN] Fix build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364004
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Fangrui Song [Fri, 21 Jun 2019 01:51:50 +0000 (01:51 +0000)]
[MIPS GlobalISel] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D63541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364003
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Amara Emerson [Fri, 21 Jun 2019 00:36:19 +0000 (00:36 +0000)]
[GlobalISel][Localizer] Allow localization of G_INTTOPTR and chains of instructions.
G_INTTOPTR can prevent the localizer from moving G_CONSTANTs, but since it's
essentially a side effect free cast instruction we can remat both instructions.
This patch changes the localizer to enable localization of the chains by
iterating over the entry block instructions in reverse order. That way, uses will
localized first, and then the defs are free to be localized as well.
This also changes the previous SmallPtrSet of localized instructions to use a
SetVector instead. We're dealing with pointers and need deterministic iteration
order.
Overall, this change improves ARM64 -O0 CTMark code size by around 0.7% geomean.
Differential Revision: https://reviews.llvm.org/D63630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364001
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Seiya Nuta [Fri, 21 Jun 2019 00:21:50 +0000 (00:21 +0000)]
[llvm-objcopy][MachO] Rebuild the symbol/string table in the writer
Summary: Build the string table using StringTableBuilder, reassign symbol indices, and update symbol indices in relocations to allow adding/modifying/removing symbols from the object.
Reviewers: alexshap, rupprecht, jhenderson
Reviewed By: alexshap
Subscribers: mgorny, jakehehrlich, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364000
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Cameron McInally [Thu, 20 Jun 2019 23:03:55 +0000 (23:03 +0000)]
[Reassociate] Remove bogus assert reported in PR42349.
Also, add a FIXME for the unsafe transform on a unary FNeg. A unary FNeg can only be transformed to a FMul by -1.0 when the nnan flag is present. The unary FNeg project is a WIP, so the unsafe transformation is acceptable until that work is complete.
The bogus assert with introduced in D63445.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363998
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Sanjay Patel [Thu, 20 Jun 2019 22:55:28 +0000 (22:55 +0000)]
[InstSimplify] simplify power-of-2 (single bit set) sequences
As discussed in PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
Improving the canonicalization for these patterns:
rL363956
...means we should adjust/enhance the related simplification.
https://rise4fun.com/Alive/w1cp
Name: isPow2 or zero
%x = and i32 %xx, 2048
%a = add i32 %x, -1
%r = and i32 %a, %x
=>
%r = i32 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363997
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Evandro Menezes [Thu, 20 Jun 2019 22:03:54 +0000 (22:03 +0000)]
[CodeGen] Refactor check of suitability for a jump table (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363992
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Eli Friedman [Thu, 20 Jun 2019 22:00:07 +0000 (22:00 +0000)]
[ARM GlobalISel] Tests for s64 G_ADD and G_SUB.
Forgot to commit these in r363989 (https://reviews.llvm.org/D63585)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363991
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