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Simon Pilgrim [Thu, 15 Mar 2018 15:12:12 +0000 (15:12 +0000)]
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes
Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327632
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Sanjay Patel [Thu, 15 Mar 2018 14:48:39 +0000 (14:48 +0000)]
[InstSimplify] add tests with NaN operand for fp binops; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327631
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Simon Pilgrim [Thu, 15 Mar 2018 14:45:30 +0000 (14:45 +0000)]
[X86][SSE] Introduce Float/Vector WriteMove, WriteLoad and Writetore scheduler classes
As discussed on D44428 and PR36726, this patch splits off WriteFMove/WriteVecMove, WriteFLoad/WriteVecLoad and WriteFStore/WriteVecStore scheduler classes to permit vectors to be handled separately from gpr/scalar types.
I've minimised the diff here by only moving various basic SSE/AVX vector instructions across - we can fix the rest when called for. This does fix the MOVDQA vs MOVAPS/MOVAPD discrepancies mentioned on D44428.
Differential Revision: https://reviews.llvm.org/D44471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327630
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Simon Pilgrim [Thu, 15 Mar 2018 14:30:59 +0000 (14:30 +0000)]
[X86] Regenerate schedule tests with zero latency comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327628
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Sanjay Patel [Thu, 15 Mar 2018 14:29:27 +0000 (14:29 +0000)]
[PatternMatch, InstSimplify] allow undef elements when matching any vector FP zero
This matcher implementation appears to be slightly more efficient than
the generic constant check that it is replacing because every use was
for matching FP patterns, but the previous code would check int and
pointer type nulls too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327627
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Sanjay Patel [Thu, 15 Mar 2018 14:04:31 +0000 (14:04 +0000)]
[InstSimplify] remove 'nsz' requirement for frem 0, X
From the LangRef definition for frem:
"The value produced is the floating-point remainder of the two operands.
This is the same output as a libm ‘fmod‘ function, but without any
possibility of setting errno. The remainder has the same sign as the
dividend. This instruction is assumed to execute in the default
floating-point environment."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327626
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Sjoerd Meijer [Thu, 15 Mar 2018 13:42:28 +0000 (13:42 +0000)]
[AArch64] Codegen tests for the Armv8.2-A FP16 intrinsics
This is a follow up of the AArch64 FP16 intrinsics work;
the codegen tests had not been added yet.
Differential Revision: https://reviews.llvm.org/D44510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327624
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Ulrich Weigand [Thu, 15 Mar 2018 12:28:48 +0000 (12:28 +0000)]
[Debug] Retain both copies of debug intrinsics in HoistThenElseCodeToIf
When hoisting common code from the "then" and "else" branches of a condition
to before the "if", the HoistThenElseCodeToIf routine will attempt to merge
the debug location associated with the two original copies of the hoisted
instruction.
This is a problem in the special case where the hoisted instruction is a
debug info intrinsic, since for those the debug location is considered
part of the intrinsic and attempting to modify it may resut in invalid
IR. This is the underlying cause of PR36410.
This patch fixes the problem by handling debug info intrinsics specially:
instead of hoisting one copy and merging the two locations, the code now
simply hoists both copies, each with its original location intact. Note
that this is still only done in the case where both original copies are
otherwise (i.e. apart from location metadata) identical.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D44312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327622
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Brock Wyma [Thu, 15 Mar 2018 11:52:17 +0000 (11:52 +0000)]
[CodeView] Initial support for emitting S_BLOCK32 symbols for lexical scopes
This patch sorts local variables by lexical scope and emits them inside
an appropriate S_BLOCK32 CodeView symbol.
Differential Revision: https://reviews.llvm.org/D42926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327620
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Fedor Sergeev [Thu, 15 Mar 2018 11:01:19 +0000 (11:01 +0000)]
[New PM][IRCE] port of Inductive Range Check Elimination pass to the new pass manager
There are two nontrivial details here:
* Loop structure update interface is quite different with new pass manager,
so the code to add new loops was factored out
* BranchProbabilityInfo is not a loop analysis, so it can not be just getResult'ed from
within the loop pass. It cant even be queried through getCachedResult as LoopCanonicalization
sequence (e.g. LoopSimplify) might invalidate BPI results.
Complete solution for BPI will likely take some time to discuss and figure out,
so for now this was partially solved by making BPI optional in IRCE
(skipping a couple of profitability checks if it is absent).
Most of the IRCE tests got their corresponding new-pass-manager variant enabled.
Only two of them depend on BPI, both marked with TODO, to be turned on when BPI
starts being available for loop passes.
Reviewers: chandlerc, mkazantsev, sanjoy, asbirlea
Reviewed By: mkazantsev
Differential Revision: https://reviews.llvm.org/D43795
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327619
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Andrei Elovikov [Thu, 15 Mar 2018 09:59:15 +0000 (09:59 +0000)]
[LoopUnroll] Ignore ephemeral values when checking full unroll profitability.
Summary:
Before this patch call graph is like this in the LoopUnrollPass:
tryToUnrollLoop
ApproximateLoopSize
collectEphemeralValues
/* Use collected ephemeral values */
computeUnrollCount
analyzeLoopUnrollCost
/* Bail out from the analysis if loop contains CallInst */
This patch moves collection of the ephemeral values to the tryToUnrollLoop
function and passes the collected values into both ApproximateLoopsize (as
before) and additionally starts using them in analyzeLoopUnrollCost:
tryToUnrollLoop
collectEphemeralValues
ApproximateLoopSize(EphValues)
/* Use EphValues */
computeUnrollCount(EphValues)
analyzeLoopUnrollCost(EphValues)
/* Ignore ephemeral values - they don't contribute to the final cost */
/* Bail out from the analysis if loop contains CallInst */
Reviewers: mzolotukhin, evstupac, sanjoy
Reviewed By: evstupac
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327617
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Max Kazantsev [Thu, 15 Mar 2018 09:38:00 +0000 (09:38 +0000)]
[SCEV][NFC] Remove TBB, FBB parameters from exit limit computations
Methods `computeExitLimitFromCondCached` and `computeExitLimitFromCondImpl` take
true and false branches as parameters and only use them for asserts and for identifying
whether true/false branch belongs to the loop (which can be done once earlier). This fact
complicates generalization of exit limit computation logic on guards because the guards
don't have blocks to which they go in case of failure explicitly.
The motivation of this patch is that currently this part of SCEV knows nothing about guards
and only works with explicit branches. As result, it fails to prove that a loop
for (i = 0; i < 100; i++)
guard(i < 10);
exits after 10th iteration, while in the equivalent example
for (i = 0; i < 100; i++)
if (i >= 10) break;
SCEV easily proves this fact. We are going to change it in near future, and this is why
we need to make these methods operate on more abstract level.
This patch refactors this code to get rid of these parameters as meaningless and prepare
ground for teaching these methods to work with guards as well as they work with explicit
branching instructions.
Differential Revision: https://reviews.llvm.org/D44419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327615
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Craig Topper [Thu, 15 Mar 2018 06:49:01 +0000 (06:49 +0000)]
[X86] Add test cases for 512-bit addsub from build_vector.
There is no 512 bit addsub instruction, but we partially match it handle fmaddsub matching. We explicitly bail out for 512 bit vectors after failing the fmaddsub match, but we had no test coverage for that bail out.
We might want to consider splitting and using 256 bit instructions instead of the long sequence seen here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327605
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Craig Topper [Thu, 15 Mar 2018 06:14:55 +0000 (06:14 +0000)]
[X86] Add support for matching FMSUBADD from build_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327604
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Craig Topper [Thu, 15 Mar 2018 06:14:53 +0000 (06:14 +0000)]
[X86] Remove old TODO. We have coverage for this now.
Coverage was added in r320950.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327603
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Craig Topper [Thu, 15 Mar 2018 06:14:51 +0000 (06:14 +0000)]
[X86] Use MVT in a couple places where we know the type is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327602
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Aaron Smith [Thu, 15 Mar 2018 06:04:51 +0000 (06:04 +0000)]
[DebugInfo] Add a new method IPDBSession::findLineNumbersBySectOffset
Summary:
Some PDB symbols do not have a valid VA or RVA but have Addr by Section and Offset. For example, a variable in thread-local storage has the following properties:
get_addressOffset: 0
get_addressSection: 5
get_lexicalParentId: 2
get_name: g_tls
get_symIndexId: 12
get_typeId: 4
get_dataKind: 6
get_symTag: 7
get_locationType: 2
This change provides a new method to locate line numbers by Section and Offset from those symbols.
Reviewers: zturner, rnk, llvm-commits
Subscribers: asmith, JDevlieghere
Differential Revision: https://reviews.llvm.org/D44407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327601
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Lei Huang [Thu, 15 Mar 2018 03:06:44 +0000 (03:06 +0000)]
[PowerPC][NFC] formatting-only fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327599
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George Burgess IV [Thu, 15 Mar 2018 02:58:36 +0000 (02:58 +0000)]
Remove unused variable; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327597
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Lang Hames [Thu, 15 Mar 2018 00:30:14 +0000 (00:30 +0000)]
[ORC] Re-apply r327566 with a fix for test-global-ctors.ll.
Also clang-formats the patch, which I should have done the first time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327594
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Matt Davis [Wed, 14 Mar 2018 23:30:31 +0000 (23:30 +0000)]
[CleanUp] Remove NumInstructions field from LoopVectorizer's RegisterUsage struct.
Summary:
This variable is largely going unused; aside from reporting number of instructions for in DEBUG builds.
The only use of NumInstructions is in debug output to represent the LoopSize. That value can be can be misleading as it also includes metadata instructions (e.g., DBG_VALUE) which have no real impact. If we do choose to keep this around, we probably should guard it by a DEBUG macro, as it's not used in production builds.
Reviewers: majnemer, congh, rengolin
Reviewed By: rengolin
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D44495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327589
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Simon Pilgrim [Wed, 14 Mar 2018 23:12:09 +0000 (23:12 +0000)]
[X86][Btver2] Add support for multiple pipelines stages for fpu schedules. NFCI.
This allows us to use JWriteResFpuPair for complex schedule classes as well as single pipe instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327588
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Sanjay Patel [Wed, 14 Mar 2018 22:45:58 +0000 (22:45 +0000)]
[InstSimplify] add tests for frem and vectors with undef; NFC
These should all be folded. The vector tests need to have
m_AnyZero updated to ignore undef elements, but we need to
be careful not to return the existing value in that case
and unintentionally propagate undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327585
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Mark Searles [Wed, 14 Mar 2018 22:04:32 +0000 (22:04 +0000)]
[AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed.
Differential Revision: https://reviews.llvm.org/D44434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327583
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Simon Pilgrim [Wed, 14 Mar 2018 21:55:54 +0000 (21:55 +0000)]
[X86][Btver2] Add ResourceCycles and NumMicroOps overrides to scalar instructions. NFCI.
Currently still use default values - this is setup for a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327582
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Reid Kleckner [Wed, 14 Mar 2018 21:54:21 +0000 (21:54 +0000)]
[FastISel] Sink local value materializations to first use
Summary:
Local values are constants, global addresses, and stack addresses that
can't be folded into the instruction that uses them. For example, when
storing the address of a global variable into memory, we need to
materialize that address into a register.
FastISel doesn't want to materialize any given local value more than
once, so it generates all local value materialization code at
EmitStartPt, which always dominates the current insertion point. This
allows it to maintain a map of local value registers, and it knows that
the local value area will always dominate the current insertion point.
The downside is that local value instructions are always emitted without
a source location. This is done to prevent jumpy line tables, but it
means that the local value area will be considered part of the previous
statement. Consider this C code:
call1(); // line 1
++global; // line 2
++global; // line 3
call2(&global, &local); // line 4
Today we end up with assembly and line tables like this:
.loc 1 1
callq call1
leaq global(%rip), %rdi
leaq local(%rsp), %rsi
.loc 1 2
addq $1, global(%rip)
.loc 1 3
addq $1, global(%rip)
.loc 1 4
callq call2
The LEA instructions in the local value area have no source location and
are treated as being on line 1. Stepping through the code in a debugger
and correlating it with the assembly won't make much sense, because
these materializations are only required for line 4.
This is actually problematic for the VS debugger "set next statement"
feature, which effectively assumes that there are no registers live
across statement boundaries. By sinking the local value code into the
statement and fixing up the source location, we can make that feature
work. This was filed as https://bugs.llvm.org/show_bug.cgi?id=35975 and
https://crbug.com/793819.
This change is obviously not enough to make this feature work reliably
in all cases, but I felt that it was worth doing anyway because it
usually generates smaller, more comprehensible -O0 code. I measured a
0.12% regression in code generation time with LLC on the sqlite3
amalgamation, so I think this is worth doing.
There are some special cases worth calling out in the commit message:
1. local values materialized for phis
2. local values used by no-op casts
3. dead local value code
Local values can be materialized for phis, and this does not show up as
a vreg use in MachineRegisterInfo. In this case, if there are no other
uses, this patch sinks the value to the first terminator, EH label, or
the end of the BB if nothing else exists.
Local values may also be used by no-op casts, which adds the register to
the RegFixups table. Without reversing the RegFixups map direction, we
don't have enough information to sink these instructions.
Lastly, if the local value register has no other uses, we can delete it.
This comes up when fastisel tries two instruction selection approaches
and the first materializes the value but fails and the second succeeds
without using the local value.
Reviewers: aprantl, dblaikie, qcolombet, MatzeB, vsk, echristo
Subscribers: dotdash, chandlerc, hans, sdardis, amccarth, javed.absar, zturner, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D43093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327581
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Francis Visoiu Mistrih [Wed, 14 Mar 2018 21:52:13 +0000 (21:52 +0000)]
[CodeGen] Use MIR syntax for MachineMemOperand printing
Get rid of the "; mem:" suffix and use the one we use in MIR: ":: (load 2)".
rdar://
38163529
Differential Revision: https://reviews.llvm.org/D42377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327580
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Philip Reames [Wed, 14 Mar 2018 21:35:06 +0000 (21:35 +0000)]
[EarlyCSE] Exploit open ended invariant.start scopes
If we have an invariant.start with no corresponding invariant.end, then the memory location becomes invariant indefinitely after the invariant.start. As a result, anything dominated by the start is guaranteed to see the value the memory location had when the invariant.start executed.
This patch adds an AvailableInvariants table which tracks the generation a particular memory location became invariant and then uses that information to allow value forwarding that would otherwise be disallowed by potentially aliasing stores. (Reminder: In EarlyCSE everything clobbers everything by default.)
This should be compatible with the MemorySSA variant, but design is generational. We can and should add first class support for invariant.start within MemorySSA at a later time. I took a quick look at doing so, but probably need some input from a MemorySSA expert.
Differential Revision: https://reviews.llvm.org/D43716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327577
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Reid Kleckner [Wed, 14 Mar 2018 21:32:34 +0000 (21:32 +0000)]
Revert "[ORC] Switch from shared_ptr to unique_ptr for addModule methods."
This reverts commit r327566, it breaks
test/ExecutionEngine/OrcMCJIT/test-global-ctors.ll.
The test doesn't crash with a stack trace, unfortunately. It merely
returns 1 as the exit code.
ASan didn't produce a report, and I reproduced this on my Linux machine
and Windows box.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327576
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Sanjay Patel [Wed, 14 Mar 2018 21:23:27 +0000 (21:23 +0000)]
[InstSimplify] fix folds for (0.0 - X) + X --> 0 (PR27151)
As shown in:
https://bugs.llvm.org/show_bug.cgi?id=27151
...the existing fold could miscompile when X is NaN.
The fold was also dependent on 'ninf' but that's not necessary.
From IEEE-754 (with default rounding which we can assume for these opcodes):
"When the sum of two operands with opposite signs (or the difference of two
operands with like signs) is exactly zero, the sign of that sum (or difference)
shall be +0...However, x + x = x − (−x) retains the same sign as x even when
x is zero."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327575
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Simon Pilgrim [Wed, 14 Mar 2018 21:03:09 +0000 (21:03 +0000)]
[X86] Add haswell testing for PR35635 as well.
To improve complete model testing for schedulers for instructions with multiple results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327572
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Francis Visoiu Mistrih [Wed, 14 Mar 2018 20:34:03 +0000 (20:34 +0000)]
[AArch64] Emit CSR loads in the same order as stores
Optionally allow the order of restoring the callee-saved registers in the
epilogue to be reversed.
The flag -reverse-csr-restore-seq generates the following code:
```
stp x26, x25, [sp, #-64]!
stp x24, x23, [sp, #16]
stp x22, x21, [sp, #32]
stp x20, x19, [sp, #48]
; [..]
ldp x24, x23, [sp, #16]
ldp x22, x21, [sp, #32]
ldp x20, x19, [sp, #48]
ldp x26, x25, [sp], #64
ret
```
Note how the CSRs are restored in the same order as they are saved.
One exception to this rule is the last `ldp`, which allows us to merge
the stack adjustment and the ldp into a post-index ldp. This is done by
first generating:
ldp x26, x27, [sp]
add sp, sp, #64
which gets merged by the arm64 load store optimizer into
ldp x26, x25, [sp], #64
The flag is disabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327569
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Lang Hames [Wed, 14 Mar 2018 20:29:45 +0000 (20:29 +0000)]
[ORC] Switch from shared_ptr to unique_ptr for addModule methods.
Layer implementations typically mutate module state, and this is better
reflected by having layers own the Module they are operating on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327566
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Alexander Richardson [Wed, 14 Mar 2018 20:28:53 +0000 (20:28 +0000)]
[UpdateTestChecks] Handle IR variables with a '-' in the name
Summary:
I noticed that clang will emit variables such as %indirect-arg-temp when
running update_cc1_test_checks.py and therefore update_cc1_test_checks.py
wasn't adding FileCheck captures for those variables.
Reviewers: MaskRay
Reviewed By: MaskRay
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327564
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Reid Kleckner [Wed, 14 Mar 2018 19:24:32 +0000 (19:24 +0000)]
[MC] Always emit relocations for same-section function references
Summary:
We already emit relocations in this case when the "incremental linker
compatible" flag is set, but it turns out these relocations are also
required for /guard:cf. Now that we have two use cases for this
behavior, let's make it unconditional to try to keep things simple.
We never hit this problem in Clang because it always sets the
"incremental linker compatible" flag when targeting MSVC. However, LLD
LTO doesn't set this flag, so we'd get CFG failures at runtime when
using ThinLTO and /guard:cf. We probably don't want LLD LTO to set the
"incremental linker compatible" assembler flag, since this has nothing
to do with incremental linking, and we don't need to timestamp LTO
temporary objects.
Fixes PR36624.
Reviewers: inglorion, espindola, majnemer
Subscribers: mehdi_amini, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D44485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327557
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Sanjay Patel [Wed, 14 Mar 2018 18:52:40 +0000 (18:52 +0000)]
[InstSimplify] add tests to show missing/broken fadd folds (PR27151, PR26958); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327554
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Sanjay Patel [Wed, 14 Mar 2018 18:49:57 +0000 (18:49 +0000)]
[InstSimplify] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327553
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Reid Kleckner [Wed, 14 Mar 2018 18:33:53 +0000 (18:33 +0000)]
[LLVM-C] [bindings/go] Add C and Golang bindings for COMDAT
Patch by Ben Clayton
Differential Revision: https://reviews.llvm.org/D44086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327551
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Roman Lebedev [Wed, 14 Mar 2018 17:59:12 +0000 (17:59 +0000)]
[InstSimplify] [NFC] cast-unsigned-icmp-cmp-0.ll - don't run instcombine
As disscussed in post-commit review of D44421, there is simply
no reason to run instcombine on this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327541
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Craig Topper [Wed, 14 Mar 2018 17:57:19 +0000 (17:57 +0000)]
[X86] Add back fast-isel code for handling i8 shifts.
I removed this in r316797 because the coverage report showed no coverage and I thought it should have been handled by the auto generated table. I now see that there is code that bypasses the table if the shift amount is out of bounds.
This adds back the code. We'll codegen out of bounds i8 shifts to effectively (amount & 0x1f). The 0x1f is a strange quirk of x86 that shift amounts are always masked to 5-bits(except 64-bits). So if the masked value is still out bounds the result will be 0.
Fixes PR36731.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327540
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Fangrui Song [Wed, 14 Mar 2018 17:47:07 +0000 (17:47 +0000)]
Fix LLVM IR check lines in utils/update_cc_test_checks.py
Reviewers: arichardson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327538
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Roman Lebedev [Wed, 14 Mar 2018 17:31:08 +0000 (17:31 +0000)]
[InstSimplify] [NFC] Add tests for peeking through unsigned FP casts for sign compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
Looking at the IR pattern in question, as per [[ https://github.com/rutgers-apl/alive-nj | alive-nj ]], for all the type combinations i checked
(input: `i16`, `i32`, `i64`; intermediate: `half`/`i16`, `float`/`i32`, `double`/`i64`)
for the following `icmp` comparisons the `uitofp`+`bitcast`+`icmp` can be evaluated to a boolean:
* `slt 0`
* `sgt -1`
I did not check vectors, but i'm guessing it's the same there.
{
F5889242}
Thus all these cases are in the testcase (along with the vector variant with additional `undef` element in the middle).
There are no negative patterns here (unless alive-nj lied/is broken), all of these should be optimized.
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327535
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Roman Lebedev [Wed, 14 Mar 2018 17:31:03 +0000 (17:31 +0000)]
[InstCombine] [NFC] Add tests for peeking through unsigned FP casts for zero-equality compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
Looking at the IR pattern in question, as per [[ https://github.com/rutgers-apl/alive-nj | alive-nj ]], for all the type combinations i checked
(input: `i16`, `i32`, `i64`; intermediate: `half`/`i16`, `float`/`i32`, `double`/`i64`)
for the following `icmp` comparisons the `uitofp`+`bitcast` can be dropped:
* `eq 0`
* `ne 0`
I did not check vectors, but i'm guessing it's the same there.
{
F5889189}
Thus all these cases are in the testcase (along with the vector variant with additional `undef` element in the middle).
There are no negative patterns here (unless alive-nj lied/is broken), all of these should be optimized.
Generated with
{
F5889196}
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327534
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Francis Visoiu Mistrih [Wed, 14 Mar 2018 17:10:58 +0000 (17:10 +0000)]
[AArch64] Keep track of MIFlags in the LoadStoreOptimizer
Merging:
* $x26, $x25 = frame-setup LDPXi $sp, 0
* $sp = frame-destroy ADDXri $sp, 64, 0
into an LDPXpost should preserve the flags from both instructions as
following:
* frame-setup frame-destroy LDPXpost
Differential Revision: https://reviews.llvm.org/D44446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327533
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Craig Topper [Wed, 14 Mar 2018 16:55:15 +0000 (16:55 +0000)]
[X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demanded bits if it helps created an and mask that can be matched as a zero extend.
I had to modify the bswap recognition to allow unshrunk masks to make this work.
Fixes PR36689.
Differential Revision: https://reviews.llvm.org/D44442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327530
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Nicholas Wilson [Wed, 14 Mar 2018 15:58:03 +0000 (15:58 +0000)]
[WebAssembly] Add DenseMap traits and operator== for Wasm type structs
Differential Revision: https://reviews.llvm.org/D44303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327526
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Simon Pilgrim [Wed, 14 Mar 2018 15:47:08 +0000 (15:47 +0000)]
[X86][AVX] Use WriteFShuffleLd for broadcast reg-mem instructions
They shouldn't be treated as pure loads.
Found while investigating D44428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327524
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Nicholas Wilson [Wed, 14 Mar 2018 15:44:45 +0000 (15:44 +0000)]
[WebAssembly] Identify COMDATs by index rather than string. NFC
This will enable an optimisation in LLD.
Differential Revision: https://reviews.llvm.org/D44343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327522
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Arnold Schwaighofer [Wed, 14 Mar 2018 15:44:07 +0000 (15:44 +0000)]
SjLjEHPrepare: Don't reg-to-mem swifterror values
swifterror llvm values model the swifterror register as memory at the
LLVM IR level. ISel will perform adhoc mem-to-reg on them. swifterror
values are constraint in how they can be used. Spilling them to memory
is not allowed.
SjLjEHPrepare tried to lower swifterror values to memory which is
unecessary since the back-end will spill and reload the register as
neccessary (as long as clobbering calls are marked as such which is the
case here) and further leads to invalid IR because swifterror values
can't be stored to memory.
rdar://
38164004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327521
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Alexander Ivchenko [Wed, 14 Mar 2018 15:41:11 +0000 (15:41 +0000)]
[GlobalIsel][X86] Support for G_SDIV instruction
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327520
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Sanjay Patel [Wed, 14 Mar 2018 15:28:48 +0000 (15:28 +0000)]
[CodeGen] allow printing of zero latency in sched comments
I don't know how to expose this in a test. There are ARM / AArch64
sched classes that include zero latency instructions, but I'm not
seeing sched info printed for those targets. X86 will almost
certainly have these soon (see PR36671), but no model has
'let Latency = 0' currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327518
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Andrea Di Biagio [Wed, 14 Mar 2018 15:19:47 +0000 (15:19 +0000)]
[llvm-mca] Remove unused variable from InstrBuilder.cpp. NFC
This was causing a buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327517
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Andrea Di Biagio [Wed, 14 Mar 2018 14:57:23 +0000 (14:57 +0000)]
[llvm-mca] Move the logic that updates the register files from InstrBuilder to DispatchUnit. NFCI
Before this patch, the register file was always updated at instruction creation
time. That means, new read-after-write dependencies, and new temporary registers
were allocated at instruction creation time.
This patch refactors the code in InstrBuilder, and move all the logic that
updates the register file into the dispatch unit. We only want to update the
register file when instructions are effectively dispatched (not before).
This refactoring also helps removing a bad dependency between the InstrBuilder
and the DispatchUnit.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327514
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Petar Jovanovic [Wed, 14 Mar 2018 14:13:31 +0000 (14:13 +0000)]
[mips] Add support for CRC ASE
This includes
Instructions: crc32b, crc32h, crc32w, crc32d,
crc32cb, crc32ch, crc32cw, crc32cd
Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc
Attribute: crc
.MIPS.abiflags: CRC (0x8000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327511
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Simon Pilgrim [Wed, 14 Mar 2018 14:05:19 +0000 (14:05 +0000)]
[X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costs
Account for ymm double pumping and add proper pshufb/permutevar support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327510
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Teresa Johnson [Wed, 14 Mar 2018 14:00:57 +0000 (14:00 +0000)]
[LTO/gold] Fix workaround for old plugin-api.h in --wrap support
The workaround for older plugin-api.h in r327506 unfortunately
used another union member that is also fairly new and not available
in the plugin-api.h on some of the bots, leading to:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/9121/steps/build-stage2-LLVMgold.so/logs/stdio
Change to use a different member that we will definitely have (as it
is used elsewhere in gold-plugin.cpp already).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327509
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Teresa Johnson [Wed, 14 Mar 2018 13:26:18 +0000 (13:26 +0000)]
[LTO/gold] Support --wrap
Summary:
(Restores r327459 with handling for old plugin-api.h)
Utilize new gold plugin api interface for obtaining --wrap option
arguments, and LTO API handling (added for --wrap support in lld LTO),
to mark symbols so that LTO does not optimize them inappropriately.
Note the test cases will be in a new gold test subdirectory that
is dependent on the next release of gold which will contain the new
interfaces.
Reviewers: pcc, tmsriram
Subscribers: mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D44235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327506
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Simon Pilgrim [Wed, 14 Mar 2018 13:22:56 +0000 (13:22 +0000)]
[X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instructions
They shouldn't be treated as pure loads.
Found while investigating D44428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327505
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Martin Storsjo [Wed, 14 Mar 2018 13:09:10 +0000 (13:09 +0000)]
[AArch64] Don't produce R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
Support for this relocation is missing in both LLD and GNU binutils
at the moment.
This reverts the ELF parts of SVN r327316.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327503
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Simon Pilgrim [Wed, 14 Mar 2018 12:04:51 +0000 (12:04 +0000)]
Fix 'not all control paths return a value' MSVC warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327502
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Pavel Labath [Wed, 14 Mar 2018 11:31:17 +0000 (11:31 +0000)]
Fix msvc compiler error in r327498
msvc reports an "illegal indirection" error here. Attempt to appease it
with a different initialization syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327500
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Alexander Ivchenko [Wed, 14 Mar 2018 11:23:57 +0000 (11:23 +0000)]
[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327499
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Pavel Labath [Wed, 14 Mar 2018 11:14:43 +0000 (11:14 +0000)]
Explicitly initialize dwarf::FormParams in DIEInteger::SizeOf
This could end up inititialized if someone called the function with a
null AsmPrinter. Right now this only happens in DIEHash unit tests,
presumably because it was hard to create an AsmPrinter in the context of
unit tests. This only worked before r327486 because those tests did not
use any dwarf forms whose size actually depended on the dwarf version
(otherwise, they would have crashed due to null dereference).
I fix the uninitialized error, by explicitly initializing FormParams to
an invalid value, which will cause getFixedFormByteSize to return None
if called with a form with version-dependent size. A more principled
solution might be to fix the DIEHash tests to always pass in a valid
AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327498
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Nicolai Haehnle [Wed, 14 Mar 2018 11:01:01 +0000 (11:01 +0000)]
TableGen: Explicitly forbid some nestings of class, multiclass, and foreach
These previously all failed one way or another, but now we produce a more
helpful error message.
Change-Id: I8ffd2e87c8e35a5134c3be289e0a1fecaa2bb8ca
Differential revision: https://reviews.llvm.org/D44115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327497
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:57 +0000 (11:00 +0000)]
TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons
Change-Id: I8e2ece677268972d578a787467f7ef52a1f33a71
Differential revision: https://reviews.llvm.org/D44114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327496
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:48 +0000 (11:00 +0000)]
TableGen: Allow dag operators to be resolved late
Change-Id: I51bb80fd5c48c8ac441ab11e43d43c1b91b4b590
Differential revision: https://reviews.llvm.org/D44113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327495
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:43 +0000 (11:00 +0000)]
TableGen: Type-check BinOps
Additionally, allow more than two operands to !con, !add, !and, !or
in the same way as is already allowed for !listconcat and !strconcat.
Change-Id: I9659411f554201b90cd8ed7c7e004d381a66fa93
Differential revision: https://reviews.llvm.org/D44112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327494
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:33 +0000 (11:00 +0000)]
TableGen: Allow ? in lists
This makes using !dag more convenient in some cases.
Change-Id: I0a8c35e15ccd1ecec778fd1c8d64eee38d74517c
Differential revision: https://reviews.llvm.org/D44111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327493
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:26 +0000 (11:00 +0000)]
TableGen: Add !dag function for construction
This allows constructing DAG nodes with programmatically determined
names, and can simplify constructing DAG nodes in other cases as
well.
Also, add documentation and some very simple tests for the already
existing !con.
Change-Id: Ida61cd82e99752548d7109ce8da34d29da56a5f7
Differential revision: https://reviews.llvm.org/D44110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327492
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Alexander Timofeev [Wed, 14 Mar 2018 09:48:51 +0000 (09:48 +0000)]
[AMDGPU] Fix for DAGCombiner infinite loop in OCLtst
Differential revision: https://reviews.llvm.org/D44417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327488
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Pavel Labath [Wed, 14 Mar 2018 09:39:54 +0000 (09:39 +0000)]
DWARF: Unify form size handling code
Summary:
This patch replaces the two switches which are deducing the size of
various forms with a single implementation. I have put the new
implementation into BinaryFormat, to avoid introducing dependencies
between the two independent libraries (DebugInfo and CodeGen) that need
this functionality.
Reviewers: aprantl, JDevlieghere, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327486
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Jonas Devlieghere [Wed, 14 Mar 2018 09:34:54 +0000 (09:34 +0000)]
[dsymutil] Print architecture in warning
Make the architecture part of the warning in the DebugMapParser. This
makes things consistent with the Apple's internal version of dsymutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327485
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Pavel Labath [Wed, 14 Mar 2018 09:28:38 +0000 (09:28 +0000)]
Export LLVM_DYLIB_COMPONENTS in LLVMConfig.cmake
Summary:
This is needed so that external projects (e.g. a standalone build of
lldb) can link to the LLVM shared library via the USE_SHARED argument of
llvm_config. Without this, llvm_config would add LLVM to the link list,
but then also add the constituent static libraries, resulting in
multiply defined symbols.
Reviewers: beanz, mgorny
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327484
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Alexander Ivchenko [Wed, 14 Mar 2018 09:11:23 +0000 (09:11 +0000)]
[GlobalIsel][X86] Support for G_ZEXT instruction
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327482
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Robert Widmann [Wed, 14 Mar 2018 06:45:51 +0000 (06:45 +0000)]
[LLVM-C] Redo unnamed_address attribute bindings
Summary:
The old bindings should have used an enum instead of a boolean. This
deprecates LLVMHasUnnamedAddr and LLVMSetUnnamedAddr , replacing them
with LLVMGetUnnamedAddress and LLVMSetUnnamedAddress respectively that do.
Though it is unlikely LLVM will gain more supported global value linker
hints, the new API can scale to accommodate this.
Reviewers: deadalnix, whitequark
Reviewed By: whitequark
Subscribers: llvm-commits, harlanhaskins
Differential Revision: https://reviews.llvm.org/D43448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327479
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Lang Hames [Wed, 14 Mar 2018 06:39:49 +0000 (06:39 +0000)]
[RuntimeDyld] Silence a compiler error.
This should fix the error at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327478
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Lang Hames [Wed, 14 Mar 2018 06:25:08 +0000 (06:25 +0000)]
[ORC] Fix a data race in the lookup function.
The Error locals need to be protected by a mutex. (This could be fixed by
having the promises / futures contain Expected and Error values, but
MSVC's future implementation does not support this yet).
Hopefully this will fix some of the errors seen on the builders due to
r327474.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327477
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Lang Hames [Wed, 14 Mar 2018 06:25:07 +0000 (06:25 +0000)]
[ExecutionEngine] Add a getSymbolTable method to RuntimeDyld.
This can be used to extract the symbol table from a RuntimeDyld instance prior
to disposing of it.
This patch also updates RTDyldObjectLinkingLayer to use the new method, rather
than requesting symbols one at a time via getSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327476
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Lang Hames [Wed, 14 Mar 2018 05:23:56 +0000 (05:23 +0000)]
[ORC] Silence a compiler error.
This should fix the builder error at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327475
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Lang Hames [Wed, 14 Mar 2018 04:18:04 +0000 (04:18 +0000)]
[ORC] Add a 'lookup' convenience function for finding symbols in a list of VSOs.
The lookup function takes a list of VSOs, a set of symbol names (or just one
symbol name) and a materialization function object. It returns an
Expected<SymbolMap> (if given a set of names) or an Expected<JITEvaluatedSymbol>
(if given just one name). The lookup method constructs an
AsynchronousSymbolQuery for the given names, applies that query to each VSO in
the list in turn, and then blocks waiting for the query to complete. If
threading is enabled then the materialization function object can be used to
execute the materialization on different threads. If threading is disabled the
MaterializeOnCurrentThread utility must be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327474
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Eugene Zemtsov [Wed, 14 Mar 2018 02:10:07 +0000 (02:10 +0000)]
Disable test debuglineinfo-path on powerpc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327472
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Eugene Zemtsov [Wed, 14 Mar 2018 01:07:18 +0000 (01:07 +0000)]
grep for global functions only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327469
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Matt Arsenault [Wed, 14 Mar 2018 00:36:23 +0000 (00:36 +0000)]
TargetMachine: Add address space to getPointerSize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327467
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Eugene Zemtsov [Wed, 14 Mar 2018 00:15:16 +0000 (00:15 +0000)]
Add extra output/check to debug clang-ppc64be-linux test failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327466
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Teresa Johnson [Tue, 13 Mar 2018 23:55:34 +0000 (23:55 +0000)]
Revert "[LTO/gold] Support --wrap"
This reverts commit r327459. The new gold plugin interface is not
available with older gold installations, leading to compile failures:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/9109/steps/build-stage2-LLVMgold.so/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327465
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Craig Topper [Tue, 13 Mar 2018 23:31:48 +0000 (23:31 +0000)]
[X86] Re-generate test to get proper capitalization of its CHECK lines. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327462
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Aditya Nandakumar [Tue, 13 Mar 2018 23:21:13 +0000 (23:21 +0000)]
[GISel]: Fix incorrect type used in Pattern Match for ICst
getConstantVRegVal() returns int64_t but we use uint64_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327461
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Teresa Johnson [Tue, 13 Mar 2018 23:06:19 +0000 (23:06 +0000)]
[LTO/gold] Support --wrap
Summary:
Utilize new gold plugin api interface for obtaining --wrap option
arguments, and LTO API handling (added for --wrap support in lld LTO),
to mark symbols so that LTO does not optimize them inappropriately.
Note the test cases will be in a new gold test subdirectory that
is dependent on the next release of gold which will contain the new
interfaces.
Reviewers: pcc, tmsriram
Subscribers: mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D44235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327459
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Eugene Zemtsov [Tue, 13 Mar 2018 22:48:39 +0000 (22:48 +0000)]
Disable optimizations in debuglineinfo-path test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327458
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Craig Topper [Tue, 13 Mar 2018 22:36:07 +0000 (22:36 +0000)]
[X86] Simplify the LowerAVXCONCAT_VECTORS code a little by creating a single path for insert_subvector handling.
We now only create recursive concats if we have more than two non-zero values. This keeps our subvector broadcast DAG combine functioning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327457
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Craig Topper [Tue, 13 Mar 2018 22:05:25 +0000 (22:05 +0000)]
[X86] Rewrite LowerAVXCONCAT_VECTORS similar to how we handle vXi1 concats.
This better able to detect undef and zeros pieces in the concat. Or cases when only one subvector is non-zero. This allows us to avoid silly things like double inserts into progressively larger undefs.
This still builds 512 bit concats of 128 bits by building up through 256 bits first. But I don't know if that's best.
We probably want to merge this with the vXi1 concat code since they are very similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327454
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Zachary Turner [Tue, 13 Mar 2018 21:18:00 +0000 (21:18 +0000)]
Disable PDB injected sources test temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327451
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Hiroshi Yamauchi [Tue, 13 Mar 2018 21:13:18 +0000 (21:13 +0000)]
Simplify more cases of logical ops of masked icmps.
Summary:
For example,
((X & 255) != 0) && ((X & 15) == 8) -> ((X & 15) == 8).
((X & 7) != 0) && ((X & 15) == 8) -> false.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327450
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Eugene Zemtsov [Tue, 13 Mar 2018 21:10:15 +0000 (21:10 +0000)]
Remove explicit triple and data layout from the test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327449
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Craig Topper [Tue, 13 Mar 2018 20:36:28 +0000 (20:36 +0000)]
[DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with BUILD_VECTORS between LegalizeVectorOps and LegalizeDAG.
BUILD_VECTORs aren't themselves legalized until LegalizeDAG so we should still be able to create an "illegal" one before that. This helps combine with BUILD_VECTORS that are introduced during LegalizeVectorOps due to unrolling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327446
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Zachary Turner [Tue, 13 Mar 2018 20:16:37 +0000 (20:16 +0000)]
Update modulemap to exclude new DIA headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327444
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Eugene Zemtsov [Tue, 13 Mar 2018 20:06:33 +0000 (20:06 +0000)]
Fix debuglineinfo-path.ll
This fix is based on an assumption that some build bots are missing 'echo
-n'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327443
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Francis Visoiu Mistrih [Tue, 13 Mar 2018 19:53:16 +0000 (19:53 +0000)]
[MIR] Allow frame-setup and frame-destroy on the same instruction
Nothing prevents us from having both frame-setup and frame-destroy on
the same instruction.
When merging:
* frame-setup OPCODE1
* frame-destroy OPCODE2
into
* frame-setup frame-destroy OPCODE3
we want to be able to print and parse both flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327442
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Eugene Zemtsov [Tue, 13 Mar 2018 19:48:31 +0000 (19:48 +0000)]
Temporary disable debuglineinfo-path.ll to fix build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327441
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Anna Thomas [Tue, 13 Mar 2018 19:38:45 +0000 (19:38 +0000)]
Test Commit NFC. Updated comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327436
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