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Craig Topper [Fri, 21 Apr 2017 16:43:32 +0000 (16:43 +0000)]
[ValueTracking] Use APInt::setAllBits and APInt::intersects to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300997
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Craig Topper [Fri, 21 Apr 2017 16:13:15 +0000 (16:13 +0000)]
[APInt] Add compare/compareSigned methods that return -1, 0, 1. Reimplement slt/ult and friends using them
Currently sle and ule have to call slt/ult and eq to get the proper answer. This results in extra code for both calls and additional scans of multiword APInts.
This patch replaces slt/ult with a compareSigned/compare that can return -1, 0, or 1 so we can cover all the comparison functions with a single call.
While I was there I removed the activeBits calls and other checks at the start of the slow part of ult. Both of the activeBits calls potentially scan through each of the APInts separately. I can't imagine that's any better than just scanning them in parallel and doing the compares. Now we just share the code with tcCompare.
These changes seem to be good for about a 7-8k reduction on the size of the opt binary on my local x86-64 build.
Differential Revision: https://reviews.llvm.org/D32339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300995
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Juergen Ributzka [Fri, 21 Apr 2017 16:05:01 +0000 (16:05 +0000)]
Remove empty and unused header file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300994
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Daniel Sanders [Fri, 21 Apr 2017 15:59:56 +0000 (15:59 +0000)]
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
Summary:
The SelectionDAG importer now imports rules with Predicate's attached via
Requires, PredicateControl, etc. These predicates are implemented as
bitset's to allow multiple predicates to be tested together. However,
unlike the MC layer subtarget features, each target only pays for it's own
predicates (e.g. AArch64 doesn't have 192 feature bits just because X86
needs a lot).
Both AArch64 and X86 derive at least one predicate from the MachineFunction
or Function so they must re-initialize AvailableFeatures before each
function. They also declare locals in <Target>InstructionSelector so that
computeAvailableFeatures() can use the code from SelectionDAG without
modification.
Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab
Reviewed By: rovka
Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D31418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300993
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Craig Topper [Fri, 21 Apr 2017 15:53:42 +0000 (15:53 +0000)]
[SimplifyCFG] Fix the determination of PostBB in conditional store merging to handle the targets on the second branch being commuted
Currently we choose PostBB as the single successor of QFB, but its possible that QTB's single successor is QFB which would make QFB the correct choice.
Differential Revision: https://reviews.llvm.org/D32323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300992
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Wei Mi [Fri, 21 Apr 2017 15:50:16 +0000 (15:50 +0000)]
[ConstHoisting] Add BFI in constanthoisting pass and select the best insertion
places based on it.
Existing constant hoisting pass will merge a group of contants in a small range
and hoist the const materialization code to the common dominator of their uses.
However, if the uses are all in cold pathes, existing implementation may hoist
the materialization code from cold pathes to a hot place. This may hurt performance.
The patch introduces BFI to the pass and selects the best insertion places based
on it.
The change is controlled by an option consthoist-with-block-frequency which is
off by default for now.
Differential Revision: https://reviews.llvm.org/D28962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300989
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Chad Rosier [Fri, 21 Apr 2017 14:58:32 +0000 (14:58 +0000)]
[AArch64][Falkor] Refine modeling of store-release exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300987
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Joel Jones [Fri, 21 Apr 2017 14:49:27 +0000 (14:49 +0000)]
[Mips] Document Mips Backend Relocation Principles
This revision documents the combination of C++ and table-gen code that
handles relocations and addresses.
Thanks for Simon Dardis for the careful reviews.
Differential Revision: https://reviews.llvm.org/D31628
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300986
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Chad Rosier [Fri, 21 Apr 2017 14:33:13 +0000 (14:33 +0000)]
[AArch64][Falkor] Refine resource needs of STRQ with register offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300984
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Matthew Simpson [Fri, 21 Apr 2017 14:14:54 +0000 (14:14 +0000)]
[LV] Model if-converted phi node costs
Phi nodes in non-header blocks are converted to select instructions after
if-conversion. This patch updates the cost model to account for the selects.
Differential Revision: https://reviews.llvm.org/D31906
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300980
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Daniel Sanders [Fri, 21 Apr 2017 14:09:20 +0000 (14:09 +0000)]
Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I
haven't worked out why. Reverting to make it green while I figure it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300978
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Sanjay Patel [Fri, 21 Apr 2017 14:03:54 +0000 (14:03 +0000)]
[InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)
This matches the demanded bits behavior in the DAG and should fix:
https://bugs.llvm.org/show_bug.cgi?id=32706
Differential Revision: https://reviews.llvm.org/D32255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300977
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Chad Rosier [Fri, 21 Apr 2017 13:55:41 +0000 (13:55 +0000)]
[AArch64][Falkor] Refine loads/stores that require an extra LD pipe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300976
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Chad Rosier [Fri, 21 Apr 2017 13:37:01 +0000 (13:37 +0000)]
[AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300975
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Chad Rosier [Fri, 21 Apr 2017 13:36:57 +0000 (13:36 +0000)]
[AArch64] Fix a few missed pre/post-inc in Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300974
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Diana Picus [Fri, 21 Apr 2017 13:16:50 +0000 (13:16 +0000)]
[ARM] GlobalISel: Add support for G_TRUNC
Select them as copies. We only select if both the source and the
destination are on the same register bank, so this shouldn't cause any
trouble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300971
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Daniel Sanders [Fri, 21 Apr 2017 12:51:43 +0000 (12:51 +0000)]
[globalisel][tablegen] Try again to fix builds on old MSVC's after r300964
This should fix llvm-clang-x86_64-expensive-checks-win
I reproduced the error using the following code:
namespace llvm {
// Moving this out of the llvm namespace fixes the error.
template<unsigned NumBits> class PredicateBitsetImpl {};
}
namespace {
const unsigned MAX_SUBTARGET_PREDICATES = 11;
// This works on Clang but is broken on MSVC
// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
// Some versions emit a syntax error here ("error C2061: syntax error: identifier
// 'PredicateBitsetImpl'") but others accept it and only emit the C3646 below.
//
// This works on Clang and MSVC
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
class Foo {
private:
PredicateBitset A; // error C3646: 'A': unknown override specifier
};
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300970
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Daniel Sanders [Fri, 21 Apr 2017 12:08:25 +0000 (12:08 +0000)]
Revert: r300966 - [globalisel][tablegen] Attempt to fix builds on old MSVC's after r300964
It didn't fix the builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300968
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Diana Picus [Fri, 21 Apr 2017 11:53:01 +0000 (11:53 +0000)]
[ARM] GlobalISel: Make struct arguments fail elegantly
The condition in isSupportedType didn't handle struct/array arguments
properly. Fix the check and add a test to make sure we use the fallback
path in this kind of situation. The test deals with some common cases
where the call lowering should error out. There are still some issues
here that need to be addressed (tail calls come to mind), but they can
be addressed in other patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300967
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Daniel Sanders [Fri, 21 Apr 2017 11:29:29 +0000 (11:29 +0000)]
[globalisel][tablegen] Attempt to fix builds on old MSVC's after r300964
This should fix llvm-clang-x86_64-expensive-checks-win
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300966
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Daniel Sanders [Fri, 21 Apr 2017 10:27:20 +0000 (10:27 +0000)]
[globalisel][tablegen] Import SelectionDAG's rule predicates and support the equivalent in GIRule.
Summary:
The SelectionDAG importer now imports rules with Predicate's attached via
Requires, PredicateControl, etc. These predicates are implemented as
bitset's to allow multiple predicates to be tested together. However,
unlike the MC layer subtarget features, each target only pays for it's own
predicates (e.g. AArch64 doesn't have 192 feature bits just because X86
needs a lot).
Both AArch64 and X86 derive at least one predicate from the MachineFunction
or Function so they must re-initialize AvailableFeatures before each
function. They also declare locals in <Target>InstructionSelector so that
computeAvailableFeatures() can use the code from SelectionDAG without
modification.
Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab
Reviewed By: rovka
Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D31418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300964
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Clement Courbet [Fri, 21 Apr 2017 09:21:05 +0000 (09:21 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300963
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Clement Courbet [Fri, 21 Apr 2017 09:21:01 +0000 (09:21 +0000)]
add skylake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300962
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Clement Courbet [Fri, 21 Apr 2017 09:20:58 +0000 (09:20 +0000)]
add 32 bit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300961
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Clement Courbet [Fri, 21 Apr 2017 09:20:55 +0000 (09:20 +0000)]
use repmovsb when optimizing forminsize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300960
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Clement Courbet [Fri, 21 Apr 2017 09:20:50 +0000 (09:20 +0000)]
Rename FastString flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300959
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Clement Courbet [Fri, 21 Apr 2017 09:20:44 +0000 (09:20 +0000)]
add more tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300958
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Clement Courbet [Fri, 21 Apr 2017 09:20:39 +0000 (09:20 +0000)]
X86 memcpy: use REPMOVSB instead of REPMOVS{Q,D,W} for inline copies
when the subtarget has fast strings.
This has two advantages:
- Speed is improved. For example, on Haswell thoughput improvements increase
linearly with size from 256 to 512 bytes, after which they plateau:
(e.g. 1% for 260 bytes, 25% for 400 bytes, 40% for 508 bytes).
- Code is much smaller (no need to handle boundaries).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300957
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George Rimar [Fri, 21 Apr 2017 09:12:18 +0000 (09:12 +0000)]
[DWARF] - Refactoring: localize handling of relocations in a single place.
This is splitted from D32228,
currently DWARF parsers code has few places that applied relocations values manually.
These places has similar duplicated code. Patch introduces separate method that can be
used to obtain relocated value. That helps to reduce code and simplifies things.
Differential revision: https://reviews.llvm.org/D32284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300956
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Clement Courbet [Fri, 21 Apr 2017 07:40:59 +0000 (07:40 +0000)]
Delete dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300952
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Artyom Skrobov [Fri, 21 Apr 2017 07:35:21 +0000 (07:35 +0000)]
[Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing `Uses = [CPSR]`
Summary: Thanks to Oliver Stannard for helping catch this.
Reviewers: olista01, efriedma
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D31815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300951
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Serguei Katkov [Fri, 21 Apr 2017 06:14:38 +0000 (06:14 +0000)]
[AsmWriter] Eliminate warning. NFC
This patch eliminates the following warning
lib/IR/AsmWriter.cpp:1128:57: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
(StrVal[1] >= '0' && StrVal[1] <= '9')) &&
Reviewers: timshen, rnk, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D32337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300950
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George Burgess IV [Fri, 21 Apr 2017 04:54:52 +0000 (04:54 +0000)]
[MSSA] Clean up the updater a bit. NFC
- Mark an internal function static
- Remove the llvm namespace (just holding on to the `using namespace
llvm;` Works on My Machine(TM))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300947
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Davide Italiano [Fri, 21 Apr 2017 04:25:00 +0000 (04:25 +0000)]
[PartialInliner] Fix crash when inlining functions with unreachable blocks.
CodeExtractor looks up the dominator node corresponding to return blocks
when splitting them. If one of these blocks is unreachable, there's no
node in the Dom and CodeExtractor crashes because it doesn't check
for domtree node validity.
In theory, we could add just a check for skipping null DTNodes in
`splitReturnBlock` but the fix I propose here is slightly different. To the
best of my knowledge, unreachable blocks are irrelevant for the algorithm,
therefore we can just skip them when building the candidate set in the
constructor.
Differential Revision: https://reviews.llvm.org/D32335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300946
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Serguei Katkov [Fri, 21 Apr 2017 03:14:30 +0000 (03:14 +0000)]
[BPI] Add multiplication by scalar operators to BranchProbability
This patch just adds two operators to BranchProbability class:
(BP * scalar) and (BP *= scalar).
Reviewers: junbuml, chandlerc, sanjoy, vsk
Reviewed By: chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D32334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300945
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Serguei Katkov [Fri, 21 Apr 2017 02:52:17 +0000 (02:52 +0000)]
[AsmWriter/APFloat] FP constant printing: Avoid usage of locale dependent snprinf
This should fix the bug https://bugs.llvm.org/show_bug.cgi?id=12906
To print the FP constant AsmWriter does the following:
1) convert FP value to String (actually using snprintf function which is locale dependent).
2) Convert String back to FP Value
3) Compare original and got FP values. If they are not equal just dump as hex.
The problem happens on the 2nd step when APFloat does not expect group delimiter or
fraction delimiter other than period symbol and so on, which can be produced on the
first step if LLVM library is used in an environment with corresponding locale set.
To fix this issue the locale independent APFloat:toString function is used.
However it prints FP values slightly differently than snprintf does. Specifically
it suppress trailing zeros in significant, use capital E and so on.
It results in 117 test failures during make check.
To avoid this I've also updated APFloat.toString a bit to pass make check at least.
Reviewers: sberg, bogner, majnemer, sanjoy, timshen, rnk
Reviewed By: timshen, rnk
Subscribers: rnk, llvm-commits
Differential Revision: https://reviews.llvm.org/D32276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300943
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Akira Hatanaka [Fri, 21 Apr 2017 01:31:50 +0000 (01:31 +0000)]
Revert r300932 and r300930.
It seems that r300930 was creating an infinite loop in dag-combine when
compling the following file:
MultiSource/Benchmarks/MiBench/consumer-typeset/z21.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300940
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Akira Hatanaka [Fri, 21 Apr 2017 00:35:27 +0000 (00:35 +0000)]
[AArch64] Use suffix ULL to shift a 64-bit value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300932
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Davide Italiano [Fri, 21 Apr 2017 00:21:09 +0000 (00:21 +0000)]
[CodeExtractor] Remove an unneeded level of indirection. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300931
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Akira Hatanaka [Fri, 21 Apr 2017 00:05:16 +0000 (00:05 +0000)]
[AArch64] Improve code generation for logical instructions taking
immediate operands.
This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.
This recommits r300913, which broke bots because I didn't fix a call to
ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of
TargetLoweringOpt and TargetLowering.
rdar://problem/
18231627
Differential Revision: https://reviews.llvm.org/D5591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300930
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Eli Friedman [Thu, 20 Apr 2017 23:59:05 +0000 (23:59 +0000)]
Revert r300746 (SCEV analysis for or instructions).
There have been multiple reports of this causing problems: a
compile-time explosion on the LLVM testsuite, and a stack
overflow for an opencl kernel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300928
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Craig Topper [Thu, 20 Apr 2017 23:58:27 +0000 (23:58 +0000)]
[InstCombine] Remove the zextOrTrunc from ShrinkDemandedConstant.
The demanded mask and the constant should always be the same width for all callers today.
Also stop copying the demanded mask as its passed in. We should avoid allocating memory unless we are going to do something. The final AND to create the new constant will take care of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300927
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Matthias Braun [Thu, 20 Apr 2017 23:34:50 +0000 (23:34 +0000)]
X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFC
X86RegisterInfo::eliminateFrameIndex() and
X86FrameLowering::getFrameIndexReference() both had logic to compute the
base register. This consolidates the code.
Also use MachineInstr::isReturn instead of manually enumerating tail
call instructions (return instructions were not included in the previous
list because they never reference frame indexes).
Differential Revision: https://reviews.llvm.org/D32206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300923
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Matthias Braun [Thu, 20 Apr 2017 23:34:46 +0000 (23:34 +0000)]
X86RegisterInfo: eliminateFrameIndex: Force SP for AfterFPPop; NFC
AfterFPPop is used for tailcall/tailjump instructions. We shouldn't ever
have frame-pointer/base-pointer relative addressing for those. After all
the frame/base pointer should already be restored to their previous
values at the return.
Make this fact explicit in preparation for an upcoming refactoring.
Differential Revision: https://reviews.llvm.org/D32205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300922
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Sanjoy Das [Thu, 20 Apr 2017 23:07:00 +0000 (23:07 +0000)]
Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300918
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Akira Hatanaka [Thu, 20 Apr 2017 23:03:30 +0000 (23:03 +0000)]
Revert "[AArch64] Improve code generation for logical instructions taking"
This reverts r300913.
This broke bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300916
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Craig Topper [Thu, 20 Apr 2017 22:57:36 +0000 (22:57 +0000)]
[Simplify] Add testcase to show that merging conditional stores for triangles is sensitive to the order of the branch targets on the conditional branches. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300915
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Akira Hatanaka [Thu, 20 Apr 2017 22:47:56 +0000 (22:47 +0000)]
[AArch64] Improve code generation for logical instructions taking
immediate operands.
This commit adds an AArch64 dag-combine that optimizes code generation
for logical instructions taking immediate operands. The optimization
uses demanded bits to change a logical instruction's immediate operand
so that the immediate can be folded into the immediate field of the
instruction.
rdar://problem/
18231627
Differential Revision: https://reviews.llvm.org/D5591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300913
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Sanjay Patel [Thu, 20 Apr 2017 22:37:01 +0000 (22:37 +0000)]
[InstCombine] function names start with lower-case letter; NFC
Forgot to make this fix with the signature change in r300911.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300912
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Sanjay Patel [Thu, 20 Apr 2017 22:33:54 +0000 (22:33 +0000)]
[InstCombine] allow shl+shr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300911
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Sanjay Patel [Thu, 20 Apr 2017 22:18:47 +0000 (22:18 +0000)]
[InstCombine] add tests for shl+shr demanded bits splat vector folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300907
91177308-0d34-0410-b5e6-
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Tim Northover [Thu, 20 Apr 2017 21:57:45 +0000 (21:57 +0000)]
AArch64: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300905
91177308-0d34-0410-b5e6-
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Tim Northover [Thu, 20 Apr 2017 21:56:52 +0000 (21:56 +0000)]
ARM: lower "fence singlethread" to a pure compiler barrier.
Single-threaded fences aren't required to provide any synchronization with
other processing elements so there's no need for a DMB. They should still be a
barrier for compiler optimizations though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300904
91177308-0d34-0410-b5e6-
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Xinliang David Li [Thu, 20 Apr 2017 21:40:22 +0000 (21:40 +0000)]
Use basicblock split block utility function
Instead of calling BasicBlock::SplitBasicBlock directly in
CodeExtractor.
Differential Revision: https://reviews.llvm.org/D32308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300899
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Apr 2017 21:33:02 +0000 (21:33 +0000)]
[InstCombine] allow shl demanded bits folds with splat constants
More fixes are needed to enable the helper SimplifyShrShlDemandedBits().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300898
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 20 Apr 2017 21:24:37 +0000 (21:24 +0000)]
[InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few more places in SimplifyDemandedBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300896
91177308-0d34-0410-b5e6-
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Chad Rosier [Thu, 20 Apr 2017 21:11:17 +0000 (21:11 +0000)]
[AArch64] Whitespace/ordering fixes for Falkor machine description. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300893
91177308-0d34-0410-b5e6-
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Chad Rosier [Thu, 20 Apr 2017 21:11:09 +0000 (21:11 +0000)]
[AArch64] Refine Falkor machine description for pre/post-inc and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300892
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 20 Apr 2017 20:59:02 +0000 (20:59 +0000)]
[InstCombine] allow ashr/lshr demanded bits folds with splat constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300888
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 20 Apr 2017 20:47:35 +0000 (20:47 +0000)]
[InstCombine] Use APInt::isSubsetOf to simplify some code in SimplifyDemandedBits. NFC
This allows us to use less temporary APInt for And and Invert operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300885
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Sanjay Patel [Thu, 20 Apr 2017 20:44:54 +0000 (20:44 +0000)]
[InstCombine] add tests for demanded bits ashr/lshr splat constants; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300884
91177308-0d34-0410-b5e6-
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Adrian Prantl [Thu, 20 Apr 2017 20:42:33 +0000 (20:42 +0000)]
Don't emit locations that need a DW_OP_stack_value in DWARF 2 & 3.
https://bugs.llvm.org/show_bug.cgi?id=32382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300883
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Benjamin Kramer [Thu, 20 Apr 2017 20:28:18 +0000 (20:28 +0000)]
[Support] Make asan poisoning for recyclers more aggressive by also poisoning the 'next' pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300882
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Thu, 20 Apr 2017 20:03:36 +0000 (20:03 +0000)]
Remove stray ^S. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300880
91177308-0d34-0410-b5e6-
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Paul Robinson [Thu, 20 Apr 2017 20:03:03 +0000 (20:03 +0000)]
[DWARF] Fix a couple of typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300879
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Tim Northover [Thu, 20 Apr 2017 19:54:02 +0000 (19:54 +0000)]
ARM: handle post-indexed NEON ops where the offset isn't the access width.
Before, we assumed that any ConstantInt offset was precisely the access width,
so we could use the "[rN]!" form. ISelLowering only ever created that kind, but
further simplification during combining could lead to unexpected constants and
incorrect codegen.
Should fix PR32658.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300878
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Adrian McCarthy [Thu, 20 Apr 2017 19:34:06 +0000 (19:34 +0000)]
VarStreamArrayIterator needed non-const operator* overload.
Without this change, the operator-> provided by iterator_facade lost type
qualifiers.
Differential Revision: https://reviews.llvm.org/D32235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300877
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Craig Topper [Thu, 20 Apr 2017 19:31:22 +0000 (19:31 +0000)]
[InstCombine] Remove redundant code from SimplifyDemandedBits handling for Or. The code above it is equivalent if you work through the bitwise math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300876
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Paul Robinson [Thu, 20 Apr 2017 19:16:51 +0000 (19:16 +0000)]
[DWARF] Versioning for DWARF constants; verify FORMs
Associate the version-when-defined with definitions of standard DWARF
constants. Identify the "vendor" for DWARF extensions.
Use this information to verify FORMs in .debug_abbrev are defined as
of the DWARF version specified in the associated unit.
Removed two tests that had specified DWARF v1 (which essentially does
not exist).
Differential Revision: http://reviews.llvm.org/D30785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300875
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Benjamin Kramer [Thu, 20 Apr 2017 19:06:11 +0000 (19:06 +0000)]
[go bindings] Rmove duplicated conversion function definitions after r300843.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300872
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Chad Rosier [Thu, 20 Apr 2017 18:50:21 +0000 (18:50 +0000)]
[AArch64] Improve scheduling of logical operations on Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300871
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Weiming Zhao [Thu, 20 Apr 2017 18:37:14 +0000 (18:37 +0000)]
[Thumb-1] Fix corner cases for compressed jump tables
Summary:
When synthesized TBB/TBH is expanded, we need to avoid the case of:
BaseReg is redefined after the load of branching target. E.g.:
%R2 = tLEApcrelJT <jt#1>
%R1 = tLDRr %R1, %R2 ==> %R2 = tLEApcrelJT <jt#1>
%R2 = tLDRspi %SP, 12 %R2 = tLDRspi %SP, 12
tBR_JTr %R1 tTBB_JT %R2, %R1
`
Reviewers: jmolloy
Reviewed By: jmolloy
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D32250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300870
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Davide Italiano [Thu, 20 Apr 2017 18:33:40 +0000 (18:33 +0000)]
[CodeExtractor] Remove a bunch of unneeded constructors.
Differential Revision: https://reviews.llvm.org/D32305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300869
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Benjamin Kramer [Thu, 20 Apr 2017 18:29:37 +0000 (18:29 +0000)]
[Recycler] Add asan/msan annotations.
This enables use after free and uninit memory checking for memory
returned by a recycler. SelectionDAG currently relies on the opcode of a
free'd node being ISD::DELETED_NODE, so poke a hole in the asan poison
for SDNode opcodes. This means that we won't find some issues, but only
in SDag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300868
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Benjamin Kramer [Thu, 20 Apr 2017 18:29:14 +0000 (18:29 +0000)]
Fix use-after-frees on memory allocated in a Recycler.
This will become asan errors once the patch lands that poisons the
memory after free. The x86 change is a hack, but I don't see how to
solve this properly at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300867
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Artyom Skrobov [Thu, 20 Apr 2017 18:20:02 +0000 (18:20 +0000)]
Fixing outdated comment [NFC]
Since r32105 back in 2006, RegisterPass doesn't support
passes without a default constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300866
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Andrew Kaylor [Thu, 20 Apr 2017 18:18:36 +0000 (18:18 +0000)]
Fix formatting of constrained FP intrinsic documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300865
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Yaxun Liu [Thu, 20 Apr 2017 18:15:34 +0000 (18:15 +0000)]
CodeGen: Let frame index value type match alloca addr space
Recently alloca address space has been added to data layout. Due to this
change, pointer returned by alloca may have different size as pointer in
address space 0.
However, currently the value type of frame index is assumed to be of the
same size as pointer in address space 0.
This patch fixes that.
Most targets assume alloca returning pointer in address space 0, which
is the default alloca address space. Therefore it is NFC for them.
AMDGCN target with amdgiz environment requires this change since it
assumes alloca returning pointer to addr space 5 and its size is 32,
which is different from the size of pointer in addr space 0 which is 64.
Differential Revision: https://reviews.llvm.org/D32021
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300864
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Reid Kleckner [Thu, 20 Apr 2017 18:08:36 +0000 (18:08 +0000)]
Remove duplicate AttributeList::removeAttributes implementation
Have the AttributeList overload delegate to the AttrBuilder one.
Simplify the AttrBuilder overload by avoiding getSlotAttributes, which
creates temporary AttributeLists.
Simplify `AttrBuilder::removeAttributes(AttributeList, unsigned)` by
using getAttributes instead of manually iterating over slots.
Extracted from https://reviews.llvm.org/D32262
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300863
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Sanjay Patel [Thu, 20 Apr 2017 18:02:27 +0000 (18:02 +0000)]
[DAGCombiner] use more local variables in isAlias(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300860
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Sam Clegg [Thu, 20 Apr 2017 17:18:15 +0000 (17:18 +0000)]
[WebAssembly] Add known failures for wasm object file backend
Subscribers: jfb, dschuff
Differential Revision: https://reviews.llvm.org/D32300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300859
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Zachary Turner [Thu, 20 Apr 2017 16:56:54 +0000 (16:56 +0000)]
Resubmit "[BitVector] Add operator<<= and operator>>=."
This was failing due to the use of assigning a Mask to an
unsigned, rather than to a BitWord. But most systems do not
have sizeof(unsigned) == sizeof(unsigned long), so the mask
was getting truncated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300857
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Craig Topper [Thu, 20 Apr 2017 16:56:25 +0000 (16:56 +0000)]
[APInt] Rename getSignBit to getSignMask
getSignBit is a static function that creates an APInt with only the sign bit set. getSignMask seems like a better name to convey its functionality. In fact several places use it and then store in an APInt named SignMask.
Differential Revision: https://reviews.llvm.org/D32108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300856
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Amara Emerson [Thu, 20 Apr 2017 16:54:49 +0000 (16:54 +0000)]
[SVE] Fix mismatched sign comparison warning in unit test from r300842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300855
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Sanjay Patel [Thu, 20 Apr 2017 16:36:37 +0000 (16:36 +0000)]
[DAGCombiner] fix variable names in isAlias(); NFCI
We started with zero-based params and switched to one-based locals...
Also, variables start with a capital and functions do not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300854
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Zachary Turner [Thu, 20 Apr 2017 16:35:22 +0000 (16:35 +0000)]
Revert "[BitVector] Add operator<<= and operator>>=."
This is causing test failures on Linux / BSD systems. Reverting
while I investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300852
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Craig Topper [Thu, 20 Apr 2017 16:17:13 +0000 (16:17 +0000)]
[APInt] Add isSubsetOf method that can check if one APInt is a subset of another without creating temporary APInts
This question comes up in many places in SimplifyDemandedBits. This makes it easy to ask without allocating additional temporary APInts.
The BitVector class provides a similar functionality through its (IMHO badly named) test(const BitVector&) method. Though its output polarity is reversed.
I've provided one example use case in this patch. I plan to do more as a follow up.
Differential Revision: https://reviews.llvm.org/D32258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300851
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Sanjay Patel [Thu, 20 Apr 2017 16:15:08 +0000 (16:15 +0000)]
[DAGCombiner] give names to repeated calcs in isAlias(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300850
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 20 Apr 2017 16:14:58 +0000 (16:14 +0000)]
In SimplifyDemandedUseBits, use computeKnownBits directly to handle Constants
Currently we don't explicitly process ConstantDataSequential, ConstantAggregateZero, or ConstantVector, or Undef before applying the Depth limit. Instead they occur after the depth check in the non-instruction path.
For the constant types that we do handle, the code is replicated from computeKnownBits.
This patch fixes the missing constant handling and the reduces the amount of code by just using computeKnownBits directly for any type of Constant.
Differential Revision: https://reviews.llvm.org/D32123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300849
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Zachary Turner [Thu, 20 Apr 2017 15:57:58 +0000 (15:57 +0000)]
[BitVector] Add operator<<= and operator>>=.
Differential Revision: https://reviews.llvm.org/D32244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300848
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Daniel Sanders [Thu, 20 Apr 2017 15:46:12 +0000 (15:46 +0000)]
[globalisel] Enable tracing the legalizer with --debug-only=legalize-mir
Reviewers: t.p.northover, ab, qcolombet, aditya_nandakumar, rovka, kristof.beyls
Reviewed By: kristof.beyls
Subscribers: dberris, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D31750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300847
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Amaury Sechet [Thu, 20 Apr 2017 14:22:47 +0000 (14:22 +0000)]
Introduce LLVMDIBuilderRef
Summary:
This patch adds a definition of `LLVMDIBuilderRef` that represents an `llvm::DIBuilder`.
Authored by Harlan Haskins
Reviewers: deadalnix, aprantl, probinson, dblaikie, echristo, whitequark
Reviewed By: deadalnix, whitequark
Subscribers: CodaFi, loladiro
Differential Revision: https://reviews.llvm.org/D32122
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300843
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Amara Emerson [Thu, 20 Apr 2017 13:54:09 +0000 (13:54 +0000)]
[MVT][SVE] Scalable vector MVTs (3/3)
Adds MVT::ElementCount to represent the length of a
vector which may be scalable, then adds helper functions
that work with it.
Patch by Graham Hunter.
Differential Revision: https://reviews.llvm.org/D32019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300842
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Amara Emerson [Thu, 20 Apr 2017 13:36:58 +0000 (13:36 +0000)]
[MVT][SVE] Scalable vector MVTs (2/3)
Adds scalable vector machine value types, and updates
the switch statements required for tablegen.
Patch by Graham Hunter.
Differential Revision: https://reviews.llvm.org/D32018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300840
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Petar Jovanovic [Thu, 20 Apr 2017 13:26:46 +0000 (13:26 +0000)]
[mips][msa] Mask vectors holding shift amounts
Masked vectors which hold shift amounts when creating the following nodes:
ISD::SHL, ISD::SRL or ISD::SRA.
Instructions that use said nodes, which have had their arguments altered are
sll, srl, sra, bneg, bclr and bset.
For said instructions, the shift amount or the bit position that is
specified in the corresponding vector elements will be interpreted as the
shift amount/bit position modulo the size of the element in bits.
The problem lies in compiling with -O2 enabled, where the instructions for
formats .w and .d are not generated, but are instead optimized away.
In this case, having shift amounts that are either negative or greater than
the element bit size results in generation of incorrect results when
constant folding.
We remedy this by masking the operands for the nodes mentioned above before
actually creating them, so that the final result is correct before placed
into the constant pool.
Patch by Stefan Maksimovic.
Differential Revision: https://reviews.llvm.org/D31331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300839
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Amara Emerson [Thu, 20 Apr 2017 13:08:17 +0000 (13:08 +0000)]
[MVT][SVE] Scalable vector MVTs (1/3)
This patch adds a few helper functions to obtain new vector
value types based on existing ones without needing to care
about whether they are scalable or not.
I've confined their use to a few common locations right now,
and targets that don't have scalable vectors should never
need to care about these.
Patch by Graham Hunter.
Differential Revision: https://reviews.llvm.org/D32017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300838
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John Brawn [Thu, 20 Apr 2017 10:18:13 +0000 (10:18 +0000)]
[ARM] Fix handling of mapping symbols when changing sections
ChangeSection incorrectly registers LastEMSInfo as belonging to the previous
section, not the current section. This happens to work when changing sections
using .section, as the previous section is set to the current section before
the call to ChangeSection, but not when using .popsection.
Differential Revision: https://reviews.llvm.org/D32225
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300831
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John Brawn [Thu, 20 Apr 2017 10:13:54 +0000 (10:13 +0000)]
[AArch64] Fix handling of zero immediate in fmov instructions
Currently fmov #0 with a vector destination is handle incorrectly and results in
fmov #-1.9375 being emitted but should instead give an error. This is due to the
way we cope with fmov #0 with a scalar destination being an alias of fmov zr, so
fix this by actually doing it through an alias.
Differential Revision: https://reviews.llvm.org/D31949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300830
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John Brawn [Thu, 20 Apr 2017 10:10:10 +0000 (10:10 +0000)]
[AArch64] Fix handling of integer fp immediates
When an integer is used as an fp immediate we're failing to check the return
value of getFP64Imm, so invalid values are silently permitted. Fix this by
merging together the integer and real handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300828
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Diana Picus [Thu, 20 Apr 2017 09:38:25 +0000 (09:38 +0000)]
[ARM] Rename HW div feature to HW div Thumb. NFCI.
The hardware div feature refers only to Thumb, but because of its name
it is tempting to use it to check for hardware division in general,
which may cause problems in ARM mode. See https://reviews.llvm.org/D32005.
This patch adds "Thumb" to its name, to make its scope clear. One
notable place where I haven't made the change is in the feature flag
(used with -mattr), which is still hwdiv. Changing it would also require
changes in a lot of tests, including clang tests, and it doesn't seem
like it's worth the effort.
Differential Revision: https://reviews.llvm.org/D32160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300827
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