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Craig Topper [Fri, 15 Jun 2018 17:56:17 +0000 (17:56 +0000)]
[X86] Prevent folding stack reloads into instructions in hasUndefRegUpdate.
An earlier commit prevented folds from the peephole pass by checking for IMPLICIT_DEF. But later in the pipeline IMPLICIT_DEF just becomes and Undef flag on the input register so we need to check for that case too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334848
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Krzysztof Parzyszek [Fri, 15 Jun 2018 16:58:22 +0000 (16:58 +0000)]
Remove <undef> from rematerialized full register
When coalescing a small register into a subregister of a larger register,
if the larger register is rematerialized, the function updateRegDefUses
can add an <undef> flag to the rematerialized definition (since it's
treating it as only definining the coalesced subregister). While with that
assumption doing so is not incorrect, make sure to remove the flag later
on after the call to updateRegDefUses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334845
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Joseph Tremoulet [Fri, 15 Jun 2018 16:52:40 +0000 (16:52 +0000)]
[InstCombine] Avoid iteration/mutation conflict
Summary:
When iterating users of a multiply in processUMulZExtIdiom, the
call to setOperand in the truncation case may replace the use
being visited; make sure the iterator has been advanced before
doing that replacement.
Reviewers: majnemer, davide
Reviewed By: davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334844
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Sander de Smalen [Fri, 15 Jun 2018 16:39:46 +0000 (16:39 +0000)]
[AArch64][SVE] Asm: Support for CPY SIMD/FP and GPR instructions.
Predicated splat/copy of SIMD/FP register or general purpose
register to SVE vector, along with MOV-aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334842
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Jordan Rose [Fri, 15 Jun 2018 16:35:31 +0000 (16:35 +0000)]
Avoid copying PrettyStackTrace messages an extra time on Apple OSs
We were unnecessarily going from SmallString to std::string just to
get a null-terminated C string. So just...don't do that. Crash
slightly faster!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334841
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Diego Caballero [Fri, 15 Jun 2018 16:21:35 +0000 (16:21 +0000)]
[LV] Prevent LV to run cost model twice for VF=2
This is a minor fix for LV cost model, where the cost for VF=2 was
computed twice when the vectorization of the loop was forced without
specifying a VF.
Reviewers: xusx595, hsaito, fhahn, mkuper
Reviewed By: hsaito, xusx595
Differential Revision: https://reviews.llvm.org/D48048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334840
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Sander de Smalen [Fri, 15 Jun 2018 15:47:44 +0000 (15:47 +0000)]
[AArch64][SVE] Asm: Support for INC/DEC (scalar) instructions.
Increment/decrement scalar register by (scaled) element count given by
predicate pattern, e.g. 'incw x0, all, mul #4'.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334838
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Matt Arsenault [Fri, 15 Jun 2018 15:31:36 +0000 (15:31 +0000)]
AMDGPU: Add combine for short vector extract_vector_elts
Try to access pieces 4 bytes at a time. This helps
various hasOneUse extract_vector_elt combines, such
as load width reductions.
Avoids test regressions in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334836
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Matt Arsenault [Fri, 15 Jun 2018 15:15:46 +0000 (15:15 +0000)]
AMDGPU: Make v4i16/v4f16 legal
Some image loads return these, and it's awkward working
around them not being legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334835
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Paul Semel [Fri, 15 Jun 2018 14:15:02 +0000 (14:15 +0000)]
[llvm-readobj] Add -string-dump (-p) option
This option prints the section content as a string.
Differential Revision: https://reviews.llvm.org/D47989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334834
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Roman Lebedev [Fri, 15 Jun 2018 14:01:43 +0000 (14:01 +0000)]
[MCA] Add -summary-view option
Summary:
While that is indeed a quite interesting summary stat,
there are cases where it does not really add anything
other than consuming extra lines.
Declutters the output of D48190.
Reviewers: RKSimon, andreadb, courbet, craig.topper
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334833
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Roman Lebedev [Fri, 15 Jun 2018 14:01:35 +0000 (14:01 +0000)]
[MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-stats
Summary:
There does not seem to be any other tests for this.
Split off from D47676.
Reviewers: RKSimon, craig.topper, courbet, andreadb
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D48190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334832
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Sander de Smalen [Fri, 15 Jun 2018 13:57:51 +0000 (13:57 +0000)]
[AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: javed.absar
Differential Revision: https://reviews.llvm.org/D47712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334831
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Bjorn Pettersson [Fri, 15 Jun 2018 13:48:55 +0000 (13:48 +0000)]
Re-apply "[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue"
This is r334704 (which was reverted in r334732) with a fix for
types like x86_fp80. We need to use getTypeAllocSizeInBits and
not getTypeStoreSizeInBits to avoid dropping debug info for
such types.
Original commit msg:
> Summary:
> Do not convert a DbgDeclare to DbgValue if the store
> instruction only refer to a fragment of the variable
> described by the DbgDeclare.
>
> Problem was seen when for example having an alloca for an
> array or struct, and there were stores to individual elements.
> In the past we inserted a DbgValue intrinsics for each store,
> just as if the store wrote the whole variable.
>
> When handling store instructions we insert a DbgValue that
> indicates that the variable is "undefined", as we do not know
> which part of the variable that is updated by the store.
>
> When ConvertDebugDeclareToDebugValue is used with a load/phi
> instruction we assert that the referenced value is large enough
> to cover the whole variable. Afaict this should be true for all
> scenarios where those methods are used on trunk. If the assert
> blows in the future I guess we could simply skip to insert a
> dbg.value instruction.
>
> In the future I think we should examine which part of the variable
> that is accessed, and add a DbgValue instrinsic with an appropriate
> DW_OP_LLVM_fragment expression.
>
> Reviewers: dblaikie, aprantl, rnk
>
> Reviewed By: aprantl
>
> Subscribers: JDevlieghere, llvm-commits
>
> Tags: #debug-info
>
> Differential Revision: https://reviews.llvm.org/D48024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334830
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Simon Dardis [Fri, 15 Jun 2018 13:29:35 +0000 (13:29 +0000)]
[mips] Add licensing information of the microMIPS tablegen files. (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334827
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Sander de Smalen [Fri, 15 Jun 2018 13:11:49 +0000 (13:11 +0000)]
[AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates.
Some instructions require of a limited set of FP immediates as operands,
for example '#0.5 or #1.0' for SVE's FADD instruction.
This patch adds support for parsing and printing such FP immediates as
exact values (e.g. #0.499999 is not accepted for #0.5).
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334826
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Roman Lebedev [Fri, 15 Jun 2018 12:41:50 +0000 (12:41 +0000)]
[NFC] chmod +x utils/update_analyze_test_checks.py
Looks like a simple oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334825
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Matt Arsenault [Fri, 15 Jun 2018 12:09:15 +0000 (12:09 +0000)]
DAG: Fix creating concat_vectors with illegal type
Test passes as is, but fails with future patch to make v4i16/v4f16
legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334823
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Simon Pilgrim [Fri, 15 Jun 2018 10:29:37 +0000 (10:29 +0000)]
[SLP][X86] Add AVX2 run to POW2 SDIV Tests
Non-uniform pow2 tests are only make sense on targets with fast (low cost) non-uniform shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334821
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Simon Pilgrim [Fri, 15 Jun 2018 10:07:03 +0000 (10:07 +0000)]
[SLP][X86] Regenerate POW2 SDIV Tests
Added non-uniform pow2 test as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334819
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Roman Lebedev [Fri, 15 Jun 2018 09:56:52 +0000 (09:56 +0000)]
[InstCombine] Recommit: Fold (x << y) >> y -> x & (-1 >> y)
Summary:
We already do it for splat constants, but not just values.
Also, undef cases are mostly non-functional.
The original commit was reverted because
it broke tests for amdgpu backend, which i didn't check.
Now, the backed was updated to recognize these new
patterns, so we are good.
https://bugs.llvm.org/show_bug.cgi?id=37603
https://rise4fun.com/Alive/cplX
Reviewers: spatel, craig.topper, mareko, bogner, rampitec, nhaehnle, arsenm
Reviewed By: spatel, rampitec, nhaehnle
Subscribers: wdng, nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D47980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334818
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Roman Lebedev [Fri, 15 Jun 2018 09:56:45 +0000 (09:56 +0000)]
[AMDGPU] Recognize x & ~(-1 << y) pattern.
Summary: The same pattern as D48010, but this one is IR-canonical as of D47428.
Reviewers: nhaehnle, bogner, tstellar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #amdgpu
Differential Revision: https://reviews.llvm.org/D48012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334817
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Roman Lebedev [Fri, 15 Jun 2018 09:56:39 +0000 (09:56 +0000)]
[AMDGPU] Recognize x & ((1 << y) - 1) pattern.
Summary:
As a followup for D48007.
Since we already handle `x << (bitwidth - y) >> (bitwidth - y)` pattern,
which does not have ub for both the edge cases (`y == 0`, `y == bitwidth`),
i think also handling a pattern that is ub for `y == bitwidth` should be fine.
Reviewers: nhaehnle, bogner, tstellar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #amdgpu
Differential Revision: https://reviews.llvm.org/D48010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334816
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Roman Lebedev [Fri, 15 Jun 2018 09:56:31 +0000 (09:56 +0000)]
[AMDGPU] Recognize x & (-1 >> (32 - y)) pattern.
Summary:
D47980 will canonicalize the `x << (32 - y) >> (32 - y)`,
which is the pattern the AMDGPU expects to `x & (-1 >> (32 - y))`,
which is not recognized by AMDGPU.
Thus, it needs to be recognized, too.
Reviewers: nhaehnle, bogner, tstellar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #amdgpu
Differential Revision: https://reviews.llvm.org/D48007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334815
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Peter Smith [Fri, 15 Jun 2018 09:48:18 +0000 (09:48 +0000)]
[MC] Move bundling and MCSubtargetInfo to MCEncodedFragment [NFC]
Instruction bundling is only supported on descendants of the
MCEncodedFragment type. By moving the bundling functionality and
MCSubtargetInfo to this class it makes it easier to set and extract the
MCSubtargetInfo when it is necessary.
This is a refactoring change that will make it easier to pass the
MCSubtargetInfo through to writeNops when nop padding is required.
Differential Revision: https://reviews.llvm.org/D45959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334814
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Clement Courbet [Fri, 15 Jun 2018 09:46:57 +0000 (09:46 +0000)]
[llvm-exegesis][NFC] Remove dead variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334813
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Clement Courbet [Fri, 15 Jun 2018 09:27:12 +0000 (09:27 +0000)]
[llvm-exegesis][NFC] Add more comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334811
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QingShan Zhang [Fri, 15 Jun 2018 08:34:41 +0000 (08:34 +0000)]
add myself to the CREDITS.TXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334808
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Mikhail Dvoretckii [Fri, 15 Jun 2018 07:59:29 +0000 (07:59 +0000)]
NFC: Regenerating x86-sse41.ll test for InstCombine
Test regenerated to reduce noise in further patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334806
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Clement Courbet [Fri, 15 Jun 2018 07:30:45 +0000 (07:30 +0000)]
[llvm-exegesis] Print the whole snippet in analysis.
Summary:
On hover, the whole asm snippet is displayed, including operands.
This requires the actual assembly output instead of just the MCInsts:
This is because some pseudo-instructions get lowered to actual target
instructions during codegen (e.g. ABS_Fp32 -> SSE or X87).
Reviewers: gchatelet
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334805
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Craig Topper [Fri, 15 Jun 2018 06:15:26 +0000 (06:15 +0000)]
Revert r334802 "[X86] Prevent folding stack reloads with instructions that have an undefined register update."
There's a typo causing the build to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334803
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Craig Topper [Fri, 15 Jun 2018 06:11:36 +0000 (06:11 +0000)]
[X86] Prevent folding stack reloads with instructions that have an undefined register update.
We want to keep the load unfolded so we can use the same register for both sources to avoid a false dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334802
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Craig Topper [Fri, 15 Jun 2018 05:49:19 +0000 (05:49 +0000)]
[X86] Add more instructions to the memory folding tables using the autogenerated table as a guide.
I think this covers most of the unmasked vector instructions. We're still missing a lot of the masked instructions.
There are some test changes here because of the new folding support. I don't think these particular cases should be folded because it creates an undef register dependency. I think the changes introduced in r334175 are not handling stack folding. They're only blocking the peephole pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334800
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Hiroshi Inoue [Fri, 15 Jun 2018 05:10:09 +0000 (05:10 +0000)]
[NFC] fix trivial typos in documents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334799
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Craig Topper [Fri, 15 Jun 2018 04:42:55 +0000 (04:42 +0000)]
[X86] Fix some checks to use X86 instead of X32.
These tests were recently updated so it looks like gone wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334786
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Craig Topper [Fri, 15 Jun 2018 04:42:54 +0000 (04:42 +0000)]
[X86] Add 'Z' to the internal names of various EVEX instructions for overall consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334785
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Andrew Kaylor [Fri, 15 Jun 2018 00:07:28 +0000 (00:07 +0000)]
Add debug info for OProfile profiling support
Patch by Gaetano Priori
Differential Revision: https://reviews.llvm.org/D47925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334782
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Shoaib Meenai [Thu, 14 Jun 2018 23:40:04 +0000 (23:40 +0000)]
[cmake] Change ON/OFF to YES/NO. NFC
compnerd pointed out that the latter reads better over here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334781
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Shoaib Meenai [Thu, 14 Jun 2018 23:26:33 +0000 (23:26 +0000)]
[cmake] Add linker detection for Apple platforms
LLVM currently assumes that Apple platforms will always use ld64. In the
future, LLD Mach-O might also be supported, so add the beginnings of
linker detection support. ld64 is currently the only detected linker,
since `ld64.lld -v` doesn't yield any useful version output, but we can
add that detection later, and in the meantime it's still useful to have
the ld64 identification.
Switch clang's order file check to use this new detection rather than
just checking for the presence of an ld64 executable.
Differential Revision: https://reviews.llvm.org/D48201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334780
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Eli Friedman [Thu, 14 Jun 2018 22:58:48 +0000 (22:58 +0000)]
Make uitofp and sitofp defined on overflow.
IEEE 754 defines the expected result on overflow. As far as I know,
hardware implementations (of f16), and compiler-rt (__floatuntisf)
correctly return +-Inf on overflow. And I can't think of any useful
transform that would take advantage of overflow being undefined here.
Differential Revision: https://reviews.llvm.org/D47807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334777
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Lang Hames [Thu, 14 Jun 2018 21:16:29 +0000 (21:16 +0000)]
[ORC] Strip weak flags from a symbol once it is selected for materialization.
Once a symbol has been selected for materialization it can no longer be
overridden. Stripping the weak flag guarantees this (override attempts will
then be treated as duplicate definitions and result in a DuplicateDefinition
error).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334771
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Matt Davis [Thu, 14 Jun 2018 20:58:54 +0000 (20:58 +0000)]
[llvm-mca] Clean up the header comment. NFC.
This change removes a few dashes to make room for the header syntax string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334770
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Michael Berg [Thu, 14 Jun 2018 20:54:13 +0000 (20:54 +0000)]
easing the constraint for isNegatibleForFree and GetNegatedExpression
Summary:
Here we relax the old constraint which utilized unsafe with the TargetOption flag HonorSignDependentRoundingFPMathOption, with the assertion that unsafe is no longer needed or never was required for correctness on FDIV/FMUL.
Reviewers: spatel, hfinkel, wristow, arsenm, javed.absar
Reviewed By: spatel
Subscribers: efriedma, wdng, tpr
Differential Revision: https://reviews.llvm.org/D48057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334769
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Florian Hahn [Thu, 14 Jun 2018 20:32:58 +0000 (20:32 +0000)]
Revert r334764, as it breaks some bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334767
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Florian Hahn [Thu, 14 Jun 2018 20:23:48 +0000 (20:23 +0000)]
[TableGen] Make TreePatternNode::getChild return a reference (NFC)
The return value of TreePatternNode::getChild is never null. This patch also
updates various places that use return values of getChild to also use
references. Those changes were suggested post-commit for D47463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334764
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George Burgess IV [Thu, 14 Jun 2018 19:55:53 +0000 (19:55 +0000)]
[MSSA] Print more optimization information
In particular, when asked to print a MemoryAccess, we'll now print where
defs are optimized to, and we'll print optimized access types.
This patch also introduces an operator<< to make printing AliasResults
easier.
Patch by Juneyoung Lee!
Differential Revision: https://reviews.llvm.org/D47860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334760
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Sanjay Patel [Thu, 14 Jun 2018 19:55:02 +0000 (19:55 +0000)]
[x86] be more selective about converting 'and' to shuffle (PR37749)
isVectorClearMaskLegal() is the TLI hook used by the generic
DAGCombiner::XformToShuffleWithZero().
We've grown to accomodate/expect this transform to shuffle
(disabling it more generally results in many regressions).
So I'm narrowly excluding the 256-bit types that clearly
are not worthwhile for AVX1.
I think in most cases we are able to recover by converting
the shuffle back into 'and' ops, but the cases in:
https://bugs.llvm.org/show_bug.cgi?id=37749
...show that there are cracks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334759
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Craig Topper [Thu, 14 Jun 2018 19:28:31 +0000 (19:28 +0000)]
[X86] Fix stale comment in folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334758
91177308-0d34-0410-b5e6-
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Tom Stellard [Thu, 14 Jun 2018 19:26:37 +0000 (19:26 +0000)]
AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.cvt.pkrtz
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45907
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334757
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Justin Bogner [Thu, 14 Jun 2018 19:24:03 +0000 (19:24 +0000)]
Re-apply "[VirtRegRewriter] Avoid clobbering registers when expanding copy bundles"
This is r334750 (which was reverted in r334754) with a fix for an
uninitialized variable that was caught by msan.
Original commit message:
> If a copy bundle happens to involve overlapping registers, we can end
> up with emitting the copies in an order that ends up clobbering some
> of the subregisters. Since instructions in the copy bundle
> semantically happen at the same time, this is incorrect and we need to
> make sure we order the copies such that this doesn't happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334756
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Justin Bogner [Thu, 14 Jun 2018 19:10:57 +0000 (19:10 +0000)]
Revert "[VirtRegRewriter] Avoid clobbering registers when expanding copy bundles"
There's an msan failure:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19549
This reverts r334750.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334754
91177308-0d34-0410-b5e6-
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Michael Berg [Thu, 14 Jun 2018 18:48:31 +0000 (18:48 +0000)]
updating isNegatibleForFree and GetNegatedExpression with fmf for fadd
Summary: A FMF constraint is added to FADD with unsafe still available as the fallback
Reviewers: spatel, wristow, arsenm, hfinkel
Reviewed By: spatel
Subscribers: wdng
Differential Revision: https://reviews.llvm.org/D48180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334753
91177308-0d34-0410-b5e6-
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Sam Clegg [Thu, 14 Jun 2018 18:48:19 +0000 (18:48 +0000)]
[WebAssembly] Ignore explicit section names for functions
WebAssembly doesn't support more than one function per section
and we rely on function sections being unique. This change ignores
the section provided by the function to avoid two functions being
in the same section.
Without this change the object writer produces the following
error for this test:
LLVM ERROR: section already has a defining function: baz
Differential Revision: https://reviews.llvm.org/D48178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334752
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Justin Bogner [Thu, 14 Jun 2018 18:32:55 +0000 (18:32 +0000)]
[VirtRegRewriter] Avoid clobbering registers when expanding copy bundles
If a copy bundle happens to involve overlapping registers, we can end
up with emitting the copies in an order that ends up clobbering some
of the subregisters. Since instructions in the copy bundle
semantically happen at the same time, this is incorrect and we need to
make sure we order the copies such that this doesn't happen.
Differential Revision: https://reviews.llvm.org/D48154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334750
91177308-0d34-0410-b5e6-
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Bruno Cardoso Lopes [Thu, 14 Jun 2018 18:19:54 +0000 (18:19 +0000)]
[CMAKE] Honor CMAKE_OSX_SYSROOT to compute include dir for libxml2
On MacOS, if CMAKE_OSX_SYSROOT is used and the user has command line tools
installed, we currently get the include path for libxml2 as
/usr/include/libxml2, instead of ${CMAKE_OSX_SYSROOT}/usr/include/libxml2.
Make it consistent on MacOS by prefixing ${CMAKE_OSX_SYSROOT} when
possible.
rdar://problem/
41103601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334746
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Sanjay Patel [Thu, 14 Jun 2018 18:08:06 +0000 (18:08 +0000)]
[x86] add tests for AVX1 FP logic op abuse (PR37749); NFC
Also, add a RUN for AVX2 to make sure that's good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334744
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Andrea Di Biagio [Thu, 14 Jun 2018 17:48:42 +0000 (17:48 +0000)]
[llvm-mca] Add tests for instructions that implicitly clear the upper portion of a super-register.
On x86-64, a write to register EAX implicitly clears the upper half or RAX.
128-bit AVX instructions clear the upper 128-bit of the YMM register that
aliases the XMM definition register.
llvm-mca doesn't know about register writes that implicitly clear the upper
portion of an aliasing super-register. This issue will be fixed in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334742
91177308-0d34-0410-b5e6-
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Tomasz Krupa [Thu, 14 Jun 2018 17:32:58 +0000 (17:32 +0000)]
[X86] Lowering Mask Scalar intrinsics to native IR (LLVM part)
Summary: Complementary patch to lowering add, sub, mul and div mask scalar
intrinsics in Clang.
Reviewers: craig.topper, sroland, spatel, RKSimon
Reviewed by: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47978
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334740
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Justin Lebar [Thu, 14 Jun 2018 17:14:01 +0000 (17:14 +0000)]
[SCEV] Fix a variable name, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334738
91177308-0d34-0410-b5e6-
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Justin Lebar [Thu, 14 Jun 2018 17:13:48 +0000 (17:13 +0000)]
[SCEV] Simplify zext/trunc idiom that appears when handling bitmasks.
Summary:
Specifically, we transform
zext(2^K * (trunc X to iN)) to iM ->
2^K * (zext(trunc X to i{N-K}) to iM)<nuw>
This is helpful because pulling the 2^K out of the zext allows further
optimizations.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits, timshen
Differential Revision: https://reviews.llvm.org/D48158
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334737
91177308-0d34-0410-b5e6-
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Justin Lebar [Thu, 14 Jun 2018 17:13:35 +0000 (17:13 +0000)]
[SCEV] Simplify trunc-of-add/mul to add/mul-of-trunc under more circumstances.
Summary:
Previously we would do this simplification only if it did not introduce
any new truncs (excepting new truncs which replace other cast ops).
This change weakens this condition: If the number of truncs stays the
same, but we're able to transform trunc(X + Y) to X + trunc(Y), that's
still simpler, and it may open up additional transformations.
While we're here, also clean up some duplicated code.
Reviewers: sanjoy
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D48160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334736
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Justin Lebar [Thu, 14 Jun 2018 17:13:22 +0000 (17:13 +0000)]
[SCEV] Fix indentation and combine two if statements in getMulExpr, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334735
91177308-0d34-0410-b5e6-
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Sam Clegg [Thu, 14 Jun 2018 17:11:19 +0000 (17:11 +0000)]
Revert "[MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer."
This reverts rL331412. We didn't up using fragment atoms
in the wasm object writer after all.
Differential Revision: https://reviews.llvm.org/D48173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334734
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Tony Tye [Thu, 14 Jun 2018 16:40:10 +0000 (16:40 +0000)]
[AMDGPU] Document the AMDGPU LLVM attributes
Differential Revision: https://reviews.llvm.org/D48101
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334733
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Bjorn Pettersson [Thu, 14 Jun 2018 16:08:22 +0000 (16:08 +0000)]
Revert rL334704: "[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue"
This reverts commit r334704.
Buildbots detected an assertion in "test tsan in debug compiler-rt build".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334732
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Nirav Dave [Thu, 14 Jun 2018 15:55:15 +0000 (15:55 +0000)]
Avoid unused variable in non-assert builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334731
91177308-0d34-0410-b5e6-
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Andrea Di Biagio [Thu, 14 Jun 2018 15:54:34 +0000 (15:54 +0000)]
[llvm-mca] Add another test for partial register stalls.
This test checks that a physical register is correctly allocated for the partial
write to register BX.
The ADD instruction has to wait for the write to RBX (and BX) before being
executed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334730
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Nirav Dave [Thu, 14 Jun 2018 15:46:23 +0000 (15:46 +0000)]
[DAG] Avoid needing to walk out legalization tables. NFCI.
To avoid redundant work, during DAG legalization we keep tables
mapping pre-legalized SDValues to post-legalized SDValues and a
SDValue-to-SDValue map to enable fast node replacements. However, as
the keys are nodes which may be reused it is possible that an entry in
a table refers to a now deleted node N (that should have been renamed
by the value replacement map) while a new node N' exists. If N' is
then replaced that entry would be wrong. Previously we avoided this by
when potentially violating this property, walking every table and
updating all node pointers. This is very expensive but hopefully rare
occurance.
This patch assigns each instance of a SDValue used in legalization a
unique id and uses these ids in the legalization tables. This avoids
any such aliasing issue, avoiding the full table search and allowing
more aggressive incremental table pruning.
In some cases this is a 1000x speedup to compilation.
Reviewers: jyknight, echristo, bogner, tra
Reviewed By: bogner
Subscribers: dberris, grandinj, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D47959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334729
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Craig Topper [Thu, 14 Jun 2018 15:40:31 +0000 (15:40 +0000)]
[X86] Add more vector instructions to the memory folding table using the autogenerated table as a guide.
The test cahnge is because we now fold stack reload into RNDSCALE and RNDSCALE can be turned into ROUND by EVEX->VEX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334728
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 14 Jun 2018 15:40:30 +0000 (15:40 +0000)]
[X86] Remove '128' from the internal name of some scalar FP instructions to be consistent with other scalar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334727
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 14 Jun 2018 15:40:29 +0000 (15:40 +0000)]
[X86] Disable load unfolding for a bunch of instruction where unfolding would increase the size of the load.
Found by an audit of the manual table vs the autogenerated table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334726
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Craig Topper [Thu, 14 Jun 2018 15:40:27 +0000 (15:40 +0000)]
[X86] Remove NotMemoryFoldable from some AVX/AVX512 scalar instructions.
Some of these instructions are already in the manual folding table so we should have them in the auto table too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334725
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Lang Hames [Thu, 14 Jun 2018 15:32:59 +0000 (15:32 +0000)]
[ORC] Filter out self-dependencies in VSO::addDependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334724
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Lang Hames [Thu, 14 Jun 2018 15:32:59 +0000 (15:32 +0000)]
[ORC] Assert that the query argument to VSO::lookup must be non-null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334723
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Lang Hames [Thu, 14 Jun 2018 15:32:58 +0000 (15:32 +0000)]
[ORC] Add a WaitUntilReady argument to blockingLookup.
If WaitUntilReady is set to true then blockingLookup will return once all
requested symbols are ready. If WaitUntilReady is set to false then
blockingLookup will return as soon as all requested symbols have been
resolved. In the latter case, if any error occurs in finalizing the symbols it
will be reported to the ExecutionSession, rather than returned by
blockingLookup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334722
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Lang Hames [Thu, 14 Jun 2018 15:32:56 +0000 (15:32 +0000)]
[ORC] Strip the Materializing flag off finalized symbols in VSOs.
Finalized symbols are no longer in the materializing state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334721
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Simon Dardis [Thu, 14 Jun 2018 15:16:37 +0000 (15:16 +0000)]
[docs] Update CompilerWriterInfo.rst for MIPS
Update the URL of where the documentation can be found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334720
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Simon Pilgrim [Thu, 14 Jun 2018 14:22:03 +0000 (14:22 +0000)]
[EarlyCSE] Fix MSVC build. NFCI.
MSVC doesn't let you assign different lambdas through a ternary operator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334715
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Simon Pilgrim [Thu, 14 Jun 2018 14:20:20 +0000 (14:20 +0000)]
[CostModel][AArch64] Add cost tests for ALTERNATE/SELECT style shuffle masks
Precursor to fixing a regression with SLP vectorizer for supporting SELECT shuffles (vs the current ALTERNATE)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334714
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Sam Clegg [Thu, 14 Jun 2018 14:04:23 +0000 (14:04 +0000)]
[MC] Move MCAssembler::dump into the correct cpp file. NFC
Differential Revision: https://reviews.llvm.org/D46556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334713
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Paul Robinson [Thu, 14 Jun 2018 13:38:20 +0000 (13:38 +0000)]
[DWARFv5] Tolerate files not all having an MD5 checksum.
In some cases, for example when compiling a preprocessed file, the
front-end is not able to provide an MD5 checksum for all files. When
that happens, omit the MD5 checksums from the final DWARF, because
DWARF doesn't have a way to indicate that some but not all files have
a checksum.
When assembling a .s file, and some but not all .file directives
provide an MD5 checksum, issue a warning and don't emit MD5 into the
DWARF.
Fixes PR37623.
Differential Revision: https://reviews.llvm.org/D48135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334710
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Simon Dardis [Thu, 14 Jun 2018 13:03:53 +0000 (13:03 +0000)]
[mips] Correct predicates for MSA pseudo instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334708
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Max Kazantsev [Thu, 14 Jun 2018 13:02:13 +0000 (13:02 +0000)]
[EarlyCSE] Propagate conditions of AND and OR instructions
This patches teaches EarlyCSE to figure out that if `and i1 %x, %y` is true then both
`%x` and `%y` are true in the taken branch, and if `or i1 %x, %y` is false then both
`%x` and `%y` are false in non-taken branch. Fix for PR37635.
Differential Revision: https://reviews.llvm.org/D47574
Reviewed By: reames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334707
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Florian Hahn [Thu, 14 Jun 2018 11:56:19 +0000 (11:56 +0000)]
[TableGen] Move some shared_ptrs to avoid unnecessary copies (NFC).
Those changes were suggested post-commit for D47463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334706
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Bjorn Pettersson [Thu, 14 Jun 2018 11:23:42 +0000 (11:23 +0000)]
[DebugInfo] Check size of variable in ConvertDebugDeclareToDebugValue
Summary:
Do not convert a DbgDeclare to DbgValue if the store
instruction only refer to a fragment of the variable
described by the DbgDeclare.
Problem was seen when for example having an alloca for an
array or struct, and there were stores to individual elements.
In the past we inserted a DbgValue intrinsics for each store,
just as if the store wrote the whole variable.
When handling store instructions we insert a DbgValue that
indicates that the variable is "undefined", as we do not know
which part of the variable that is updated by the store.
When ConvertDebugDeclareToDebugValue is used with a load/phi
instruction we assert that the referenced value is large enough
to cover the whole variable. Afaict this should be true for all
scenarios where those methods are used on trunk. If the assert
blows in the future I guess we could simply skip to insert a
dbg.value instruction.
In the future I think we should examine which part of the variable
that is accessed, and add a DbgValue instrinsic with an appropriate
DW_OP_LLVM_fragment expression.
Reviewers: dblaikie, aprantl, rnk
Reviewed By: aprantl
Subscribers: JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D48024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334704
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Simon Pilgrim [Thu, 14 Jun 2018 10:25:19 +0000 (10:25 +0000)]
[SLPVectorizer] Remove RawInstructionsData/getMainOpcode and merge into getSameOpcode
This is part of the work to cleanup use of 'alternate' ops so we can use the more general SK_Select shuffle type.
Only getSameOpcode calls getMainOpcode and much of the logic is repeated in both functions. This will require some reworking of D28907 but that patch has hit trouble and is unlikely to be completed anytime soon.
Differential Revision: https://reviews.llvm.org/D48120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334701
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 14 Jun 2018 09:48:19 +0000 (09:48 +0000)]
[CostModel] Cleanup isSingleSourceVectorMask to match other shuffle matchers. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334699
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 14 Jun 2018 09:35:00 +0000 (09:35 +0000)]
[CostModel] Recognise REVERSE shuffle mask if the elements come from the second src
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334698
91177308-0d34-0410-b5e6-
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Clement Courbet [Thu, 14 Jun 2018 06:57:52 +0000 (06:57 +0000)]
[llvm-exegesis] Use BenchmarkResult::Instructions instead of OpcodeName
Summary:
Get rid of OpcodeName.
To remove the opcode name from an old file:
```
cat old_file | sed '/opcode_name.*/d'
```
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334691
91177308-0d34-0410-b5e6-
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Hiroshi Inoue [Thu, 14 Jun 2018 05:41:49 +0000 (05:41 +0000)]
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334687
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 14 Jun 2018 03:16:58 +0000 (03:16 +0000)]
[x86] fix mappings of cvttp2si/cvttp2ui x86 intrinsics to x86-specific nodes and isel patterns (PR37551)
Summary:
The tests in:
https://bugs.llvm.org/show_bug.cgi?id=37751
...show miscompiles because we wrongly mapped and folded x86-specific intrinsics into generic DAG nodes.
This patch corrects the mappings in X86IntrinsicsInfo.h and adds isel matching corresponding to the new patterns. The complete tests for the failure cases should be in avx-cvttp2si.ll and sse-cvttp2si.ll and avx512-cvttp2i.ll
Reviewers: RKSimon, gbedwell, spatel
Reviewed By: spatel
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D47993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334685
91177308-0d34-0410-b5e6-
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Matt Davis [Thu, 14 Jun 2018 01:20:18 +0000 (01:20 +0000)]
[llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class).
Summary: This patch transforms the Scheduler class into the ExecuteStage. Most of the logic remains.
Reviewers: andreadb, RKSimon, courbet
Reviewed By: andreadb
Subscribers: mgorny, javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334679
91177308-0d34-0410-b5e6-
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Tom Stellard [Wed, 13 Jun 2018 22:30:47 +0000 (22:30 +0000)]
AMDGPU/GlobalISel: Implement select() for 32-bit G_FADD and G_FMUL
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46171
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334665
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Zachary Turner [Wed, 13 Jun 2018 21:24:19 +0000 (21:24 +0000)]
Revert "Enable ThreadPool to queue tasks that return values."
This is failing to compile when LLVM_ENABLE_THREADS is false,
and the fix is not immediately obvious, so reverting while I look
into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334658
91177308-0d34-0410-b5e6-
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Francis Visoiu Mistrih [Wed, 13 Jun 2018 21:03:56 +0000 (21:03 +0000)]
Reland: [Timers] Use the pass argument name for JSON keys in time-passes
When using clang --save-stats -mllvm -time-passes, both timers and stats
end up in the same json file.
We could end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.Virtual Register Map.wall": 2.
9015541076660156e-04,
"time.pass.Virtual Register Map.user": 2.
0500000000000379e-04,
"time.pass.Virtual Register Map.sys": 8.
5000000000001741e-05,
}
This patch makes use of the pass argument name (if available) in the
JSON key to end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.virtregmap.wall": 2.
9015541076660156e-04,
"time.pass.virtregmap.user": 2.
0500000000000379e-04,
"time.pass.virtregmap.sys": 8.
5000000000001741e-05,
}
This also helps avoiding to write another JSON printer to handle all the
cases that we could have in our pass names.
Fixed test instead of adding a new one originally from r334649.
Differential Revision: https://reviews.llvm.org/D48109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334657
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Wed, 13 Jun 2018 20:59:53 +0000 (20:59 +0000)]
[TableGen] Make getOnlyTree return a const ref (NFC)
This avoids some unnecessary copies of shared_ptrs.
Those changes were suggested post-commit for D47463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334656
91177308-0d34-0410-b5e6-
96231b3b80d8
George Karpenkov [Wed, 13 Jun 2018 20:48:53 +0000 (20:48 +0000)]
Update comments of CheckedArithmetic API based on Philip Reames feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334655
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 13 Jun 2018 20:47:21 +0000 (20:47 +0000)]
[WinASan] Don't instrument globals in sections containing '$'
Such globals are very likely to be part of a sorted section array, such
the .CRT sections used for dynamic initialization. The uses its own
sorted sections called ATL$__a, ATL$__m, and ATL$__z. Instead of special
casing them, just look for the dollar sign, which is what invokes linker
section sorting for COFF.
Avoids issues with ASan and the ATL uncovered after we started
instrumenting comdat globals on COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334653
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Jun 2018 20:44:02 +0000 (20:44 +0000)]
Revert r334649 "[Timers] Use the pass argument name for JSON keys in time-passes"
This reverts commit r334649.
This breaks a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334651
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Jun 2018 20:09:59 +0000 (20:09 +0000)]
[Timers] Use the pass argument name for JSON keys in time-passes
When using clang --save-stats -mllvm -time-passes, both timers and stats
end up in the same json file.
We could end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.Virtual Register Map.wall": 2.
9015541076660156e-04,
"time.pass.Virtual Register Map.user": 2.
0500000000000379e-04,
"time.pass.Virtual Register Map.sys": 8.
5000000000001741e-05,
}
This patch makes use of the pass argument name (if available) in the
JSON key to end up with things like:
{
"asm-printer.EmittedInsts": 1,
"time.pass.virtregmap.wall": 2.
9015541076660156e-04,
"time.pass.virtregmap.user": 2.
0500000000000379e-04,
"time.pass.virtregmap.sys": 8.
5000000000001741e-05,
}
This also helps avoiding to write another JSON printer to handle all the
cases that we could have in our pass names.
Differential Revision: https://reviews.llvm.org/D48109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334649
91177308-0d34-0410-b5e6-
96231b3b80d8