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Craig Topper [Wed, 14 Mar 2018 17:57:19 +0000 (17:57 +0000)]
[X86] Add back fast-isel code for handling i8 shifts.
I removed this in r316797 because the coverage report showed no coverage and I thought it should have been handled by the auto generated table. I now see that there is code that bypasses the table if the shift amount is out of bounds.
This adds back the code. We'll codegen out of bounds i8 shifts to effectively (amount & 0x1f). The 0x1f is a strange quirk of x86 that shift amounts are always masked to 5-bits(except 64-bits). So if the masked value is still out bounds the result will be 0.
Fixes PR36731.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327540
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Fangrui Song [Wed, 14 Mar 2018 17:47:07 +0000 (17:47 +0000)]
Fix LLVM IR check lines in utils/update_cc_test_checks.py
Reviewers: arichardson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327538
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Roman Lebedev [Wed, 14 Mar 2018 17:31:08 +0000 (17:31 +0000)]
[InstSimplify] [NFC] Add tests for peeking through unsigned FP casts for sign compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
Looking at the IR pattern in question, as per [[ https://github.com/rutgers-apl/alive-nj | alive-nj ]], for all the type combinations i checked
(input: `i16`, `i32`, `i64`; intermediate: `half`/`i16`, `float`/`i32`, `double`/`i64`)
for the following `icmp` comparisons the `uitofp`+`bitcast`+`icmp` can be evaluated to a boolean:
* `slt 0`
* `sgt -1`
I did not check vectors, but i'm guessing it's the same there.
{
F5889242}
Thus all these cases are in the testcase (along with the vector variant with additional `undef` element in the middle).
There are no negative patterns here (unless alive-nj lied/is broken), all of these should be optimized.
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327535
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Roman Lebedev [Wed, 14 Mar 2018 17:31:03 +0000 (17:31 +0000)]
[InstCombine] [NFC] Add tests for peeking through unsigned FP casts for zero-equality compares (PR36682)
Summary:
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
Looking at the IR pattern in question, as per [[ https://github.com/rutgers-apl/alive-nj | alive-nj ]], for all the type combinations i checked
(input: `i16`, `i32`, `i64`; intermediate: `half`/`i16`, `float`/`i32`, `double`/`i64`)
for the following `icmp` comparisons the `uitofp`+`bitcast` can be dropped:
* `eq 0`
* `ne 0`
I did not check vectors, but i'm guessing it's the same there.
{
F5889189}
Thus all these cases are in the testcase (along with the vector variant with additional `undef` element in the middle).
There are no negative patterns here (unless alive-nj lied/is broken), all of these should be optimized.
Generated with
{
F5889196}
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327534
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Francis Visoiu Mistrih [Wed, 14 Mar 2018 17:10:58 +0000 (17:10 +0000)]
[AArch64] Keep track of MIFlags in the LoadStoreOptimizer
Merging:
* $x26, $x25 = frame-setup LDPXi $sp, 0
* $sp = frame-destroy ADDXri $sp, 64, 0
into an LDPXpost should preserve the flags from both instructions as
following:
* frame-setup frame-destroy LDPXpost
Differential Revision: https://reviews.llvm.org/D44446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327533
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Craig Topper [Wed, 14 Mar 2018 16:55:15 +0000 (16:55 +0000)]
[X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demanded bits if it helps created an and mask that can be matched as a zero extend.
I had to modify the bswap recognition to allow unshrunk masks to make this work.
Fixes PR36689.
Differential Revision: https://reviews.llvm.org/D44442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327530
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Nicholas Wilson [Wed, 14 Mar 2018 15:58:03 +0000 (15:58 +0000)]
[WebAssembly] Add DenseMap traits and operator== for Wasm type structs
Differential Revision: https://reviews.llvm.org/D44303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327526
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Simon Pilgrim [Wed, 14 Mar 2018 15:47:08 +0000 (15:47 +0000)]
[X86][AVX] Use WriteFShuffleLd for broadcast reg-mem instructions
They shouldn't be treated as pure loads.
Found while investigating D44428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327524
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Nicholas Wilson [Wed, 14 Mar 2018 15:44:45 +0000 (15:44 +0000)]
[WebAssembly] Identify COMDATs by index rather than string. NFC
This will enable an optimisation in LLD.
Differential Revision: https://reviews.llvm.org/D44343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327522
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Arnold Schwaighofer [Wed, 14 Mar 2018 15:44:07 +0000 (15:44 +0000)]
SjLjEHPrepare: Don't reg-to-mem swifterror values
swifterror llvm values model the swifterror register as memory at the
LLVM IR level. ISel will perform adhoc mem-to-reg on them. swifterror
values are constraint in how they can be used. Spilling them to memory
is not allowed.
SjLjEHPrepare tried to lower swifterror values to memory which is
unecessary since the back-end will spill and reload the register as
neccessary (as long as clobbering calls are marked as such which is the
case here) and further leads to invalid IR because swifterror values
can't be stored to memory.
rdar://
38164004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327521
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Alexander Ivchenko [Wed, 14 Mar 2018 15:41:11 +0000 (15:41 +0000)]
[GlobalIsel][X86] Support for G_SDIV instruction
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327520
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Sanjay Patel [Wed, 14 Mar 2018 15:28:48 +0000 (15:28 +0000)]
[CodeGen] allow printing of zero latency in sched comments
I don't know how to expose this in a test. There are ARM / AArch64
sched classes that include zero latency instructions, but I'm not
seeing sched info printed for those targets. X86 will almost
certainly have these soon (see PR36671), but no model has
'let Latency = 0' currently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327518
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Andrea Di Biagio [Wed, 14 Mar 2018 15:19:47 +0000 (15:19 +0000)]
[llvm-mca] Remove unused variable from InstrBuilder.cpp. NFC
This was causing a buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327517
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Andrea Di Biagio [Wed, 14 Mar 2018 14:57:23 +0000 (14:57 +0000)]
[llvm-mca] Move the logic that updates the register files from InstrBuilder to DispatchUnit. NFCI
Before this patch, the register file was always updated at instruction creation
time. That means, new read-after-write dependencies, and new temporary registers
were allocated at instruction creation time.
This patch refactors the code in InstrBuilder, and move all the logic that
updates the register file into the dispatch unit. We only want to update the
register file when instructions are effectively dispatched (not before).
This refactoring also helps removing a bad dependency between the InstrBuilder
and the DispatchUnit.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327514
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Petar Jovanovic [Wed, 14 Mar 2018 14:13:31 +0000 (14:13 +0000)]
[mips] Add support for CRC ASE
This includes
Instructions: crc32b, crc32h, crc32w, crc32d,
crc32cb, crc32ch, crc32cw, crc32cd
Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc
Attribute: crc
.MIPS.abiflags: CRC (0x8000)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327511
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Simon Pilgrim [Wed, 14 Mar 2018 14:05:19 +0000 (14:05 +0000)]
[X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costs
Account for ymm double pumping and add proper pshufb/permutevar support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327510
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Teresa Johnson [Wed, 14 Mar 2018 14:00:57 +0000 (14:00 +0000)]
[LTO/gold] Fix workaround for old plugin-api.h in --wrap support
The workaround for older plugin-api.h in r327506 unfortunately
used another union member that is also fairly new and not available
in the plugin-api.h on some of the bots, leading to:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/9121/steps/build-stage2-LLVMgold.so/logs/stdio
Change to use a different member that we will definitely have (as it
is used elsewhere in gold-plugin.cpp already).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327509
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Teresa Johnson [Wed, 14 Mar 2018 13:26:18 +0000 (13:26 +0000)]
[LTO/gold] Support --wrap
Summary:
(Restores r327459 with handling for old plugin-api.h)
Utilize new gold plugin api interface for obtaining --wrap option
arguments, and LTO API handling (added for --wrap support in lld LTO),
to mark symbols so that LTO does not optimize them inappropriately.
Note the test cases will be in a new gold test subdirectory that
is dependent on the next release of gold which will contain the new
interfaces.
Reviewers: pcc, tmsriram
Subscribers: mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D44235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327506
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Simon Pilgrim [Wed, 14 Mar 2018 13:22:56 +0000 (13:22 +0000)]
[X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instructions
They shouldn't be treated as pure loads.
Found while investigating D44428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327505
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Martin Storsjo [Wed, 14 Mar 2018 13:09:10 +0000 (13:09 +0000)]
[AArch64] Don't produce R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
Support for this relocation is missing in both LLD and GNU binutils
at the moment.
This reverts the ELF parts of SVN r327316.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327503
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Simon Pilgrim [Wed, 14 Mar 2018 12:04:51 +0000 (12:04 +0000)]
Fix 'not all control paths return a value' MSVC warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327502
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Pavel Labath [Wed, 14 Mar 2018 11:31:17 +0000 (11:31 +0000)]
Fix msvc compiler error in r327498
msvc reports an "illegal indirection" error here. Attempt to appease it
with a different initialization syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327500
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Alexander Ivchenko [Wed, 14 Mar 2018 11:23:57 +0000 (11:23 +0000)]
[GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327499
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Pavel Labath [Wed, 14 Mar 2018 11:14:43 +0000 (11:14 +0000)]
Explicitly initialize dwarf::FormParams in DIEInteger::SizeOf
This could end up inititialized if someone called the function with a
null AsmPrinter. Right now this only happens in DIEHash unit tests,
presumably because it was hard to create an AsmPrinter in the context of
unit tests. This only worked before r327486 because those tests did not
use any dwarf forms whose size actually depended on the dwarf version
(otherwise, they would have crashed due to null dereference).
I fix the uninitialized error, by explicitly initializing FormParams to
an invalid value, which will cause getFixedFormByteSize to return None
if called with a form with version-dependent size. A more principled
solution might be to fix the DIEHash tests to always pass in a valid
AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327498
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Nicolai Haehnle [Wed, 14 Mar 2018 11:01:01 +0000 (11:01 +0000)]
TableGen: Explicitly forbid some nestings of class, multiclass, and foreach
These previously all failed one way or another, but now we produce a more
helpful error message.
Change-Id: I8ffd2e87c8e35a5134c3be289e0a1fecaa2bb8ca
Differential revision: https://reviews.llvm.org/D44115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327497
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:57 +0000 (11:00 +0000)]
TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons
Change-Id: I8e2ece677268972d578a787467f7ef52a1f33a71
Differential revision: https://reviews.llvm.org/D44114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327496
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:48 +0000 (11:00 +0000)]
TableGen: Allow dag operators to be resolved late
Change-Id: I51bb80fd5c48c8ac441ab11e43d43c1b91b4b590
Differential revision: https://reviews.llvm.org/D44113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327495
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:43 +0000 (11:00 +0000)]
TableGen: Type-check BinOps
Additionally, allow more than two operands to !con, !add, !and, !or
in the same way as is already allowed for !listconcat and !strconcat.
Change-Id: I9659411f554201b90cd8ed7c7e004d381a66fa93
Differential revision: https://reviews.llvm.org/D44112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327494
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:33 +0000 (11:00 +0000)]
TableGen: Allow ? in lists
This makes using !dag more convenient in some cases.
Change-Id: I0a8c35e15ccd1ecec778fd1c8d64eee38d74517c
Differential revision: https://reviews.llvm.org/D44111
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327493
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Nicolai Haehnle [Wed, 14 Mar 2018 11:00:26 +0000 (11:00 +0000)]
TableGen: Add !dag function for construction
This allows constructing DAG nodes with programmatically determined
names, and can simplify constructing DAG nodes in other cases as
well.
Also, add documentation and some very simple tests for the already
existing !con.
Change-Id: Ida61cd82e99752548d7109ce8da34d29da56a5f7
Differential revision: https://reviews.llvm.org/D44110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327492
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Alexander Timofeev [Wed, 14 Mar 2018 09:48:51 +0000 (09:48 +0000)]
[AMDGPU] Fix for DAGCombiner infinite loop in OCLtst
Differential revision: https://reviews.llvm.org/D44417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327488
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Pavel Labath [Wed, 14 Mar 2018 09:39:54 +0000 (09:39 +0000)]
DWARF: Unify form size handling code
Summary:
This patch replaces the two switches which are deducing the size of
various forms with a single implementation. I have put the new
implementation into BinaryFormat, to avoid introducing dependencies
between the two independent libraries (DebugInfo and CodeGen) that need
this functionality.
Reviewers: aprantl, JDevlieghere, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327486
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Jonas Devlieghere [Wed, 14 Mar 2018 09:34:54 +0000 (09:34 +0000)]
[dsymutil] Print architecture in warning
Make the architecture part of the warning in the DebugMapParser. This
makes things consistent with the Apple's internal version of dsymutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327485
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Pavel Labath [Wed, 14 Mar 2018 09:28:38 +0000 (09:28 +0000)]
Export LLVM_DYLIB_COMPONENTS in LLVMConfig.cmake
Summary:
This is needed so that external projects (e.g. a standalone build of
lldb) can link to the LLVM shared library via the USE_SHARED argument of
llvm_config. Without this, llvm_config would add LLVM to the link list,
but then also add the constituent static libraries, resulting in
multiply defined symbols.
Reviewers: beanz, mgorny
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327484
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Alexander Ivchenko [Wed, 14 Mar 2018 09:11:23 +0000 (09:11 +0000)]
[GlobalIsel][X86] Support for G_ZEXT instruction
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327482
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Robert Widmann [Wed, 14 Mar 2018 06:45:51 +0000 (06:45 +0000)]
[LLVM-C] Redo unnamed_address attribute bindings
Summary:
The old bindings should have used an enum instead of a boolean. This
deprecates LLVMHasUnnamedAddr and LLVMSetUnnamedAddr , replacing them
with LLVMGetUnnamedAddress and LLVMSetUnnamedAddress respectively that do.
Though it is unlikely LLVM will gain more supported global value linker
hints, the new API can scale to accommodate this.
Reviewers: deadalnix, whitequark
Reviewed By: whitequark
Subscribers: llvm-commits, harlanhaskins
Differential Revision: https://reviews.llvm.org/D43448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327479
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Lang Hames [Wed, 14 Mar 2018 06:39:49 +0000 (06:39 +0000)]
[RuntimeDyld] Silence a compiler error.
This should fix the error at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327478
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Lang Hames [Wed, 14 Mar 2018 06:25:08 +0000 (06:25 +0000)]
[ORC] Fix a data race in the lookup function.
The Error locals need to be protected by a mutex. (This could be fixed by
having the promises / futures contain Expected and Error values, but
MSVC's future implementation does not support this yet).
Hopefully this will fix some of the errors seen on the builders due to
r327474.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327477
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Lang Hames [Wed, 14 Mar 2018 06:25:07 +0000 (06:25 +0000)]
[ExecutionEngine] Add a getSymbolTable method to RuntimeDyld.
This can be used to extract the symbol table from a RuntimeDyld instance prior
to disposing of it.
This patch also updates RTDyldObjectLinkingLayer to use the new method, rather
than requesting symbols one at a time via getSymbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327476
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Lang Hames [Wed, 14 Mar 2018 05:23:56 +0000 (05:23 +0000)]
[ORC] Silence a compiler error.
This should fix the builder error at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327475
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Lang Hames [Wed, 14 Mar 2018 04:18:04 +0000 (04:18 +0000)]
[ORC] Add a 'lookup' convenience function for finding symbols in a list of VSOs.
The lookup function takes a list of VSOs, a set of symbol names (or just one
symbol name) and a materialization function object. It returns an
Expected<SymbolMap> (if given a set of names) or an Expected<JITEvaluatedSymbol>
(if given just one name). The lookup method constructs an
AsynchronousSymbolQuery for the given names, applies that query to each VSO in
the list in turn, and then blocks waiting for the query to complete. If
threading is enabled then the materialization function object can be used to
execute the materialization on different threads. If threading is disabled the
MaterializeOnCurrentThread utility must be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327474
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Eugene Zemtsov [Wed, 14 Mar 2018 02:10:07 +0000 (02:10 +0000)]
Disable test debuglineinfo-path on powerpc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327472
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Eugene Zemtsov [Wed, 14 Mar 2018 01:07:18 +0000 (01:07 +0000)]
grep for global functions only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327469
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Matt Arsenault [Wed, 14 Mar 2018 00:36:23 +0000 (00:36 +0000)]
TargetMachine: Add address space to getPointerSize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327467
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Eugene Zemtsov [Wed, 14 Mar 2018 00:15:16 +0000 (00:15 +0000)]
Add extra output/check to debug clang-ppc64be-linux test failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327466
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Teresa Johnson [Tue, 13 Mar 2018 23:55:34 +0000 (23:55 +0000)]
Revert "[LTO/gold] Support --wrap"
This reverts commit r327459. The new gold plugin interface is not
available with older gold installations, leading to compile failures:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/9109/steps/build-stage2-LLVMgold.so/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327465
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Craig Topper [Tue, 13 Mar 2018 23:31:48 +0000 (23:31 +0000)]
[X86] Re-generate test to get proper capitalization of its CHECK lines. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327462
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Aditya Nandakumar [Tue, 13 Mar 2018 23:21:13 +0000 (23:21 +0000)]
[GISel]: Fix incorrect type used in Pattern Match for ICst
getConstantVRegVal() returns int64_t but we use uint64_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327461
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Teresa Johnson [Tue, 13 Mar 2018 23:06:19 +0000 (23:06 +0000)]
[LTO/gold] Support --wrap
Summary:
Utilize new gold plugin api interface for obtaining --wrap option
arguments, and LTO API handling (added for --wrap support in lld LTO),
to mark symbols so that LTO does not optimize them inappropriately.
Note the test cases will be in a new gold test subdirectory that
is dependent on the next release of gold which will contain the new
interfaces.
Reviewers: pcc, tmsriram
Subscribers: mehdi_amini, llvm-commits, inglorion
Differential Revision: https://reviews.llvm.org/D44235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327459
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Eugene Zemtsov [Tue, 13 Mar 2018 22:48:39 +0000 (22:48 +0000)]
Disable optimizations in debuglineinfo-path test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327458
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Craig Topper [Tue, 13 Mar 2018 22:36:07 +0000 (22:36 +0000)]
[X86] Simplify the LowerAVXCONCAT_VECTORS code a little by creating a single path for insert_subvector handling.
We now only create recursive concats if we have more than two non-zero values. This keeps our subvector broadcast DAG combine functioning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327457
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Craig Topper [Tue, 13 Mar 2018 22:05:25 +0000 (22:05 +0000)]
[X86] Rewrite LowerAVXCONCAT_VECTORS similar to how we handle vXi1 concats.
This better able to detect undef and zeros pieces in the concat. Or cases when only one subvector is non-zero. This allows us to avoid silly things like double inserts into progressively larger undefs.
This still builds 512 bit concats of 128 bits by building up through 256 bits first. But I don't know if that's best.
We probably want to merge this with the vXi1 concat code since they are very similar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327454
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Zachary Turner [Tue, 13 Mar 2018 21:18:00 +0000 (21:18 +0000)]
Disable PDB injected sources test temporarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327451
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Hiroshi Yamauchi [Tue, 13 Mar 2018 21:13:18 +0000 (21:13 +0000)]
Simplify more cases of logical ops of masked icmps.
Summary:
For example,
((X & 255) != 0) && ((X & 15) == 8) -> ((X & 15) == 8).
((X & 7) != 0) && ((X & 15) == 8) -> false.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327450
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Eugene Zemtsov [Tue, 13 Mar 2018 21:10:15 +0000 (21:10 +0000)]
Remove explicit triple and data layout from the test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327449
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Craig Topper [Tue, 13 Mar 2018 20:36:28 +0000 (20:36 +0000)]
[DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with BUILD_VECTORS between LegalizeVectorOps and LegalizeDAG.
BUILD_VECTORs aren't themselves legalized until LegalizeDAG so we should still be able to create an "illegal" one before that. This helps combine with BUILD_VECTORS that are introduced during LegalizeVectorOps due to unrolling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327446
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Zachary Turner [Tue, 13 Mar 2018 20:16:37 +0000 (20:16 +0000)]
Update modulemap to exclude new DIA headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327444
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Eugene Zemtsov [Tue, 13 Mar 2018 20:06:33 +0000 (20:06 +0000)]
Fix debuglineinfo-path.ll
This fix is based on an assumption that some build bots are missing 'echo
-n'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327443
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Francis Visoiu Mistrih [Tue, 13 Mar 2018 19:53:16 +0000 (19:53 +0000)]
[MIR] Allow frame-setup and frame-destroy on the same instruction
Nothing prevents us from having both frame-setup and frame-destroy on
the same instruction.
When merging:
* frame-setup OPCODE1
* frame-destroy OPCODE2
into
* frame-setup frame-destroy OPCODE3
we want to be able to print and parse both flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327442
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Eugene Zemtsov [Tue, 13 Mar 2018 19:48:31 +0000 (19:48 +0000)]
Temporary disable debuglineinfo-path.ll to fix build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327441
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Anna Thomas [Tue, 13 Mar 2018 19:38:45 +0000 (19:38 +0000)]
Test Commit NFC. Updated comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327436
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Sanjay Patel [Tue, 13 Mar 2018 19:20:01 +0000 (19:20 +0000)]
[x86] add test for WriteZero sched class instructions; NFC
Nops should have zero latency because there is no result.
Idioms like 'xorps xmm0, xmm0' may have zero latency because
they are handled without using an execution unit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327435
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Haicheng Wu [Tue, 13 Mar 2018 18:44:19 +0000 (18:44 +0000)]
[SLP] clean some formats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327433
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Brian M. Rzycki [Tue, 13 Mar 2018 18:14:10 +0000 (18:14 +0000)]
[LazyValueInfo] PR33357 prevent infinite recursion on BinaryOperator
Summary:
It is possible for LVI to encounter instructions that are not in valid
SSA form and reference themselves. One example is the following:
%tmp4 = and i1 %tmp4, undef
Before this patch LVI would recurse until running out of stack memory
and crashed. This patch marks these self-referential instructions as
Overdefined and aborts analysis on the instruction.
Fixes https://bugs.llvm.org/show_bug.cgi?id=33357
Reviewers: craig.topper, anna, efriedma, dberlin, sebpop, kuhar
Reviewed by: dberlin
Subscribers: uabelho, spatel, a.elovikov, fhahn, eli.friedman, mzolotukhin, spop, evandro, davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D34135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327432
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Zachary Turner [Tue, 13 Mar 2018 17:58:28 +0000 (17:58 +0000)]
Implement pure virtual method to fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327431
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Eugene Zemtsov [Tue, 13 Mar 2018 17:54:29 +0000 (17:54 +0000)]
Handle mixed-OS paths in DWARF reader
Make sure that DWARF line information generated by Windows can be properly read by Posix OS and vice versa.
Differential Revision: https://reviews.llvm.org/D44290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327430
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Sanjay Patel [Tue, 13 Mar 2018 17:50:27 +0000 (17:50 +0000)]
[MC] fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327429
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Zachary Turner [Tue, 13 Mar 2018 17:46:06 +0000 (17:46 +0000)]
[PDB] Support dumping injected sources via the DIA reader.
Injected sources are basically a way to add actual source file content
to your PDB. Presumably you could use this for shipping your source code
with your debug information, but in practice I can only find this being
used for embedding natvis files inside of PDBs.
In order to effectively test LLVM's natvis file injection, we need a way
to dump the injected sources of a PDB in a way that is authoritative
(i.e. based on Microsoft's understanding of the PDB format, and not
LLVM's). To this end, I've added support for dumping injected sources
via DIA. I made a PDB file that used the /natvis option to generate a
test case.
Differential Revision: https://reviews.llvm.org/D44405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327428
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Simon Dardis [Tue, 13 Mar 2018 17:31:11 +0000 (17:31 +0000)]
Revert "[mips] Guard traps for microMIPS correctly"
This appears to have broken the expensive checks bot in
a strange fashion. Reverting until I can investigate.
This reverts r327409.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327427
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Andrea Di Biagio [Tue, 13 Mar 2018 17:24:32 +0000 (17:24 +0000)]
[llvm-mca] Remove the logic that computes the reciprocal throughput, and make the SummaryView independent from the Backend. NFCI
Since r327420, the tool can query the MCSchedModel interface to obtain the
reciprocal throughput information.
As a consequence, method `ResourceManager::getRThroughput`, and
method `Backend::getRThroughput` are no longer needed.
This patch simplifies the code by removing the custom RThroughput computation.
This patch also refactors class SummaryView by removing the dependency with
the Backend object.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327425
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Simon Pilgrim [Tue, 13 Mar 2018 17:17:15 +0000 (17:17 +0000)]
[DAGCombine] visitREM - Don't assume that one divrem isn't driving another
Under some circumstances the divrems won't have been combined together before getting to this code.
So replace the assertion with a if() guard to not expand to X-((X/C)*C) to give the other combine chance to happen.
Reduced from OSS-Fuzz #6883
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327424
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Azharuddin Mohammed [Tue, 13 Mar 2018 17:04:33 +0000 (17:04 +0000)]
Build system changes for RISCV
Summary: Build system changes for RISCV. Makes it possible to build just the RISCV target alone.
Reviewers: asb, apazos, mgrang, beanz
Reviewed By: asb
Subscribers: mgorny, kito-cheng, shiva0217, llvm-commits
Differential Revision: https://reviews.llvm.org/D44153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327423
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Brian Homerding [Tue, 13 Mar 2018 16:37:59 +0000 (16:37 +0000)]
[lit] - Allow 1 test to report multiple micro-test results to provide support for microbenchmarks.
Summary:
These changes are to allow to a Result object to have nested Result objects in
order to support microbenchmarks. Currently lit is restricted to reporting one
result object for one test, this change provides support tests that want to
report individual timings for individual kernels.
This revision is the result of the discussions in
https://reviews.llvm.org/D32272#794759,
https://reviews.llvm.org/D37421#
f8003b27 and https://reviews.llvm.org/D38496.
It is a separation of the changes purposed in https://reviews.llvm.org/D40077.
This change will enable adding LCALS (Livermore Compiler Analysis Loop Suite)
collection of loop kernels to the llvm test suite using the google benchmark
library (https://reviews.llvm.org/D43319) with tracking of individual kernel
timings.
Previously microbenchmarks had been handled by using macros to section groups
of microbenchmarks together and build many executables while still getting a
grouped timing (MultiSource/TSVC). Recently the google benchmark library was
added to the test suite and utilized with a litsupport plugin. However the
limitation of 1 test 1 result limited its use to passing a runtime option to
run only 1 microbenchmark with several hand written tests
(MicroBenchmarks/XRay). This runs the same executable many times with different
hand-written tests. I will update the litsupport plugin to utilize the new
functionality (https://reviews.llvm.org/D43316).
These changes allow lit to report micro test results if desired in order to get
many precise timing results from 1 run of 1 test executable.
Reviewers: MatzeB, hfinkel, rengolin, delcypher
Differential Revision: https://reviews.llvm.org/D43314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327422
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Daniel Neilson [Tue, 13 Mar 2018 16:31:19 +0000 (16:31 +0000)]
[SelectionDAGBuilder] Replace deprecated calls to MemoryIntrinsic::getAlignment() (NFCI)
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
SelectionDAGBuilder to cease using the old getAlignment() API of MemoryIntrinsic in favour of getting
source & dest specific alignments through the new API.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816, rL327398 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327421
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Andrea Di Biagio [Tue, 13 Mar 2018 16:28:55 +0000 (16:28 +0000)]
[MC] Move the reciprocal throughput computation from TargetSchedModel to MCSchedModel.
The goal is to make the reciprocal throughput computation accessible through the
MCSchedModel interface. This is particularly important for llvm-mca because it
can only query the MCSchedModel interface.
No functional change intended.
Differential Revision: https://reviews.llvm.org/D44392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327420
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Craig Topper [Tue, 13 Mar 2018 16:23:27 +0000 (16:23 +0000)]
[X86] Remove SplitBinaryOpsAndApply and use SplitOpsAndApply by adding curly braces around the ops.
Summary: Unless you were intentionally avoiding this syntax? I saw you mentioned makeArrayRef in your commit that added SplitOpsAndApply.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327418
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Andrea Di Biagio [Tue, 13 Mar 2018 15:59:59 +0000 (15:59 +0000)]
[llvm-mca] Simplify code that computes the latency of an instruction in
InstrBuilder. NFCI
This was possible because of r327406, which added function`computeInstrLatency`
to MCSchedModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327415
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Brock Wyma [Tue, 13 Mar 2018 15:56:20 +0000 (15:56 +0000)]
Revert r327397 [CodeView] Omit forward references for unnamed structs and ...
This reverts commit r327397 to investigate a buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327414
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Zaara Syeda [Tue, 13 Mar 2018 15:49:05 +0000 (15:49 +0000)]
test commit: fix formatting of a comment
This is a simple change to do the test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327412
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Jonas Devlieghere [Tue, 13 Mar 2018 15:47:38 +0000 (15:47 +0000)]
[dsymutil] Unify error handling outside DwarfLinker.
This is a follow-up to r327137 where we unified error handling for the
DwarfLinker. This replaces calls to errs() and outs() with the
appropriate ostream wrapper everywhere in dsymutil.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327411
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Simon Dardis [Tue, 13 Mar 2018 15:46:58 +0000 (15:46 +0000)]
[mips] Guard traps for microMIPS correctly
This is part of fixing the instruction predicates for MIPS.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D44212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327409
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Rafael Espindola [Tue, 13 Mar 2018 15:24:51 +0000 (15:24 +0000)]
[ThinLTO] Clear dllimport when setting dso_local.
This is PR36686.
If a user of a library is LTOed with that library we take the
opportunity to set dso_local, but we don't clear dllimport, which
creates an invalid IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327408
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Simon Pilgrim [Tue, 13 Mar 2018 15:22:24 +0000 (15:22 +0000)]
[X86][Btver2] Split i8/i16/i32/i64 div/idiv costs
We were assuming a mixture of 32/64 division costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327407
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Andrea Di Biagio [Tue, 13 Mar 2018 15:22:13 +0000 (15:22 +0000)]
[MC] Move the instruction latency computation from TargetSchedModel to MCSchedModel.
The goal is to make the latency information accessible through the MCSchedModel
interface. This is particularly important for tools like llvm-mca that only have
access to the MCSchedModel API.
This partially fixes PR36676.
No functional change intended.
Differential Revision: https://reviews.llvm.org/D44383
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327406
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Sanjay Patel [Tue, 13 Mar 2018 14:46:32 +0000 (14:46 +0000)]
[InstCombine] fix fmul reassociation to avoid creating an extra fdiv
This was supposed to be an NFC refactoring that will eventually allow
eliminating the isFast() predicate, but there's a rare possibility
that we would pessimize the code as shown in the test case because
we failed to check 'hasOneUse()' properly. This version also removes
an inefficiency of the old code; we would look for:
(X * C) * C1 --> X * (C * C1)
...but that pattern is always handled by
SimplifyAssociativeOrCommutative().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327404
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Simon Dardis [Tue, 13 Mar 2018 14:39:44 +0000 (14:39 +0000)]
[mips] Fix the definitions of the EVA instructions
Correct their availability to their respective ISAs.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D44209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327403
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Jonas Devlieghere [Tue, 13 Mar 2018 14:28:07 +0000 (14:28 +0000)]
[dsymutil] Remove old error/warn functions. NFC.
This removes the old error and warn functions that were still present in
the dwarf linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327400
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Jonas Devlieghere [Tue, 13 Mar 2018 14:27:15 +0000 (14:27 +0000)]
[dsymutil] Perform analyzeContextInfo and CloneDIEs in parallel
This patch makes dsymutil perform analyzeContextInfo and CloneDIEs in
parallel. For the same object file, there is a dependency between the
two. However, we can do analyzeContextInfo for the next object file
while cloning DIEs for the current. This is exactly the approach taken
in this patch.
For WebCore, this leads to a performance improvement of 29% and for
clang we see similar results with at 32% improvement.
A big thanks to Pete Cooper who came up with the original idea and
the PoC.
Differential revision: https://reviews.llvm.org/D43945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327399
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Daniel Neilson [Tue, 13 Mar 2018 14:25:33 +0000 (14:25 +0000)]
[SROA] Take advantage of separate alignments for memcpy source and destination
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
SROA pass to cease using the old getAlignment() & setAlignment() APIs of MemoryIntrinsic in
favour of getting source & dest specific alignments through the new API. This allows us
to enhance visitMemTransferInst to be more aggressive setting the alignment in memcpy
calls that it creates, as well as to only change the alignment of a memcpy/memmove
argument that it replaces.
Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.
Reference
http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20151109/312083.html
Reviewers: chandlerc, bollu, efriedma
Reviewed By: efriedma
Subscribers: efriedma, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D42974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327398
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Brock Wyma [Tue, 13 Mar 2018 14:14:16 +0000 (14:14 +0000)]
[CodeView] Omit forward references for unnamed structs and unions
Codeview references to unnamed structs and unions are expected to refer to the
complete type definition instead of a forward reference so Visual Studio can
resolve the type properly.
Differential Revision: https://reviews.llvm.org/D32498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327397
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Andrea Di Biagio [Tue, 13 Mar 2018 13:58:02 +0000 (13:58 +0000)]
[llvm-mca] Use a const ArrayRef in a few places. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327396
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Haicheng Wu [Tue, 13 Mar 2018 13:52:47 +0000 (13:52 +0000)]
[TTI] Fix a typo in the comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327395
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Clement Courbet [Tue, 13 Mar 2018 13:44:18 +0000 (13:44 +0000)]
[llvm-mca] Fix unused variable warning in opt mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327394
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Clement Courbet [Tue, 13 Mar 2018 13:11:01 +0000 (13:11 +0000)]
[llvm-mca] Refactor event listeners to make the backend agnostic to event types.
Summary: This is a first step towards making the pipeline configurable.
Subscribers: llvm-commits, andreadb
Differential Revision: https://reviews.llvm.org/D44309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327389
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Simon Dardis [Tue, 13 Mar 2018 12:50:03 +0000 (12:50 +0000)]
[mips] Don't create nested CALLSEQ_START..CALLSEQ_END nodes.
For the MIPS O32 ABI, the current call lowering logic naively lowers each
call, creating the reserved argument area to hold the argument spill areas for
$a0..$a3 and the outgoing parameter area if one is required at each call site.
In the case of a sufficently large byval argument, a call to memcpy is used
to write the start+16..end of the argument into the outgoing parameter area.
This is done within the CALLSEQ_START..CALLSEQ_END of the callee. The CALLSEQ
nodes are responsible for performing the necessary stack adjustments.
Since the O32/N32/N64 MIPS ABIs do not have a red-zone and writing below the
stack pointer and reading the values back is unpredictable, the call to memcpy
cannot be hoisted out of the callee's CALLSEQ nodes.
However, for the O32 ABI requires the reserved argument area for functions
which have parameters. The naive lowering of calls will then create nested
CALLSEQ sequences. For N32 and N64 these nodes are also created, but with
zero stack adjustments as those ABIs do not have a reserved argument area.
This patch addresses the correctness issue by recognizing the special case
of lowering a byval argument that uses memcpy. By recognizing that the
incoming chain already has a CALLSEQ_START node on it when calling memcpy,
the CALLSEQ nodes are not created. For the N32 and N64 ABIs, this is not an
issue, as no stack adjustment has to be performed.
For the O32 ABI, the correctness reasoning is different. In the case of a
sufficently large byval argument, registers a0..a3 are going to be used for
the callee's arguments, mandating the creation of the reserved argument area.
The call to memcpy in the naive case will also create its own reserved
argument area. However, since the reserved argument area consists of undefined
values, both calls can use the same reserved argument area.
Reviewers: abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D44296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327388
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Simon Pilgrim [Tue, 13 Mar 2018 12:22:58 +0000 (12:22 +0000)]
[X86][SSE41] createVariablePermute v2X64 - PCMPEQQ can test for index 0/1 and select between them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327385
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Jonas Devlieghere [Tue, 13 Mar 2018 11:32:19 +0000 (11:32 +0000)]
[dsymutil] Unbreak non-Darwin bots.
BinaryHolder -> BinHolder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327384
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Jonas Devlieghere [Tue, 13 Mar 2018 10:52:49 +0000 (10:52 +0000)]
[dsymutil] Introduce LinkContext. NFC.
This patch introduces the LinkContext which is necessary to have
dsymutil perform analysis and cloning of DIEs in parallel. As requested
in D43945, I'm landing this as two separate commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327382
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Eugene Leviant [Tue, 13 Mar 2018 10:19:50 +0000 (10:19 +0000)]
[Evaluator] Evaluate load/store with bitcast
Differential revision: https://reviews.llvm.org/D43457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327381
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Jonas Paulsson [Tue, 13 Mar 2018 08:36:20 +0000 (08:36 +0000)]
[CodeGenPrepare] Respect endianness in splitMergedValStore.
splitMergedValStore will split a store into two if target prefers this, or if
-force-split-store is passed.
This patch adds the missing handling for endianness in this function along
with a test case.
Review: Eli Friedman
https://reviews.llvm.org/D44396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327375
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