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Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Restrict the MV search range based on MPEG2 encoding LEVEL
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
c05073b1f8764271ccf4fe1aa037f881dedd3818)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Rewrite inter-frame shader for MPEG2 encoding on HSW to follow MPEG2 spec
Now the MPEG2/H264 uses the same mode/motion vector prediction shader. But
the MV search region of mpeg2 is different with that on H264, which causes
that the wrong mode/motion vector prediction is used for MPEG2.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
6842f08aa375b5942cee4b9d06421609c212895a)
Xiang, Haihao [Fri, 9 Aug 2013 05:52:16 +0000 (13:52 +0800)]
Convert 422H/422V/411P/444P into other formats for internal using
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
232ef48766c1f91a87a3d41f951fd2ac26dcf2ae)
Xiang, Haihao [Fri, 9 Aug 2013 05:40:10 +0000 (13:40 +0800)]
A separate batch buffer for video processing
It is easy to result in multithread issue if the rendering code
and video processing code share the same batch buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
ce0984814269e0923f44196e47f1c7cc2dddc55c)
Xiang, Haihao [Thu, 8 Aug 2013 02:01:50 +0000 (10:01 +0800)]
Use the right wight/height to initialize the internal buffers for MPEG-2 encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3ecbff585af918d96959ce791eec29be25360d91)
Xiang, Haihao [Thu, 8 Aug 2013 01:52:33 +0000 (09:52 +0800)]
Cleanup profile tracking in encoder
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
edd25a94e92b9cec23594dc978691506a1c8cfab)
Xiang, Haihao [Thu, 8 Aug 2013 01:35:30 +0000 (09:35 +0800)]
Rename the macros
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3ab97be8db1b8e55d0d5b95f577863416a87c6ff)
Zhao Halley [Thu, 25 Jul 2013 01:09:41 +0000 (09:09 +0800)]
Enable the Bay Trail platform.
This patch adds PCI IDs for Bay Trail (sometimes called Valley View).
As far as the video driver is concerned, it's very similar to
Ivybridge GT1 except VP8 decoding support.
(cherry picked from commit
b3afeef8092dc4eb7cb73fce672ddf7a55205f34)
Li Xiaowei [Thu, 18 Jul 2013 11:18:54 +0000 (19:18 +0800)]
VPP: remove needless functions and parameters in gpe pipeline
(cherry picked from commit
ab0546e76967e5e7c465569f90e192b560678d8c)
Xiang, Haihao [Tue, 23 Jul 2013 05:22:16 +0000 (13:22 +0800)]
Fixes valgrind warning
"Conditional jump or move depends on uninitialised value(s)"
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
cbd00deb6c5cad58ebd5e6ce5b89aaaded0f78a5)
Xiang, Haihao [Tue, 23 Jul 2013 05:14:48 +0000 (13:14 +0800)]
Release the private driver data when call vaTerminate()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c735d9e58dd49c9a92ad0042b5649a9d3fe7c2c4)
Xiang, Haihao [Tue, 23 Jul 2013 05:08:05 +0000 (13:08 +0800)]
VPP: check the filter when query the video filter capabilities
Return VA_STATUS_ERROR_UNSUPPORTED_FILTER if an unsupported filter
was supplied
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
428723853f88b4d5cac436f5fd62e6cc64a9e8e9)
Xiang, Haihao [Wed, 3 Jul 2013 02:31:17 +0000 (10:31 +0800)]
Insert a phantom slice for H.264 deocdong on SNB
If the first slice does't start at 0, a phantom slice is added
before the first slice.
This fixes the GPU hang issue mentioned in https://bugs.freedesktop.org/show_bug.cgi?id=63946
(not the original issue).
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: Krzysztof Kotlenga <pocek@users.sf.net>
(cherry picked from commit
11115e3f0427d056367c1c5946585e3f7cead662)
Xiang, Haihao [Wed, 10 Jul 2013 06:16:02 +0000 (14:16 +0800)]
Check the returned pointer from malloc() before using it
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
1caf179b1425b13cacaa421c688c6df8369668c6)
Xiang, Haihao [Mon, 1 Jul 2013 04:47:28 +0000 (12:47 +0800)]
Add the dependency to the ring supported by the underlying OS for VPP filters
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a532539cbc7048f5c01b64dfe239f1570123c959)
Xiang, Haihao [Mon, 1 Jul 2013 02:40:19 +0000 (10:40 +0800)]
Check whether VEBOX is supported by the underlying OS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c586c80d29d8860011d95e78d1609ff3683f3cc4)
Xiang, Haihao [Fri, 28 Jun 2013 06:03:34 +0000 (14:03 +0800)]
Won't build the shaders for Sharpening on HSW
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=66258
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Thu, 27 Jun 2013 09:26:34 +0000 (11:26 +0200)]
build: fix make dist for packaging.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 05:14:44 +0000 (13:14 +0800)]
Udate the micro version
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 05:10:15 +0000 (13:10 +0800)]
Bump version for development
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 02:18:25 +0000 (10:18 +0800)]
Intel driver 1.2.0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 02:16:07 +0000 (10:16 +0800)]
NEWS: updates
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 25 Jun 2013 07:41:27 +0000 (15:41 +0800)]
Update the dependency on libdrm
libdrm 2.4.45 is required to support VEBOX on HSW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 25 Jun 2013 07:56:05 +0000 (15:56 +0800)]
Revert "Make it built against the current upstream libdrm"
The upstream libdrm now has supported VEBOX, hence remove the
definition of I915_EXEC_VEBOX
This reverts commit
6fdd5a24a5099d45a01da5a9f1337d26749898bb.
Xiang, Haihao [Fri, 21 Jun 2013 04:21:58 +0000 (12:21 +0800)]
Silence the warning
CC i965_drv_video_la-gen75_vpp_vebox.lo
gen75_vpp_vebox.c: In function ‘hsw_veb_dndi_iecp_command’:
gen75_vpp_vebox.c:697:5: warning: suggest parentheses around arithmetic in operand of ‘|’
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 21 Jun 2013 00:52:41 +0000 (08:52 +0800)]
VPP: Filter parameters are stored in system memory
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 17 Jun 2013 07:06:11 +0000 (15:06 +0800)]
Fix copy&paste error
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 06:54:53 +0000 (14:54 +0800)]
VEBOX: output 2 frames for advanced DI
Both current frame and previous frame are outputted
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 06:40:26 +0000 (14:40 +0800)]
VEBOX: motion adaptive DI on HSW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 03:40:42 +0000 (11:40 +0800)]
VEBOX: update internal surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 12:31:11 +0000 (20:31 +0800)]
VEBOX: track the frame sequence
Preparation work for advanced DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 12:50:58 +0000 (20:50 +0800)]
VEBOX: clean up
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 08:39:13 +0000 (16:39 +0800)]
VEBOX: Update VEBOX_STATE for Bob DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 07:55:27 +0000 (15:55 +0800)]
VEBOX: Update DNDI table on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 03:31:36 +0000 (11:31 +0800)]
Update the supported render target format and pixel format
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 7 Jun 2013 08:56:45 +0000 (16:56 +0800)]
Update the implementation of vaQueryVideoProcFilterCaps()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 30 May 2013 08:41:09 +0000 (16:41 +0800)]
Update the implementation of vaQueryVideoProcFilters()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 30 May 2013 06:52:15 +0000 (14:52 +0800)]
VAProcFilterNone isn't a actual filter
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 7 Jun 2013 01:47:22 +0000 (09:47 +0800)]
Return supported external memory types in vaQuerySurfaceAttributes()
Return the number of elements actually filled in output as well.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 6 Jun 2013 08:51:02 +0000 (16:51 +0800)]
Add support for vaQuerySurfaceAttributes()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 6 Jun 2013 07:38:09 +0000 (15:38 +0800)]
Add support for VA_SURFACE_ATTRIB_MEM_TYPE_KERNEL_DRM and VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li Xiaowei [Wed, 19 Jun 2013 18:07:48 +0000 (02:07 +0800)]
VEBOX: Fix image garbage at border when pro amp
Aligned width/height are required to be registered
to surface state, instead of original width/height
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Wed, 19 Jun 2013 17:33:01 +0000 (01:33 +0800)]
VEBOX: Fix endingX setting for dndi/iecp command
The endingX need be aligned to 64 and subtract 1
before setting to VEBOX command.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Sun, 9 Jun 2013 15:26:15 +0000 (23:26 +0800)]
VEBOX: Turn off CSC function in VEBOX pipeline
all surface format conversion process and CSC will
be done through shader, this will simplify the pipeline
data flow especially for multiple filters case.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Sun, 9 Jun 2013 07:43:08 +0000 (15:43 +0800)]
More reserved PCI IDs for Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a9c66609b289c815b2bfc0385dc1f3bff6677125)
Xiang, Haihao [Sun, 9 Jun 2013 07:34:20 +0000 (15:34 +0800)]
Update max_wm_threads on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c31f6130793c68a83d1cb1116da60489d5e4a1d4)
Xiang, Haihao [Sun, 9 Jun 2013 07:29:15 +0000 (15:29 +0800)]
Fix Haswell GT3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3c9e778718cb4d24695a880afb45e32cdf43a434)
Xiang, Haihao [Mon, 27 May 2013 02:19:10 +0000 (10:19 +0800)]
A workaround for clearing a Y-tiled surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
9c698455fec340ced7dbf93cc5be004bb4a1eb22)
Xiang, Haihao [Wed, 22 May 2013 06:23:53 +0000 (14:23 +0800)]
version 1.2.0.pre1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 May 2013 05:34:16 +0000 (13:34 +0800)]
VPP: Update the mapping of VPP filter to internal flag
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 May 2013 05:30:53 +0000 (13:30 +0800)]
remove VAProcFilterColorStandard
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 21 May 2013 08:48:54 +0000 (16:48 +0800)]
VPP/HSW: don't use VAProcFilterColorStandard
VAProcFilterColorStandard will be removed from va_vpp.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 May 2013 08:08:54 +0000 (16:08 +0800)]
Support tiled surface for IMC1/IMC3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 May 2013 08:19:41 +0000 (16:19 +0800)]
Use IMC3 for JPEG decoding
To match the pre-defined VA FOURCC in va.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Thu, 9 May 2013 08:53:07 +0000 (16:53 +0800)]
Add the config attribute of EncMaxRefFrames
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:53:50 +0000 (13:53 +0800)]
PAK encoding uses the reference list parsed from slice_param instead of hacked DPB
Of course it still can work if the slice_param doesn't contain the
valid REfPicList0/1(Hacked DPB mode). This is to be compatible with
the older version of avcenc tool.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:52:31 +0000 (13:52 +0800)]
Unify the AVC ref frame index setting on Snb/Ivy/HSW
This is to remove the duplicated code.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:52:28 +0000 (13:52 +0800)]
VME uses reference frame parsed from slice_param instead of hacked DPB
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Wed, 24 Apr 2013 08:54:09 +0000 (16:54 +0800)]
Clean up gen7_vme_context_init()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:48:58 +0000 (09:48 +0800)]
Rework the VPP CSC shader from NV12 to RGB to eliminate corruption
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:48:12 +0000 (09:48 +0800)]
Fix the incorrect VPP parameter setting on Ivy/Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:47:53 +0000 (09:47 +0800)]
Handle the pitch when using RGBX surface in VPP
Signed-off-by: Ung, Teng En <teng.en.ung@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Wed, 3 Apr 2013 00:58:13 +0000 (08:58 +0800)]
Merge branch 'master' into staging
Conflicts:
NEWS
configure.ac
src/Makefile.am
src/gen6_mfc.c
src/gen6_mfd.c
src/gen6_vme.c
src/gen6_vme.h
src/gen75_mfc.c
src/gen75_mfd.c
src/gen75_vme.c
src/gen75_vpp_vebox.c
src/gen75_vpp_vebox.h
src/gen7_mfd.c
src/i965_avc_bsd.c
src/i965_decoder.h
src/i965_decoder_utils.c
src/i965_defines.h
src/i965_drv_video.c
src/i965_drv_video.h
src/i965_encoder.c
src/i965_encoder.h
src/i965_output_dri.c
src/i965_post_processing.c
src/i965_post_processing.h
src/i965_render.c
src/i965_structs.h
src/intel_driver.c
src/object_heap.c
src/shaders/post_processing/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/Common/Init_All_Regs.asm
src/shaders/post_processing/Makefile.am
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
src/shaders/post_processing/gen5_6/Makefile.am
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
src/shaders/post_processing/gen7/EOT.g4a
src/shaders/post_processing/gen7/Makefile.am
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
src/shaders/post_processing/gen7/Save_AVS_PA.g4a
src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
src/shaders/post_processing/gen7/Set_Layer_0.g4a
src/shaders/post_processing/gen7/VP_Setup.g4a
src/shaders/vme/Makefile.am
src/shaders/vme/inter_frame_haswell.asm
src/shaders/vme/inter_frame_haswell.g75b
src/shaders/vme/intra_frame_haswell.asm
src/shaders/vme/intra_frame_haswell.g75b
src/shaders/vme/vme75.inc
src/shaders/vme/vme7_mpeg2.inc
Li Xiaowei [Tue, 26 Mar 2013 01:06:18 +0000 (09:06 +0800)]
Fix the obj_image error in i965_hw_putimage
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Tue, 19 Mar 2013 05:00:10 +0000 (13:00 +0800)]
Bump version for development.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 19 Mar 2013 02:19:23 +0000 (10:19 +0800)]
libva-intel-driver 1.0.20
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Armin K [Fri, 15 Mar 2013 17:22:10 +0000 (18:22 +0100)]
Automake 1.13 fixups
error: 'AM_CONFIG_HEADER': this macro is obsolete.
You should use the 'AC_CONFIG_HEADERS' macro instead.
warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Added NOCONFIGURE check to autogen.sh
Xiang, Haihao [Fri, 15 Mar 2013 07:39:35 +0000 (15:39 +0800)]
Fix the size to malloc()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:19:49 +0000 (15:19 +0800)]
Check the pointer is NULL or not
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:32:01 +0000 (15:32 +0800)]
Fix potential buffer overflow for JPEG decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:04:12 +0000 (15:04 +0800)]
Remove the dead code in gen6_vme.c
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 05:44:23 +0000 (13:44 +0800)]
Check object for VA buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 04:51:33 +0000 (12:51 +0800)]
Check the object for VA buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 03:16:50 +0000 (11:16 +0800)]
Check the object instance of VAConfig
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 02:50:58 +0000 (10:50 +0800)]
Check the object instance instead of the id for subpicture and image
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 14 Mar 2013 07:47:05 +0000 (15:47 +0800)]
VPP: check the backing store buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 07:26:33 +0000 (15:26 +0800)]
Render: directly use the backing store buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 05:59:18 +0000 (13:59 +0800)]
Decoder: use surface object for the workaround
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 06:11:05 +0000 (14:11 +0800)]
Decoder: directly use surface object for decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 02:43:17 +0000 (10:43 +0800)]
Decoder: Verify picture parameter before set up pipeline for decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 07:12:07 +0000 (15:12 +0800)]
Decoder: check whether the surface for decoding output is valid
In addition, uses the corresponding surface object directly.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 07:34:21 +0000 (15:34 +0800)]
Encoder: directly use the objects for the reference pictures
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 11 Mar 2013 02:44:56 +0000 (10:44 +0800)]
Encoder: directly use the objects for the reconstructed picture and coded buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Mar 2013 06:57:08 +0000 (14:57 +0800)]
Encoder: check whether the coded buffer and reconstructed surface are valid
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 05:25:24 +0000 (13:25 +0800)]
Encoder: unify the initialization of the context
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 05:23:03 +0000 (13:23 +0800)]
Encoder: directly use the surface object of the input surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Mar 2013 02:59:48 +0000 (10:59 +0800)]
Return the status when running the pipeline
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Mar 2013 02:36:41 +0000 (10:36 +0800)]
Silence a bunch of warnings
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 07:55:59 +0000 (15:55 +0800)]
Avoid potential buffer overflow issue
Warning if the slice type is wrong for encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 05:52:12 +0000 (13:52 +0800)]
Release resource if failed to initialize display attributes
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 05:48:02 +0000 (13:48 +0800)]
Fix the initilization path and the termination path in reverse
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 02:04:10 +0000 (10:04 +0800)]
Fix object_heap_init() & object_heap_destroy()
Don't allocate resources if failed to initialize a heap
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Wed, 13 Mar 2013 01:29:23 +0000 (09:29 +0800)]
Issue memory fence message to assure memory ordering on Ivb/Hsw
Otherwise the data inconsistency between different GPU threads
is observed although the GPU threads are spawned by using hardware
scoreboard. Then it causes that avcenc encoding gets the different
results.
Reported-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Li Xiaowei [Tue, 12 Mar 2013 05:25:39 +0000 (13:25 +0800)]
Fix H264 YUV400 surface render issue on IVB
All decoded frame are considered as NV12 format in driver,
for YUV400 stream format decoding senerios, we need set the
chroma component of NV12 to a constant value(0x80), otherwise
the converted ARGB from NV12 format is not correct and cause
blue screen when rending.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Mon, 4 Mar 2013 07:56:06 +0000 (15:56 +0800)]
Update PCI IDs for Haswell CRW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
82d6940694c7a650642ccb6d68bf01b70dba4dcc)
Xiang, Haihao [Mon, 4 Mar 2013 07:56:06 +0000 (15:56 +0800)]
Update PCI IDs for Haswell CRW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 22 Feb 2013 05:56:04 +0000 (13:56 +0800)]
Update the size of DMV buffer for H.264 decoding on IVB
It is at least width_in_mbs * align(height_in_mbs, 2) * 64.
Use width_in_mbs * (height_in_mbs + 1) * 64 in the driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59050
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
00f65b78e6de520a4820702207ce098c6b073724)
Xiang, Haihao [Fri, 22 Feb 2013 05:56:04 +0000 (13:56 +0800)]
Update the size of DMV buffer for H.264 decoding on IVB
It is at least width_in_mbs * align(height_in_mbs, 2) * 64.
Use width_in_mbs * (height_in_mbs + 1) * 64 in the driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59050
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 22 Feb 2013 00:42:33 +0000 (08:42 +0800)]
Don't have flag register f2, use f1 instead
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
f6ec762eab4e602a0644e9f17ce97dab34bf512f)
Conflicts:
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/rgbx_to_nv12.g75b
src/shaders/post_processing/gen7/rgbx_to_nv12.g7b
Xiang, Haihao [Fri, 22 Feb 2013 00:42:33 +0000 (08:42 +0800)]
Don't have flag register f2, use f1 instead
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>