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Andrey Konovalov [Fri, 13 Apr 2018 18:05:21 +0000 (18:05 +0000)]
hwasan: add -fsanitize=kernel-hwaddress flag
This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables
-hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff.
Differential Revision: https://reviews.llvm.org/D45046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330044
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Roman Lebedev [Fri, 13 Apr 2018 17:15:55 +0000 (17:15 +0000)]
[InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.
This was intended since initially, but i did not really think
about it, and did not know how to force that. Now that the
xor->or fold is working (patch upcoming), this came up
to improve the test coverage.
A followup for rL330003, rL330007
https://bugs.llvm.org/show_bug.cgi?id=6773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330039
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Sean Fertile [Fri, 13 Apr 2018 16:42:48 +0000 (16:42 +0000)]
Add PPC64_GLINK dynamic tag.
Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.
Differential Revision: https://reviews.llvm.org/D45574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330038
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Simon Dardis [Fri, 13 Apr 2018 16:09:07 +0000 (16:09 +0000)]
[mips] Materialize constants for multiplication
Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.
The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.
For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant
This resolves PR36884.
Thanks to npl for reporting the issue!
Reviewers: abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D45316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330037
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Simon Pilgrim [Fri, 13 Apr 2018 15:37:56 +0000 (15:37 +0000)]
[X86] Remove remaining itinerary support from instructions and target (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330035
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Sjoerd Meijer [Fri, 13 Apr 2018 15:34:26 +0000 (15:34 +0000)]
[ARM] FP16 vmaxnm/vminnm scalar instructions
This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.
Differential Revision: https://reviews.llvm.org/D44675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330034
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Clement Courbet [Fri, 13 Apr 2018 15:19:16 +0000 (15:19 +0000)]
Revert r330027: "[llvm-exegesis] re-enable failing tests after r330026."
The tests are still failing on some bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330033
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Andrea Di Biagio [Fri, 13 Apr 2018 15:19:07 +0000 (15:19 +0000)]
[llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.
Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.
This patch fixes the issue and adds a test to verify that we don't regress that
particular case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330032
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Yan Luo [Fri, 13 Apr 2018 15:10:34 +0000 (15:10 +0000)]
[ARC] Add LImm support for J/JL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330031
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Simon Pilgrim [Fri, 13 Apr 2018 15:09:39 +0000 (15:09 +0000)]
[X86] Generalize X86FixupLEAs to work with TargetSchedModel
Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330030
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Mircea Trofin [Fri, 13 Apr 2018 15:04:36 +0000 (15:04 +0000)]
[profile] Fix binary format reader error propagation.
Summary:
This was originally part of rL328132, and led to the discovery
of the issues addressed in rL328987. Re-landing.
Reviewers: xur, davidxl, bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330029
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Clement Courbet [Fri, 13 Apr 2018 14:50:10 +0000 (14:50 +0000)]
[llvm-exegesis] re-enable failing tests after r330026.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330027
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Clement Courbet [Fri, 13 Apr 2018 14:46:48 +0000 (14:46 +0000)]
[llvm-exegesis] Fix use after free.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D45625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330026
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Simon Pilgrim [Fri, 13 Apr 2018 14:42:48 +0000 (14:42 +0000)]
Remove comment reference to itineraries. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330025
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Sander de Smalen [Fri, 13 Apr 2018 14:41:36 +0000 (14:41 +0000)]
[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330024
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Simon Pilgrim [Fri, 13 Apr 2018 14:41:05 +0000 (14:41 +0000)]
[X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not WriteFAdd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330023
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Simon Pilgrim [Fri, 13 Apr 2018 14:36:59 +0000 (14:36 +0000)]
[X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330022
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Simon Pilgrim [Fri, 13 Apr 2018 14:31:57 +0000 (14:31 +0000)]
Remove comment references to itineraries. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330021
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Clement Courbet [Fri, 13 Apr 2018 14:29:52 +0000 (14:29 +0000)]
[llvm-exegesis][NFC] Add more logging in case target creation fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330020
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Simon Pilgrim [Fri, 13 Apr 2018 14:24:06 +0000 (14:24 +0000)]
Remove out of data comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330019
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Jun Bum Lim [Fri, 13 Apr 2018 14:23:09 +0000 (14:23 +0000)]
[PostRASink]Add register dependency check for implicit operands
Summary:
This change extend the register dependency check for implicit operands in Copy instructions.
Fixes PR36902.
Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB
Reviewed By: thegameg
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330018
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Roman Lebedev [Fri, 13 Apr 2018 14:07:29 +0000 (14:07 +0000)]
[InstCombine][NFC] Regenerate logical-select.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330017
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Clement Courbet [Fri, 13 Apr 2018 13:37:07 +0000 (13:37 +0000)]
[llvm-exegesis] Create test files in temporary directory.
Currently the test fails in sandboxed environnements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330015
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Sander de Smalen [Fri, 13 Apr 2018 12:56:14 +0000 (12:56 +0000)]
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330014
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Simon Pilgrim [Fri, 13 Apr 2018 12:50:31 +0000 (12:50 +0000)]
[X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330013
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Ivan A. Kosarev [Fri, 13 Apr 2018 12:45:12 +0000 (12:45 +0000)]
[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction
Differential Revision: https://reviews.llvm.org/D45514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330011
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Clement Courbet [Fri, 13 Apr 2018 12:43:55 +0000 (12:43 +0000)]
Partially revert r330008.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330010
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Clement Courbet [Fri, 13 Apr 2018 12:20:30 +0000 (12:20 +0000)]
[llvm-exegesis] Run unit tests on more platforms.
Summary:
- Target-independent tests are run all the time.
- Tests that codegen X86 code are run when X86 is in build targets.
- Tests that run X86 jitted code are run only on X86 hosts.
Reviewers: gchatelet
Subscribers: mgorny, llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D45614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330008
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Roman Lebedev [Fri, 13 Apr 2018 12:00:00 +0000 (12:00 +0000)]
[InstCombine][NFC] Add last few tests with constant mask for masked merge folding.
A followup for rL330003
https://bugs.llvm.org/show_bug.cgi?id=6773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330007
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Hiroshi Inoue [Fri, 13 Apr 2018 11:37:06 +0000 (11:37 +0000)]
[NFC] fix trivial typos in comments
"the the" -> "the", "we we" -> "we", etc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006
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Roman Lebedev [Fri, 13 Apr 2018 10:56:35 +0000 (10:56 +0000)]
[InstCombine][NFC] Add tests for masked merge folding.
https://bugs.llvm.org/show_bug.cgi?id=6773
As discussed there, some backends may want to undo this fold
(x86+bmi for scalars, x86+sse for vectors, ...)
https://bugs.llvm.org/show_bug.cgi?id=37104
https://rise4fun.com/Alive/JXt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330003
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Roman Lebedev [Fri, 13 Apr 2018 09:57:57 +0000 (09:57 +0000)]
[InstCombine]: foldSelectICmpAndAnd(): and is commutative
Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.
I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]
This extends/generalizes that fold, so it is handled too.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45539
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330001
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Sander de Smalen [Fri, 13 Apr 2018 09:11:53 +0000 (09:11 +0000)]
[AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.
Summary:
Added Z_(b|h|s|d) vector list RegisterOperands along with support to
add/print the vector lists.
This is patch [5/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330000
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Gabor Buella [Fri, 13 Apr 2018 07:35:08 +0000 (07:35 +0000)]
[X86] Introduce cldemote instruction
Hint to hardware to move the cache line containing the
address to a more distant level of the cache without
writing back to memory.
Reviewers: craig.topper, zvi
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329992
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Martin Storsjo [Fri, 13 Apr 2018 06:38:02 +0000 (06:38 +0000)]
[Support] Fix building for Windows on ARM
The commit in SVN r310001 that added support for this actually didn't
use the right struct field for the frame pointer - for ARM, there is
no register named Fp in the CONTEXT struct. On Windows, the R11
register is used as frame pointer.
Differential Revision: https://reviews.llvm.org/D45590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329991
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Craig Topper [Fri, 13 Apr 2018 06:07:18 +0000 (06:07 +0000)]
[X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.
This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics.
We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329990
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Yunlian Jiang [Fri, 13 Apr 2018 05:03:28 +0000 (05:03 +0000)]
Enable debug fission for thinLTO linked via gold-plugin
Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user.
Reviewers: tejohnson, pcc, dblaikie
Reviewed By: pcc
Subscribers: JDevlieghere, mehdi_amini, inglorion
Differential Revision: https://reviews.llvm.org/D44792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329988
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Xin Tong [Fri, 13 Apr 2018 04:35:38 +0000 (04:35 +0000)]
[CallSiteSplit] Fix comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329987
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Erik Pilkington [Fri, 13 Apr 2018 02:53:26 +0000 (02:53 +0000)]
Fix another bot failure from r329951.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329986
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Tony Tye [Fri, 13 Apr 2018 01:01:27 +0000 (01:01 +0000)]
[AMDGPU] Update relocation record description
Document which relocation records are static and dynamic.
Differential Revision: https://reviews.llvm.org/D45587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329981
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Aaron Smith [Thu, 12 Apr 2018 23:45:15 +0000 (23:45 +0000)]
[lit] Remove duplicate to_string method
There are two versions of to_string used by TestRunner.py. The one defined
in TestRunner.py and the one defined in utils/lit/lit/util.py. The util.py
version is superior to the TestRunner.py version.
This change removes the duplicate to_string in TestRunner.py in favor of
always using the version from util.py. Beside removing duplicate code, this
makes it easier to debug TestRunner.py since only one version of to_string
is used.
Patch by Stella Stamenova!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329972
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Simon Pilgrim [Thu, 12 Apr 2018 22:57:34 +0000 (22:57 +0000)]
[X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.
Was being used to move around empty/unused itineraries...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329970
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Erik Pilkington [Thu, 12 Apr 2018 22:54:47 +0000 (22:54 +0000)]
Free a pointer, fix a bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329969
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Simon Pilgrim [Thu, 12 Apr 2018 22:44:47 +0000 (22:44 +0000)]
[X86] Remove x86 InstrItinClass entries (PR37093)
This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329967
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Fangrui Song [Thu, 12 Apr 2018 22:27:38 +0000 (22:27 +0000)]
[CachePruning] Clarify the per-directory entry limit on Linux ext4.
Summary:
508 root node entries (root_limit)
510 internal node entries (node_limit)
For a filename with 40 bytes, its sizeof(ext4_dir_entry_2) = 48, a linear directory can contain at most floor(4096/48)=85 of them.
The real per-directory entry limit should be 508*510*85 =
22021800
The limit varies with the average length of filenames.
However, the Linux ext4 code does not try rebalancing the htree, so we will not be able to create filenames in a full leaf node. This is demonstrated with the following example, certain filenames cannot be used while others can:
% touch d/
0000000000000000000000000000000000816a6f
touch: cannot touch 'd/
0000000000000000000000000000000000816a6f': No
space left on device
% touch d/
0000000000000000000000000000000000816a70
# succeeded
Reviewers: pcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329966
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Sanjay Patel [Thu, 12 Apr 2018 22:14:58 +0000 (22:14 +0000)]
[DAGCombiner] simplify code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329964
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Sanjay Patel [Thu, 12 Apr 2018 22:14:23 +0000 (22:14 +0000)]
[PowerPC] add fsub-fneg test; NFC
This is a test for a transform that was suggested in the post-commit
mailing list thread for rL329821. The target in question is not in
trunk, so PPC gets to stand in for it because it's the only in-tree
target that sets 'isFPExtFree()' to 'true'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329963
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Eli Friedman [Thu, 12 Apr 2018 22:04:11 +0000 (22:04 +0000)]
Don't call skipModule for CFI lowering passes.
opt-bisect shouldn't skip these passes; they lower intrinsics which
no other pass can handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329961
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George Burgess IV [Thu, 12 Apr 2018 21:38:43 +0000 (21:38 +0000)]
[ProfileSummary] Remove repeated cutoffs; NFCI
I'm told the repeat of "500000, 600000," is accidental, and should be
removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329959
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Brian Gesiak [Thu, 12 Apr 2018 21:28:04 +0000 (21:28 +0000)]
Let llvm-diff correctly deal with Undef/ConstantAggregateZero/ConstantVector/IndirectBr
Summary:
llvm-diff incorrectly reports that there's a diff when input IR contains undef/zeroinitializer/constantvector/indirectbr.
(This happens even if two identical files are given, e.g. `llvm-diff x.ll x.ll`)
This is fix to the bug report https://bugs.llvm.org/show_bug.cgi?id=33623 .
Reviewers: dexonsmith, rjmccall
Reviewed By: rjmccall
Subscribers: chenwj, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D34856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329957
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Peter Collingbourne [Thu, 12 Apr 2018 21:23:55 +0000 (21:23 +0000)]
AArch64: Introduce a DAG combine for folding offsets into addresses.
This is a code size win in code that takes offseted addresses
frequently, such as C++ constructors that typically need to compute
an offseted address of a vtable. This reduces the size of Chromium
for Android's .text section by 108KB.
Differential Revision: https://reviews.llvm.org/D45199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329956
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Vedant Kumar [Thu, 12 Apr 2018 20:58:24 +0000 (20:58 +0000)]
[DebugInfo] Create merged locations for instructions other than calls
This lifts a restriction on DILocation::getMergedLocation(), allowing it
to create merged locations for instructions other than calls.
Instruction::applyMergedLocation() now defaults to creating merged
locations for all instructions.
The default behavior of getMergedLocation() is unchanged: callers which
invoke it directly are unaffected.
This change will enable a follow-up Mem2Reg fix which improves crash
reporting.
Differential Revision: https://reviews.llvm.org/D45396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329955
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George Burgess IV [Thu, 12 Apr 2018 20:54:05 +0000 (20:54 +0000)]
[ProfileSummary] Move a vector we're about to destroy anyway; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329954
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Simon Pilgrim [Thu, 12 Apr 2018 20:47:34 +0000 (20:47 +0000)]
[X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329953
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Erik Pilkington [Thu, 12 Apr 2018 20:41:38 +0000 (20:41 +0000)]
[demangler] Add a partial demangling API for LLDB.
This parses a mangled name into an AST (typically an intermediate stage in
itaniumDemangle) and provides some functions to query certain properties or
print certain parts of the demangled name.
Differential revision: https://reviews.llvm.org/D44668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329951
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Erik Pilkington [Thu, 12 Apr 2018 20:41:06 +0000 (20:41 +0000)]
[demangler] NFC: Some refactoring to support partial demangling.
I'm committing this to libcxxabi too so that the two demanglers remain as
simular as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329950
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Sam Clegg [Thu, 12 Apr 2018 20:31:12 +0000 (20:31 +0000)]
[WebAssembly] libObject: Don't include the name the size of custom sections
Differential Revision: https://reviews.llvm.org/D45579
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329947
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Simon Pilgrim [Thu, 12 Apr 2018 19:59:35 +0000 (19:59 +0000)]
[X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329945
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Lang Hames [Thu, 12 Apr 2018 19:54:41 +0000 (19:54 +0000)]
[ORC] Use insert rather than emplace.
Hopefully this will fix the build failure at
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/9028
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329944
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George Burgess IV [Thu, 12 Apr 2018 19:48:05 +0000 (19:48 +0000)]
Simplify; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329943
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Simon Pilgrim [Thu, 12 Apr 2018 19:25:07 +0000 (19:25 +0000)]
[X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329940
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Sameer AbuAsal [Thu, 12 Apr 2018 19:22:40 +0000 (19:22 +0000)]
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
Summary:
GCC compresses the pseudo instruction "mv rd, rs", which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".
In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.
In this patch we fix that by adding an addi to c.mv compression pattern, the
instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
gcc does.
Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).
Reviewers: asb, apazos, zzheng, mgrang, shiva0217
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D45583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329939
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Simon Pilgrim [Thu, 12 Apr 2018 18:46:15 +0000 (18:46 +0000)]
[X86] Remove remaining gpr schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329938
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Gabor Buella [Thu, 12 Apr 2018 18:38:18 +0000 (18:38 +0000)]
[X86] Introduce LLVM wbinvd intrinsic
A previously missing intrinsic for an old instruction.
Reviewers: craig.topper, echristo
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D45312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329936
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George Burgess IV [Thu, 12 Apr 2018 18:36:01 +0000 (18:36 +0000)]
Fix a typo in a comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329935
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Lang Hames [Thu, 12 Apr 2018 18:35:08 +0000 (18:35 +0000)]
[ORC] Plumb error notifications through the VSO interface.
This allows materializers to notify the VSO that they were unable to
resolve or finalize symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329934
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Simon Pilgrim [Thu, 12 Apr 2018 18:25:38 +0000 (18:25 +0000)]
[X86] Remove gpr shift/extension schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329933
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Lei Huang [Thu, 12 Apr 2018 18:00:14 +0000 (18:00 +0000)]
[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Legalize and emit code for:
* xscvsdqp
* xscvudqp
Differential Revision: https://reviews.llvm.org/D45230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329931
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Benjamin Kramer [Thu, 12 Apr 2018 17:28:30 +0000 (17:28 +0000)]
[MCJIT] Remove the anchor from mcjit.
This is a layering violation. LTO shouldn't depend on MCJIT. The right
fix for this is moving the class somewhere else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329929
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Petar Jovanovic [Thu, 12 Apr 2018 17:01:46 +0000 (17:01 +0000)]
[MIPS GlobalISel] remove superfluous #includes (NFC)
Remove superfluous #includes.
Minor code style change in MipsCallLowering::lowerFormalArguments().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329926
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Jessica Paquette [Thu, 12 Apr 2018 16:16:18 +0000 (16:16 +0000)]
[AArch64] Move AFI->setRedZone(false) to top of emitPrologue
AFI->setRedZone(false) was put in the wrong place before, and so it only fired
on functions that didn't have stack frames. This moves that to the top of
emitPrologue to make sure that every function without a redzone has it set
correctly.
This also adds a function representing one of the early exit cases (GHC calling
convention) to the MachineOutliner noredzone test to ensure that we can outline
from functions like these, where we never use a redzone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329922
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Sanjay Patel [Thu, 12 Apr 2018 15:27:01 +0000 (15:27 +0000)]
revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)
This change is exposing UB in source code - as was warned/predicted. :)
See D44909 for discussion. Reverting while we figure out how to fix things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329920
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Krzysztof Parzyszek [Thu, 12 Apr 2018 15:11:11 +0000 (15:11 +0000)]
[Pipeliner] Use std::stable_sort when ordering NodeSets
There are cases when individual NodeSets can be equal with respect to
the ordering criteria. Since they are stored in an ordered container,
use stable_sort to preserve the relative order of equal NodeSets.
This should remove non-determinism discovered by shuffling done in
llvm::sort with expensive checks enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329915
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Simon Dardis [Thu, 12 Apr 2018 14:41:38 +0000 (14:41 +0000)]
[mips] Correct the predicates of the load/store (double)word for coprocessor 3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329913
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Simon Pilgrim [Thu, 12 Apr 2018 14:31:42 +0000 (14:31 +0000)]
[X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329912
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Benjamin Kramer [Thu, 12 Apr 2018 13:52:02 +0000 (13:52 +0000)]
Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."
This reverts commit r329865. Causes stage2/stage3 miscompare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329910
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Sander de Smalen [Thu, 12 Apr 2018 13:19:32 +0000 (13:19 +0000)]
[AArch64][AsmParser] Unify 'addVectorListOperands' functions.
Summary:
Merged 'addVectorList64Operands' and 'addVectorList128Operands' into a
generic 'addVectorListOperands', which can be easily extended to work
for SVE vectors.
This is patch [4/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329909
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Francis Visoiu Mistrih [Thu, 12 Apr 2018 12:59:50 +0000 (12:59 +0000)]
[CodeGen] Allow printing MachineMemOperands with less context in SDAGDumper
Don't assume SelectionDAG is non-null as the targets can use it with a
null pointer.
Differential Revision: https://reviews.llvm.org/D44611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329908
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Sam Parker [Thu, 12 Apr 2018 12:49:40 +0000 (12:49 +0000)]
[IRCE] isKnownNonNegative helper function
Created a helper function to query for non negative SCEVs. Uses the
SGE predicate to catch constants that could be interpreted as
negative.
Differential Revision: https://reviews.llvm.org/D45481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329907
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Simon Pilgrim [Thu, 12 Apr 2018 12:43:49 +0000 (12:43 +0000)]
[X86] Remove remaining system/special schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329906
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Simon Dardis [Thu, 12 Apr 2018 12:37:02 +0000 (12:37 +0000)]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D44436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329905
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Simon Pilgrim [Thu, 12 Apr 2018 12:09:24 +0000 (12:09 +0000)]
[X86] Remove system/control schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329903
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Roman Lebedev [Thu, 12 Apr 2018 12:04:57 +0000 (12:04 +0000)]
[InstCombine][NFC]: Add tests: foldSelectICmpAndAnd(): and is commutative
Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.
I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329901
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Sander de Smalen [Thu, 12 Apr 2018 11:40:52 +0000 (11:40 +0000)]
[AArch64][AsmParser] Make parse function for VectorLists generic to other vector types.
Summary:
Added 'RegisterKind' to the VectorListOp structure, so that this operand
type can be reused for SVE vector lists in a later patch. It also
refactors the 'tryParseVectorList' function so it can be used directly
in the ParserMethod of an operand. The parsing can now parse multiple
kinds of vectors and recover if there is no match.
This is patch [3/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329900
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Shiva Chen [Thu, 12 Apr 2018 11:30:59 +0000 (11:30 +0000)]
[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC
Summary:
According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only
allow 32-bit instruction alignment, but instruction allow to be aligned
to 16-bit boundaries for C-extension.
So we just align to 4 bytes and 2 bytes for C-extension is enough.
Reviewers: asb, apazos
Differential Revision: https://reviews.llvm.org/D45560
Patch by Kito Cheng.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329899
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Simon Pilgrim [Thu, 12 Apr 2018 11:01:40 +0000 (11:01 +0000)]
[X86] Remove CMOV/SETCC schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329898
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Simon Pilgrim [Thu, 12 Apr 2018 10:49:57 +0000 (10:49 +0000)]
[X86] Remove MMX/3DNow schedule itineraries (PR37093)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329896
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Andrea Di Biagio [Thu, 12 Apr 2018 10:49:40 +0000 (10:49 +0000)]
[llvm-mca] Removed unused argument from cycleEvent. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329895
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Simon Pilgrim [Thu, 12 Apr 2018 10:27:37 +0000 (10:27 +0000)]
[X86] Remove X87 schedule itineraries (PR37093)
First of a number of commits to remove x86 schedule itineraries entirely - approved off-line with @craig.topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329893
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Petar Jovanovic [Thu, 12 Apr 2018 09:12:29 +0000 (09:12 +0000)]
[MIPS GlobalISel] minor update to MIR tests added in r329819
Remove 'registers' section, as suggested (D. Sanders) at code review
https://reviews.llvm.org/D44304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329888
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Jonas Paulsson [Thu, 12 Apr 2018 08:08:42 +0000 (08:08 +0000)]
[SystemZ] Use ResourceCycles=30 for FPd unit (NFC).
This is better than listing FPd 30 times :-)
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329887
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Jonas Paulsson [Thu, 12 Apr 2018 08:06:04 +0000 (08:06 +0000)]
[SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels.
This is NFC, even though it caught just a few cases of overlapping regular
expressions.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329886
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Jonas Paulsson [Thu, 12 Apr 2018 07:39:33 +0000 (07:39 +0000)]
[HexagonMachineScheduler] Remove local (copied) getWeakLeft().
Since the common code getWeakLeft() is now available, there should not
be a local copy of this function in target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329885
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Jonas Paulsson [Thu, 12 Apr 2018 07:21:39 +0000 (07:21 +0000)]
[MachineScheduler] NFC refactoring
This patch makes tryCandidate() virtual and some utility functions like
tryLess(), tryGreater(), ... externally available (used to be static).
This makes it possible for a target to derive a new MachineSchedStrategy from
GenericScheduler and reuse most parts.
It was necessary to wrap functions with the same names in
AMDGPU/SIMachineScheduler in a local namespace.
Review: Andy Trick, Florian Hahn
https://reviews.llvm.org/D43329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329884
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Craig Topper [Thu, 12 Apr 2018 06:51:58 +0000 (06:51 +0000)]
[LegalizeTypes] Remove unnecessary type action check on the type of operand 0 when promoting shift result type. NFC
Operand 0 should have the same type of the result. So if the result type needs to be promoted, operand 0 needs to be promoted unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329883
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Hiroshi Inoue [Thu, 12 Apr 2018 05:53:20 +0000 (05:53 +0000)]
[NFC] fix trivial typos in documents and comments
"is is" -> "is", "if if" -> "if", "or or" -> "or"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329878
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Alex Bradbury [Thu, 12 Apr 2018 05:50:06 +0000 (05:50 +0000)]
[RISCV] Codegen support for RV32D floating point comparison operations
Also add double-prevoius-failure.ll which captures a test case that at one
point triggered a compiler crash, while developing calling convention support
for f64 on RV32D with soft-float ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329877
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Alex Bradbury [Thu, 12 Apr 2018 05:47:15 +0000 (05:47 +0000)]
[RISCV] Codegen support for RV32D floating point conversion operations
This also includes support and a test for truncating stores, which are now
possible thanks to the fpround pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329876
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Alex Bradbury [Thu, 12 Apr 2018 05:42:42 +0000 (05:42 +0000)]
[RISCV] Add codegen support for RV32D floating point arithmetic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329874
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Alex Bradbury [Thu, 12 Apr 2018 05:36:44 +0000 (05:36 +0000)]
[RISCV] Add tests missed in r329871
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329872
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