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Sanjay Patel [Tue, 16 May 2017 20:09:32 +0000 (20:09 +0000)]
[InstCombine] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303203
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Dmitry Mikulin [Tue, 16 May 2017 20:08:49 +0000 (20:08 +0000)]
In debug builds non-trivial amount of time is spent in InstCombine processing
@llvm.dbg.* calls in visitCallInst(). They can be safely ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303202
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Daniel Berlin [Tue, 16 May 2017 20:02:45 +0000 (20:02 +0000)]
NewGVN: Only do something in verifyStoreExpressions if assertions are enabled, to avoid unused code warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303201
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Daniel Berlin [Tue, 16 May 2017 19:58:47 +0000 (19:58 +0000)]
NewGVN: Fix PR 33051 by making sure we remove old store expressions
from the ExpressionToClass mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303200
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Reid Kleckner [Tue, 16 May 2017 19:55:03 +0000 (19:55 +0000)]
Revert "[X86] Replace slow LEA instructions in X86"
This reverts commit r303183, it broke various buildbots and introduced
sanitizer errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303199
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Nirav Dave [Tue, 16 May 2017 19:43:56 +0000 (19:43 +0000)]
Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303198
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Matthias Braun [Tue, 16 May 2017 18:43:30 +0000 (18:43 +0000)]
ShrinkWrap: Add skipFunction() call
ShrinkWrapping is a performance optimization that can safely be skipped,
so we can add `if (!skipFunction()) return;`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303197
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Davide Italiano [Tue, 16 May 2017 18:41:46 +0000 (18:41 +0000)]
[MetadataLoader] Remove unused Vector. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303196
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Renato Golin [Tue, 16 May 2017 17:59:07 +0000 (17:59 +0000)]
Revert "[ARM] Mark LEApcrel instructions as isAsCheapAsAMove"
Revert "[ARM] Mark LEApcrel as not having side effects"
This reverts commit r303054 and r303053, as they broke the ARM
self-hosting buildbots:
http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/1550
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost-neon/builds/1349
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15-selfhost/builds/1845
Offline investigation on course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303193
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Stanislav Mekhanoshin [Tue, 16 May 2017 16:31:45 +0000 (16:31 +0000)]
[AMDGPU] Use GCNRPTracker dumper methods in scheduler
Differential Revision: https://reviews.llvm.org/D33244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303186
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Sanjay Patel [Tue, 16 May 2017 16:30:46 +0000 (16:30 +0000)]
[InstCombine] add motivational comment for tests; NFC
The referenced tests are derived from:
https://bugs.llvm.org/show_bug.cgi?id=32791
and:
https://reviews.llvm.org/D33172
The motivation for including negative tests may not be clear, so I'm adding an explanatory comment here.
In the post-commit thread for r303133:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20170515/453793.html
...it was mentioned that we don't want to add redundant tests. This is a valid point. But in this case,
we have a patch under review (D33172) that demonstrates that no existing regression tests are affected by
a proposed code change, but these are. Therefore, I think these tests have value not visible in any
existing regression tests regardless of whether they show a transform.
Differential Revision: https://reviews.llvm.org/D33242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303185
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Stanislav Mekhanoshin [Tue, 16 May 2017 16:11:26 +0000 (16:11 +0000)]
[AMDGPU] Cache live-ins and register pressure in scheduler
Using LIS can be quite expensive, so caching of calculated region
live-ins and pressure is implemented. It does two things:
1. Caches the info for the second stage when we schedule with
decreased target occupancy.
2. Tracks the basic block from top to bottom thus eliminating the
need to scan whole register file liveness at every region split
in the middle of the block.
The scheduling is now done in 3 stages instead of two, with the first
one being really a no-op and only used to collect scheduling regions
as sent by the scheduler driver.
There is no functional change to the current behavior, only compilation
speed is affected. In general computeBlockPressure() could be simplified
if we switch to backward RP tracker, because scheduler sends regions
within a block starting from the last upward. We could use a natural
order of upward tracker to seamlessly change between regions of the same
block, since live reg set of a previous tracked region would become a
live-out of the next region. That however requires fixing upward tracker
to properly account defs and uses of the same instruction as both are
contributing to the current pressure. When we converge on the produced
pressure we should be able to switch between them back and forth. In
addition, backward tracker is less expensive as it uses LIS in recede
less often than forward uses it in advance.
At the moment the worst known case compilation time has improved from 26
minutes to 8.5.
Differential Revision: https://reviews.llvm.org/D33117
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303184
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Lama Saba [Tue, 16 May 2017 16:01:36 +0000 (16:01 +0000)]
[X86] Replace slow LEA instructions in X86
According to Intel's Optimization Reference Manual for SNB+:
" For LEA instructions with three source operands and some specific situations, instruction latency has increased to 3 cycles, and must
dispatch via port 1:
- LEA that has all three source operands: base, index, and offset
- LEA that uses base and index registers where the base is EBP, RBP,or R13
- LEA that uses RIP relative addressing mode
- LEA that uses 16-bit addressing mode "
This patch currently handles the first 2 cases only.
Differential Revision: https://reviews.llvm.org/D32277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303183
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Matthew Simpson [Tue, 16 May 2017 15:50:30 +0000 (15:50 +0000)]
Revert 303174, 303176, and 303178
These commits are breaking the bots. Reverting to investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303182
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Nirav Dave [Tue, 16 May 2017 15:49:02 +0000 (15:49 +0000)]
[DAG] Prune deleted nodes in TokenFactor
Fix visitTokenFactor to correctly remove deleted nodes. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303181
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Stanislav Mekhanoshin [Tue, 16 May 2017 15:43:52 +0000 (15:43 +0000)]
[AMDGPU] Turn register pressure estimation into forward tracker
This factors register pressure estimation mechanism from the
GCNSchedStrategy into the forward tracker to unify interface
with other strategies and expose it to other interested phases.
Differential Revision: https://reviews.llvm.org/D33105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303179
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Matthew Simpson [Tue, 16 May 2017 15:33:22 +0000 (15:33 +0000)]
Make test target-specific
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303178
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Matthew Simpson [Tue, 16 May 2017 15:20:27 +0000 (15:20 +0000)]
Fix test case to unbreak bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303176
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Matthew Simpson [Tue, 16 May 2017 14:43:55 +0000 (14:43 +0000)]
[LV] Avoid potentential division by zero when selecting IC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303174
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Gor Nishanov [Tue, 16 May 2017 14:11:39 +0000 (14:11 +0000)]
[coroutines] Handle unwind edge splitting
Summary:
RewritePHIs algorithm used in building of CoroFrame inserts a placeholder
```
%placeholder = phi [%val]
```
on every edge leading to a block starting with PHI node with multiple incoming edges,
so that if one of the incoming values was spilled and need to be reloaded, we have a
place to insert a reload. We use SplitEdge helper function to split the incoming edge.
SplitEdge function does not deal with unwind edges comping into a block with an EHPad.
This patch adds an ehAwareSplitEdge function that can correctly split the unwind edge.
For landing pads, we clone the landing pad into every edge block and replace the original
landing pad with a PHI collection the values from all incoming landing pads.
For WinEH pads, we keep the original EHPad in place and insert cleanuppad/cleapret in the
edge blocks.
Reviewers: majnemer, rnk
Reviewed By: majnemer
Subscribers: EricWF, llvm-commits
Differential Revision: https://reviews.llvm.org/D31845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303172
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George Rimar [Tue, 16 May 2017 14:05:45 +0000 (14:05 +0000)]
[DWARF] - Add RelocAddrEntry for cleanup. NFCi.
Was mentioned as possible cleanup during review of D33184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303171
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Igor Breger [Tue, 16 May 2017 13:37:31 +0000 (13:37 +0000)]
[GlobalISel][X86] Split memop test file. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303169
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Chad Rosier [Tue, 16 May 2017 12:43:23 +0000 (12:43 +0000)]
Fix an improperly placed curly bracket. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303165
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George Rimar [Tue, 16 May 2017 12:30:59 +0000 (12:30 +0000)]
[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector.
Recommit of r303159 "[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector"
All places were shitched to use DWARFAddressRange now.
Suggested during review of D33184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303163
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George Rimar [Tue, 16 May 2017 12:05:03 +0000 (12:05 +0000)]
Revert r303159 "[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector."
Something went wrong, it broke BB.
http://green.lab.llvm.org/green//job/clang-stage1-cmake-RA-incremental_build/38477/consoleFull#-
200034420049ba4694-19c4-4d7e-bec5-
911270d8a58c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303162
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George Rimar [Tue, 16 May 2017 11:54:19 +0000 (11:54 +0000)]
[DWARF] - Use DWARFAddressRange struct instead of uint64_t pair for DWARFAddressRangesVector.
Suggested during review of D33184.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303159
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James Henderson [Tue, 16 May 2017 09:43:21 +0000 (09:43 +0000)]
[LTO] Print time-passes information at conclusion of LTO codegen
The information collected when requested by -time-passes is only printed when
llvm_shutdown is called at the moment. This means that when linking against the LTO
library dynamically and using the C interface, it is not possible to see the timing
information, because llvm_shutdown cannot be called. This change modifies the LTO
code generation functions for both regular LTO and thin LTO to explicitly print and
reset the timing information.
I have tested that this works with our proprietary linker. However, as this relies
on a specific method of building and linking against the LTO library, I'm not sure
how or if this can be tested in the LLVM testsuite.
Reviewed by: mehdi_amini
Differential Revision: https://reviews.llvm.org/D32803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303152
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Max Kazantsev [Tue, 16 May 2017 07:27:06 +0000 (07:27 +0000)]
[SCEV] Fix sorting order for AddRecExprs
The existing sorting order in defined CompareSCEVComplexity sorts AddRecExprs
by loop depth, but does not pay attention to dominance of loops. This can
lead us to the following buggy situation:
for (...) { // loop1
op1 = {A,+,B}
}
for (...) { // loop2
op2 = {A,+,B}
S = add op1, op2
}
In this case there is no guarantee that in operand list of S the op2 comes
before op1 (loop depth is the same, so they will be sorted just
lexicographically), so we can incorrectly treat S as a recurrence of loop1,
which is wrong.
This patch changes the sorting logic so that it places the dominated recs
before the dominating recs. This ensures that when we pick the first recurrency
in the operands order, it will be the bottom-most in terms of domination tree.
The attached test set includes some tests that produce incorrect SCEV
estimations and crashes with oldlogic.
Reviewers: sanjoy, reames, apilipenko, anna
Reviewed By: sanjoy
Subscribers: llvm-commits, mzolotukhin
Differential Revision: https://reviews.llvm.org/D33121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303148
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Craig Topper [Tue, 16 May 2017 07:05:38 +0000 (07:05 +0000)]
[CorrelatedValuePropagation] Don't use -> to call a static method of ConstantRange. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303147
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Daniel Berlin [Tue, 16 May 2017 06:06:15 +0000 (06:06 +0000)]
NewGVN: Use StoreExpression StoredValue instead of looking it up again, since it was already looked up when it was created
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303144
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Daniel Berlin [Tue, 16 May 2017 06:06:12 +0000 (06:06 +0000)]
NewGVN: Formatting fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303143
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Davide Italiano [Tue, 16 May 2017 05:51:21 +0000 (05:51 +0000)]
Revert "[NewGVN] Replace predicate info leftovers."
It's breaking the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303142
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Davide Italiano [Tue, 16 May 2017 05:23:23 +0000 (05:23 +0000)]
[NewGVN] Replace predicate info leftovers.
Fixes PR32945.
Differential Revision: https://reviews.llvm.org/D33226
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303141
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NAKAMURA Takumi [Tue, 16 May 2017 04:01:23 +0000 (04:01 +0000)]
AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303137
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Peter Collingbourne [Tue, 16 May 2017 00:39:01 +0000 (00:39 +0000)]
IR: Give function GlobalValue::getRealLinkageName() a less misleading name: dropLLVMManglingEscape().
This function gives the wrong answer on some non-ELF platforms in some
cases. The function that does the right thing lives in Mangler.h. To try to
discourage people from using this function, give it a different name.
Differential Revision: https://reviews.llvm.org/D33162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303134
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Sanjay Patel [Mon, 15 May 2017 23:59:28 +0000 (23:59 +0000)]
[InstCombine] add tests for PR32791; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303133
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Francis Visoiu Mistrih [Mon, 15 May 2017 23:13:35 +0000 (23:13 +0000)]
[ShrinkWrapping] Handle restores on no-return paths
Shrink-wrapping uses post-dominators to find a restore point that
post-dominates all the uses of CSR / stack.
The way dominator trees are modeled in LLVM today is that unreachable
blocks are not present in a generic dominator tree, so, an unreachable node is
dominated by anything: include/llvm/Support/GenericDomTree.h:467.
Since for post-dominators, a no-return block is considered
"unreachable", calling findNearestCommonDominator on an unreachable node
A and a non-unreachable node B, will return B, which can be false. If we
find such node, we bail out since there is no good restore point
available.
rdar://problem/
30186931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303130
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Kostya Serebryany [Mon, 15 May 2017 22:55:00 +0000 (22:55 +0000)]
[libFuzzer] fix tests on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303128
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Sanjay Patel [Mon, 15 May 2017 22:54:37 +0000 (22:54 +0000)]
[InstSimplify] add tests for unnecessary mask of shifted values; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303127
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Xinliang David Li [Mon, 15 May 2017 22:43:52 +0000 (22:43 +0000)]
Fix memory leak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303126
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Kostya Serebryany [Mon, 15 May 2017 22:38:29 +0000 (22:38 +0000)]
[libFuzzer] improve the afl driver and it's tests. Make it possible to run individual inputs with afl driver
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303125
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Rui Ueyama [Mon, 15 May 2017 22:32:34 +0000 (22:32 +0000)]
Fix git command line in the Getting Started guide.
By default, git creates "llvm-project-
20170507" directory,
but we want to create "llvm-project" directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303124
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Justin Bogner [Mon, 15 May 2017 22:15:22 +0000 (22:15 +0000)]
Add "REQUIRES:" to the last few tests that use target specific intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303123
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Davide Italiano [Mon, 15 May 2017 22:10:15 +0000 (22:10 +0000)]
[AMDGPU] Kill now unused phiInfoElementGetDebugLoc(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303122
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Craig Topper [Mon, 15 May 2017 22:01:03 +0000 (22:01 +0000)]
[APInt] Simplify a for loop initialization based on the fact that 'n' is known to be 1 by an earlier 'if'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303120
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Eugene Zelenko [Mon, 15 May 2017 21:57:41 +0000 (21:57 +0000)]
[IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303119
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Tim Northover [Mon, 15 May 2017 21:51:38 +0000 (21:51 +0000)]
AArch64: use linker-private symbols for globals in MachO.
We don't use section-relative relocations on AArch64, so all symbols must be at
least visible to the linker (i.e. properly global or l_whatever, but not
L_whatever).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303118
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David Blaikie [Mon, 15 May 2017 21:34:01 +0000 (21:34 +0000)]
PR32288: Describe a bool parameter's DWARF location with a simple register
There's no need (& a bit incorrect) to mask off the high bits of the
register reference when describing a simple bool value.
Reviewers: aprantl
Differential Revision: https://reviews.llvm.org/D31062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303117
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Adam Nemet [Mon, 15 May 2017 21:15:01 +0000 (21:15 +0000)]
[SLP] Enable 64-bit wide vectorization on AArch64
ARM Neon has native support for half-sized vector registers (64 bits). This
is beneficial for example for 2D and 3D graphics. This patch adds the option
to lower MinVecRegSize from 128 via a TTI in the SLP Vectorizer.
*** Performance Analysis
This change was motivated by some internal benchmarks but it is also
beneficial on SPEC and the LLVM testsuite.
The results are with -O3 and PGO. A negative percentage is an improvement.
The testsuite was run with a sample size of 4.
** SPEC
* CFP2006/482.sphinx3 -3.34%
A pretty hot loop is SLP vectorized resulting in nice instruction reduction.
This used to be a +22% regression before rL299482.
* CFP2000/177.mesa -3.34%
* CINT2000/256.bzip2 +6.97%
My current plan is to extend the fix in rL299482 to i16 which brings the
regression down to +2.5%. There are also other problems with the codegen in
this loop so there is further room for improvement.
** LLVM testsuite
* SingleSource/Benchmarks/Misc/ReedSolomon -10.75%
There are multiple small SLP vectorizations outside the hot code. It's a bit
surprising that it adds up to 10%. Some of this may be code-layout noise.
* MultiSource/Benchmarks/VersaBench/beamformer/beamformer -8.40%
The opt-viewer screenshot can be seen at
F3218284. We start at a colder store
but the tree leads us into the hottest loop.
* MultiSource/Applications/lambda-0.1.3/lambda -2.68%
* MultiSource/Benchmarks/Bullet/bullet -2.18%
This is using 3D vectors.
* SingleSource/Benchmarks/Shootout-C++/Shootout-C++-lists +6.67%
Noise, binary is unchanged.
* MultiSource/Benchmarks/Ptrdist/anagram/anagram +4.90%
There is an additional SLP in the cold code. The test runs for ~1sec and
prints out over 2000 lines. This is most likely noise.
* MultiSource/Applications/aha/aha +1.63%
* MultiSource/Applications/JM/lencod/lencod +1.41%
* SingleSource/Benchmarks/Misc/richards_benchmark +1.15%
Differential Revision: https://reviews.llvm.org/D31965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303116
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Hans Wennborg [Mon, 15 May 2017 20:59:32 +0000 (20:59 +0000)]
Revert r302678 "[AArch64] Enable use of reduction intrinsics."
This caused PR33053.
Original commit message:
> The new experimental reduction intrinsics can now be used, so I'm enabling this
> for AArch64. We will need this for SVE anyway, so it makes sense to do this for
> NEON reductions as well.
>
> The existing code to match shufflevector patterns are replaced with a direct
> lowering of the reductions to AArch64-specific nodes. Tests updated with the
> new, simpler, representation.
>
> Differential Revision: https://reviews.llvm.org/D32247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303115
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Evgeniy Stepanov [Mon, 15 May 2017 20:43:42 +0000 (20:43 +0000)]
[asan] Better workaround for gold PR19002.
See the comment for more details. Test in a follow-up CFE commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303113
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Jan Sjodin [Mon, 15 May 2017 20:18:37 +0000 (20:18 +0000)]
Re-submit AMDGPUMachineCFGStructurizer.
Differential Revision: https://reviews.llvm.org/D23209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303111
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Tim Northover [Mon, 15 May 2017 19:42:15 +0000 (19:42 +0000)]
AArch64: diagnose unrecognized features in .cpu directive.
We were silently ignoring any features we couldn't match up, which led to
errors in an inline asm block missing the conventional "\n\t".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303108
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Davide Italiano [Mon, 15 May 2017 19:35:40 +0000 (19:35 +0000)]
[NewGVN] Remove unused setDefiningExpr(). NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303107
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Sanjay Patel [Mon, 15 May 2017 19:27:53 +0000 (19:27 +0000)]
[InstCombine] restrict icmp fold with 2 sdiv exact operands (PR32949)
This is the InstCombine counterpart to D32954.
I added some comments about the code duplication in:
rL302436
Alive-based verification:
http://rise4fun.com/Alive/dPw
This is a 2nd fix for the problem reported in:
https://bugs.llvm.org/show_bug.cgi?id=32949
Differential Revision: https://reviews.llvm.org/D32970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303105
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Sanjay Patel [Mon, 15 May 2017 19:16:49 +0000 (19:16 +0000)]
[InstSimplify] restrict icmp fold with 2 sdiv exact operands (PR32949)
These folds were introduced with https://reviews.llvm.org/rL127064 as part of solving:
https://bugs.llvm.org/show_bug.cgi?id=9343
As shown here:
http://rise4fun.com/Alive/C8
...however, the sdiv exact case needs a stronger predicate.
I opted for duplicated code instead of adding another fallthrough because I think that's
easier to read (and edit in case we need/want to restrict/loosen the predicates any more).
This should fix:
https://bugs.llvm.org/show_bug.cgi?id=32949
https://bugs.llvm.org/show_bug.cgi?id=32948
Differential Revision: https://reviews.llvm.org/D32954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303104
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Evgeny Stupachenko [Mon, 15 May 2017 19:08:56 +0000 (19:08 +0000)]
The patch adds CTLZ idiom recognition.
Summary:
The following loops should be recognized:
i = 0;
while (n) {
n = n >> 1;
i++;
body();
}
use(i);
And replaced with builtin_ctlz(n) if body() is empty or
for CPUs that have CTLZ instruction converted to countable:
for (j = 0; j < builtin_ctlz(n); j++) {
n = n >> 1;
i++;
body();
}
use(builtin_ctlz(n));
Reviewers: rengolin, joerg
Differential Revision: http://reviews.llvm.org/D32605
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303102
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Davide Italiano [Mon, 15 May 2017 18:50:53 +0000 (18:50 +0000)]
[NewGVN] Fix verification of MemoryPhis in verifyMemoryCongruency().
verifyMemoryCongruency() filters out trivially dead MemoryDef(s),
as we find them immediately dead, before moving from TOP to a new
congruence class.
This fixes the same problem for PHI(s) skipping MemoryPhis if all
the operands are dead.
Differential Revision: https://reviews.llvm.org/D33044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303100
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Geoff Berry [Mon, 15 May 2017 18:50:22 +0000 (18:50 +0000)]
[AArch64][Falkor] Fix sched details for FMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303099
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Jan Sjodin [Mon, 15 May 2017 18:39:47 +0000 (18:39 +0000)]
Revert 303091.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303098
91177308-0d34-0410-b5e6-
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Teresa Johnson [Mon, 15 May 2017 18:28:29 +0000 (18:28 +0000)]
Add support for handling ifuncs to GlobalValue::getBaseObject
Summary:
All GlobalIndirectSymbol types (not just GlobalAlias) should return
their base object.
Without this patch LTO would warn "Unable to determine comdat of
alias!" for an ifunc.
Reviewers: pcc
Subscribers: mehdi_amini, inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D33202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303096
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Craig Topper [Mon, 15 May 2017 18:14:16 +0000 (18:14 +0000)]
[SCEV] Use copy initialization of APInts instead of direct initialization.
This is based on post commit feed back from r302769.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303092
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Jan Sjodin [Mon, 15 May 2017 18:13:56 +0000 (18:13 +0000)]
Add AMDGPUMachineCFGStructurizer.
Differential Revision: https://reviews.llvm.org/D23209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303091
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Sanjay Patel [Mon, 15 May 2017 18:08:17 +0000 (18:08 +0000)]
[InstCombine] use m_OneUse to reduce code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303090
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Kostya Serebryany [Mon, 15 May 2017 17:39:42 +0000 (17:39 +0000)]
[libFuzzer] fix a warning from Wunreachable-code-loop-increment reported by Christian Holler. This also fixes a logical bug, which however does not affect the libFuzzer's ability too much (I wasn't able to create a differentiating test)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303087
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Kyle Butt [Mon, 15 May 2017 17:30:47 +0000 (17:30 +0000)]
CodeGen: BlockPlacement: Increase tail duplication size for O3.
At O3 we are more willing to increase size if we believe it will improve
performance. The current threshold for tail-duplication of 2 instructions is
conservative, and can be relaxed at O3.
Benchmark results:
llvm test-suite:
6% improvement in aha, due to duplication of loop latch
3% improvement in hexxagon
2% slowdown in lpbench. Seems related, but couldn't completely diagnose.
Internal google benchmark:
Produces 4% improvement on internal google protocol buffer serialization
benchmarks.
Differential-Revision: https://reviews.llvm.org/D32324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303084
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Simon Pilgrim [Mon, 15 May 2017 17:17:44 +0000 (17:17 +0000)]
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
Follow up to D33147
NVPTXTargetLowering::LowerCall was trusting the default argument values.
Fixes another 17 of the NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.
Differential Revision: https://reviews.llvm.org/D33189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303082
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Hans Wennborg [Mon, 15 May 2017 16:50:48 +0000 (16:50 +0000)]
build_llvm_package.bat: Minor updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303080
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Rafael Espindola [Mon, 15 May 2017 15:56:23 +0000 (15:56 +0000)]
Add an extra test for archive symbol tables.
The table should include only defined symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303075
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Simon Pilgrim [Mon, 15 May 2017 15:48:15 +0000 (15:48 +0000)]
[SLPVectorizer][X86] Add vectorization tests for vXi64/vXi32/vXi16/VXi8 add/sub/mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303074
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Florian Hahn [Mon, 15 May 2017 15:15:22 +0000 (15:15 +0000)]
[AArch64] Enable FeatureFuseAES on Cortex-A72.
This patch enables fusing dependent AESE/AESMC and AESD/AESIMC
instruction pairs on Cortex-A72, as recommended in the Software
Optimization Guide, section 4.10.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303073
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Dmitry Preobrazhensky [Mon, 15 May 2017 14:28:23 +0000 (14:28 +0000)]
[AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64
See bug 32936: https://bugs.llvm.org//show_bug.cgi?id=32936
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D33123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303070
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Simon Pilgrim [Mon, 15 May 2017 14:27:11 +0000 (14:27 +0000)]
[SLPVectorizer][X86] Add vectorization tests for vXi64/vXi32/vXi16/VXi8 shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303069
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Dinar Temirbulatov [Mon, 15 May 2017 13:14:04 +0000 (13:14 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303059
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Dmitry Preobrazhensky [Mon, 15 May 2017 12:37:03 +0000 (12:37 +0000)]
[AMDGPU][MC] Removed V_MQSAD_U16_U8
This instruction does not really exist
See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018
Reviewers: vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D33126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303055
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John Brawn [Mon, 15 May 2017 11:57:54 +0000 (11:57 +0000)]
[ARM] Mark LEApcrel instructions as isAsCheapAsAMove
Doing this means that if an LEApcrel is used in two places we will rematerialize
instead of generating two MOVs. This is particularly useful for printfs using
the same format string, where we want to generate an address into a register
that's going to get corrupted by the call.
Differential Revision: https://reviews.llvm.org/D32858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303054
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John Brawn [Mon, 15 May 2017 11:50:21 +0000 (11:50 +0000)]
[ARM] Mark LEApcrel as not having side effects
Doing this lets us hoist it out of loops, and I've also marked it as
rematerializable the same as the thumb1 and thumb2 counterparts.
It looks like it being marked as such was just a mistake, as the commit that
made that change only mentions LEApcrelJT and in thumb1 and thumb2 only the
LEApcrelJT instructions were marked as having side-effects, so it looks like
the intent was to only mark LEApcrelJT as having side-effects but LEApcrel was
accidentally marked as such also.
Differential Revision: https://reviews.llvm.org/D32857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303053
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George Rimar [Mon, 15 May 2017 11:45:28 +0000 (11:45 +0000)]
[DWARF] - Speedup handling of relocations in DWARFContextInMemory.
I am working on a speedup of building .gdb_index in LLD and
noticed that relocations that are proccessed in DWARFContextInMemory often uses
the same symbol in a row. This patch introduces caching to reduce the relocations
proccessing time.
For benchmark,
I took debug LLC binary objects configured with -ggnu-pubnames and linked it using LLD.
Link time without --gdb-index is about 4,45s.
Link time with --gdb-index: a) Without patch: 19,16s b) With patch: 15,52s
That means time spent on --gdb-index in this configuration is
19,16s - 4,45s = 14,71s (without patch) vs 15,52s - 4,45s = 11,07s (with patch).
Differential revision: https://reviews.llvm.org/D31136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303051
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Ayman Musa [Mon, 15 May 2017 11:30:54 +0000 (11:30 +0000)]
[X86] Relocate code of replacement of subtarget unsupported masked memory intrinsics to run also on -O0 option.
Currently, when masked load, store, gather or scatter intrinsics are used, we check in CodeGenPrepare pass if the subtarget support these intrinsics, if not we replace them with scalar code - this is a functional transformation not an optimization (not optional).
CodeGenPrepare pass does not run when the optimization level is set to CodeGenOpt::None (-O0).
Functional transformation should run with all optimization levels, so here I created a new pass which runs on all optimization levels and does no more than this transformation.
Differential Revision: https://reviews.llvm.org/D32487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303050
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Simon Pilgrim [Mon, 15 May 2017 10:47:48 +0000 (10:47 +0000)]
[NVPTX] Don't rely on default arguments to SelectionDAG::getMemIntrinsicNode. NFC.
NFC followup to D33147, this explicitly sets all the arguments (instead of relying on the defaults) to SelectionDAG::getMemIntrinsicNode to help identify -verify-machineinstrs issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303047
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Sam Kolton [Mon, 15 May 2017 10:13:07 +0000 (10:13 +0000)]
[TableGen] Add EncoderMethod to RegisterOperand
Reviewers: stoklund, grosbach, vpykhtin
Differential Revision: https://reviews.llvm.org/D32493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303044
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Tom Stellard [Mon, 15 May 2017 09:52:33 +0000 (09:52 +0000)]
[RegisterBankInfo] Remove overly-agressive asserts
Summary:
We were asserting in RegisterBankInfo if RBI.copyCost() returns
UINT_MAX. This is OK for RegBankSelect::Mode::Fast since we only
try one instruction mapping and can't recover from this, but for
RegBankSelect::Mode::Greedy we will be considering multiple
instruction mappings, so we can recover if we see a UNIT_MAX copy
cost.
The copy cost for one pair of register banks in the AMDGPU backend
will be UNIT_MAX, so this patch will prevent AMDGPU tests from
breaking.
Reviewers: ab, qcolombet, t.p.northover, dsanders
Reviewed By: qcolombet
Subscribers: tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D33144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303043
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Tom Stellard [Mon, 15 May 2017 09:34:23 +0000 (09:34 +0000)]
CMake: Fix docs-llvm-man target when clang+llvm is in the same source tree
Summary:
This was broken by r302499. Configuring with -DLLVM_BUILD_DOCS=ON would
cause the docs-llvm-man target not to be created.
Reviewers: anemet, beanz
Reviewed By: anemet
Subscribers: llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D33146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303042
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Arnaud A. de Grandmaison [Mon, 15 May 2017 08:43:27 +0000 (08:43 +0000)]
MCObjectStreamer : fail with a diagnostic when emitting an out of range value.
We were previously silently emitting bogus data in release mode,
making it very hard to diagnose the error, or crashing with an
assert in debug mode. A proper diagnostic is now always emitted
when the value to be emitted is out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303041
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Igor Breger [Mon, 15 May 2017 07:03:38 +0000 (07:03 +0000)]
[GlobalISel][X86] G_BR instruction select test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303036
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Craig Topper [Mon, 15 May 2017 06:39:41 +0000 (06:39 +0000)]
[ValueTracking] Replace all uses of ComputeSignBit with computeKnownBits.
This patch finishes off the conversion of ComputeSignBit to computeKnownBits.
Differential Revision: https://reviews.llvm.org/D33166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303035
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Daniel Jasper [Mon, 15 May 2017 04:58:27 +0000 (04:58 +0000)]
Add '#' to test regex that I forgot in r303025.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303034
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Craig Topper [Mon, 15 May 2017 04:40:19 +0000 (04:40 +0000)]
[ConstantRange] Fix what appear to be copy and paste mistakes in the unittest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303033
91177308-0d34-0410-b5e6-
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Sanjoy Das [Mon, 15 May 2017 04:22:09 +0000 (04:22 +0000)]
Move some code into ScalarEvolution.cpp; NFC
I need to add some asserts to these constructors that are easier to
add once they're in the .cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303032
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Craig Topper [Mon, 15 May 2017 02:44:08 +0000 (02:44 +0000)]
[InstCombine] Merge duplicate functionality between InstCombine and ValueTracking
Summary:
Merge overflow computation for signed add,
appearing both in InstCombine and ValueTracking.
As part of the merge,
cleanup the interface for overflow checks in InstCombine.
Patch by Yoav Ben-Shalom.
Reviewers: craig.topper, majnemer
Reviewed By: craig.topper
Subscribers: takuto.ikuta, llvm-commits
Differential Revision: https://reviews.llvm.org/D32946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303029
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Craig Topper [Mon, 15 May 2017 02:30:27 +0000 (02:30 +0000)]
[InstCombine] Remove 'return' of a called function that also returned void. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303028
91177308-0d34-0410-b5e6-
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Daniel Jasper [Sun, 14 May 2017 22:07:50 +0000 (22:07 +0000)]
Fix two tests that weren't correctly copied.
One didn't correctly fine the regex variable, the other still had a RUN
line for FNOBUILTIN-checks, which weren't copied to the file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303025
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Zvi Rackover [Sun, 14 May 2017 21:30:38 +0000 (21:30 +0000)]
[X86] Utilize SelectionDAG::getSelect(). NFC.
Replace SelectionDAG::getNode(ISD::SELECT, ...)
and SelectionDAG::getNode(ISD::VSELECT, ...)
with SelectionDAG::getSelect(...)
Saves a few lines of code and in some cases saves the need to explicitly
check the type of the desired node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303024
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Simon Pilgrim [Sun, 14 May 2017 20:52:11 +0000 (20:52 +0000)]
[X86][AVX1] Account for cost of extract/insert of 256-bit shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303023
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 14 May 2017 20:25:42 +0000 (20:25 +0000)]
[X86][AVX2] Fix costs for v4i64 ashr by splat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303022
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Sun, 14 May 2017 20:02:34 +0000 (20:02 +0000)]
[X86][AVX1] Account for cost of extract/insert of 256-bit shifts by splat
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303021
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 14 May 2017 19:38:11 +0000 (19:38 +0000)]
[X86] Add avx512vl command lines to the 128/256-bit vector-lzcnt tests so we can see what compare instructions are being used in the lookup table code.
I noticed the 512-bit lzcnts don't use the X86 specific lookup table code and instead use the EXPAND case in LegalizeDAG. I was toying around with fixing this and noticed it would require compare instructions that generate i1 masks and then converting from mask to vector. Then I noticed that we don't test which compares are used with avx512vl and no avx512cd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303020
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Craig Topper [Sun, 14 May 2017 19:38:09 +0000 (19:38 +0000)]
[X86] Cleanup some of the check-prefixes in the vector-lzcnt tests.
Remove an unneeded prefix from the 32-bit command line. Make all the 64-bit triples match. Replace ALL with X64 and remove it from the 32-bit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303019
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Craig Topper [Sun, 14 May 2017 19:38:06 +0000 (19:38 +0000)]
[X86] Remove unused value from IntrinsicType enum. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303018
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96231b3b80d8
Simon Pilgrim [Sun, 14 May 2017 18:52:15 +0000 (18:52 +0000)]
[X86][AVX1] Account for cost of extract/insert of 256-bit SDIV/UDIV by mul sequences
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303017
91177308-0d34-0410-b5e6-
96231b3b80d8