OSDN Git Service
Sjoerd Meijer [Wed, 5 Jun 2019 13:11:51 +0000 (13:11 +0000)]
[ARM] Allow "-march=foo+fp" to vary with foo
This is the LLVM part of this change, the Clang part contains the full
description in its commit message.
Differential Revision: https://reviews.llvm.org/D60697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362600
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 12:56:53 +0000 (12:56 +0000)]
[X86][AVX] combineX86ShuffleChain - combine shuffle(extractsubvector(x),extractsubvector(y))
We already handle the case where we combine shuffle(extractsubvector(x),extractsubvector(x)), this relaxes the requirement to permit different sources as long as they have the same value type.
This causes a couple of cases where the VPERMV3 binary shuffles occur at a wider width than before, which I intend to improve in future commits - but as only the subvector's mask indices are defined, these will broadcast so we don't see any increase in constant size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362599
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 5 Jun 2019 12:05:54 +0000 (12:05 +0000)]
gn build: Merge r362578
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362598
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Wed, 5 Jun 2019 11:37:53 +0000 (11:37 +0000)]
[llvm-objdump] - Disassemble non-executable sections if specifically requested.
This is https://bugs.llvm.org/show_bug.cgi?id=41897.
Previously -d + -j .data had no effect, that wasn't consistent with GNU,
which proccesses .data in that case. With this patch we follow this behavior.
Diffeential revision: https://reviews.llvm.org/D62848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362596
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 10:59:04 +0000 (10:59 +0000)]
[TargetLowering] SimplifyDemandedBits - pull out shift value type. NFCI.
Will be used more in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362595
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 10:55:55 +0000 (10:55 +0000)]
[X86][SSE] Add some nt-store test cases inspired by PR42123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362594
91177308-0d34-0410-b5e6-
96231b3b80d8
Serge Guelton [Wed, 5 Jun 2019 10:32:28 +0000 (10:32 +0000)]
Sanitize llvm-size help
Remove irrelevant options from standard help output.
New output:
OVERVIEW: llvm object size dumper
USAGE: llvm-size [options] <input files>
OPTIONS:
Generic Options:
--help - Display available options (--help-hidden for more)
--help-list - Display list of available options (--help-list-hidden for more)
--version - Display the version of this program
llvm-size Options:
Specify output format
-A - System V format
-B - Berkeley format
-m - Darwin -m format
--arch=<string> - architecture(s) from a Mach-O file to dump
--common - Print common symbols in the ELF file. When using Berkely format, this is added to bss.
Print size in radix:
-o - Print size in octal
-d - Print size in decimal
-x - Print size in hexadecimal
--format=<value> - Specify output format
=sysv - System V format
=berkeley - Berkeley format
=darwin - Darwin -m format
-l - When format is darwin, use long format to include addresses and offsets.
--radix=<value> - Print size in radix
=8 - Print size in octal
=10 - Print size in decimal
=16 - Print size in hexadecimal
--totals - Print totals of all objects - Berkeley format only
Differential Revision: https://reviews.llvm.org/D62482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362593
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 5 Jun 2019 10:04:05 +0000 (10:04 +0000)]
[IPO] Disabled 'default only' switch statements to fix MSVC warnings.
@jdoerfert Looks like these are placeholders for incoming abstract attributes patches so I've just commented the code out, even though this is usually frowned upon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362592
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Wed, 5 Jun 2019 08:58:00 +0000 (08:58 +0000)]
Include what you use in PPCFrameLowering.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362590
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Granitz [Wed, 5 Jun 2019 08:29:24 +0000 (08:29 +0000)]
[CMake] Export CMAKE_CONFIGURATION_TYPES for the LLVM build-tree
Summary: Useful info for standalone builds of subprojects. If a multi-configuration generator was used for the provided LLVM build-tree, standalone builds should consider actual subdirectories per configuration in `find_program()` (e.g. looking for `llvm-lit` or `llvm-tblgen`).
Reviewers: labath, beanz, mgorny
Subscribers: lldb-commits, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362588
91177308-0d34-0410-b5e6-
96231b3b80d8
Yevgeny Rouban [Wed, 5 Jun 2019 05:46:40 +0000 (05:46 +0000)]
Resubmit "[CorrelatedValuePropagation] Fix prof branch_weights metadata handling for SwitchInst"
This reverts commit
5b32f60ec31ce136edac6f693538aeb6039f4ad0.
The fix is in commit
4f9e68148bd0dada2d6997625432385918ac2e2c.
This patch fixes the CorrelatedValuePropagation pass to keep
prof branch_weights metadata of SwitchInst consistent.
It makes use of SwitchInstProfUpdateWrapper.
New tests are added.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D62126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362583
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Liao [Wed, 5 Jun 2019 04:18:12 +0000 (04:18 +0000)]
Suppress false-positive GCC -Wreturn-type warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362582
91177308-0d34-0410-b5e6-
96231b3b80d8
Rui Ueyama [Wed, 5 Jun 2019 03:04:46 +0000 (03:04 +0000)]
Read .note.gnu.property sections and emit a merged .note.gnu.property section.
This patch also adds `--require-cet` option for the sake of testing.
The actual feature for IBT-aware PLT is not included in this patch.
This is a part of https://reviews.llvm.org/D59780. Submitting this
first should make it easy to work with a related change
(https://reviews.llvm.org/D62609).
Differential Revision: https://reviews.llvm.org/D62853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362579
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Wed, 5 Jun 2019 03:02:24 +0000 (03:02 +0000)]
[Attributor] Pass infrastructure and fixpoint framework
NOTE: Note that no attributes are derived yet. This patch will not go in
alone but only with others that derive attributes. The framework is
split for review purposes.
This commit introduces the Attributor pass infrastructure and fixpoint
iteration framework. Further patches will introduce abstract attributes
into this framework.
In a nutshell, the Attributor will update instances of abstract
arguments until a fixpoint, or a "timeout", is reached. Communication
between the Attributor and the abstract attributes that are derived is
restricted to the AbstractState and AbstractAttribute interfaces.
Please see the file comment in Attributor.h for detailed information
including design decisions and typical use case. Also consider the class
documentation for Attributor, AbstractState, and AbstractAttribute.
Reviewers: chandlerc, homerdin, hfinkel, fedor.sergeev, sanjoy, spatel, nlopes, nicholas, reames
Subscribers: mehdi_amini, mgorny, hiraditya, bollu, steven_wu, dexonsmith, dang, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362578
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Wed, 5 Jun 2019 03:00:06 +0000 (03:00 +0000)]
[NFC][FnAttrs] Stress tests for attribute deduction
This commit is a preparation of upcoming patches on attribute deduction.
It will shorten the diffs and make it clear what we inferred before.
Reviewers: chandlerc, homerdin, hfinkel, fedor.sergeev, sanjoy, spatel, nlopes
Subscribers: bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362577
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 5 Jun 2019 02:36:40 +0000 (02:36 +0000)]
[PowerPC] Collapse RLDICL/RLDICR into RLDIC when possible
Generally speaking, we lower to an optimal rotate sequence for nodes visible in
the SDAG. However, there are instances where the two rotates are not visible at
ISEL time - most notably those in a very common sequence when lowering switch
statements to jump tables.
A common situation is a switch on a 32-bit integer. This value has to have the
upper 32 bits cleared and because jump table offsets are word offsets, the value
needs to be shifted left by 2 bits. We currently emit the clear and the left
shift as two separate instructions, but this is not needed as we can lower it to
a single RLDIC.
This patch just cleans that up.
Differential revision: https://reviews.llvm.org/D60402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362576
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 5 Jun 2019 02:09:03 +0000 (02:09 +0000)]
[PowerPC][NFC] Add codegen test for consecutive stores of vector elements
NFC commit of a test case in order for the subsequent review to show differences
in codegen.
Differential revision: https://reviews.llvm.org/D62843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362573
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Wed, 5 Jun 2019 01:36:48 +0000 (01:36 +0000)]
[llvm-objdump/llvm-readobj/obj2yaml/yaml2obj] Support DT_PPC_GOT and DT_PPC_OPT
In glibc, DT_PPC_GOT indicates that PowerPC32 Secure PLT ABI is used.
I plan to use it in D62464.
DT_PPC_OPT currently indicates if a TLSDESC inspired TLS optimization is
enabled.
Reviewed By: grimar, jhenderson, rupprecht
Differential Revision: https://reviews.llvm.org/D62851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362569
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 5 Jun 2019 01:31:43 +0000 (01:31 +0000)]
Initial support for IBM MASS vector library
This is the LLVM portion of patch https://reviews.llvm.org/D59881.
The clang portion is to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362568
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Desaulniers [Wed, 5 Jun 2019 01:28:55 +0000 (01:28 +0000)]
[TargetTransformInfo] assert on nullptr
Summary:
This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No.
38".
Add an assertion, since it's unlikely that this parameter is nullptr.
Reviewers: RKSimon, fhahn
Reviewed By: RKSimon
Subscribers: fhahn, llvm-commits, RKSimon, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362567
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 5 Jun 2019 01:00:34 +0000 (01:00 +0000)]
[X86] Cleanup convertIntLogicToFPLogic a little. NFCI
-Use early returns to reduce indentation
-Replace multipe ifs with a switch.
-Replace an assert with an llvm_unreachable default in the switch.
-Check that the FP type we're going to use for the
X86ISD::FAND/FOR/FXOR is legal rather than checking that the
integer type matches the width of a legal scalar fp type. This all
runs after legalization so it shouldn't really matter, but making
sure we're using a valid type in the X86ISD node is really
whats important.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362565
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 23:35:07 +0000 (23:35 +0000)]
svn propset svn:executable on utils/prepare-code-coverage-artifact.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362561
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Tue, 4 Jun 2019 23:11:42 +0000 (23:11 +0000)]
[AArch64] FastISel: fix test to specify -fast-isel when -fast-isel-abort=1 is used.
This test has been inadvertently been GISel, and now assert due to incompatible flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362559
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Tue, 4 Jun 2019 23:01:36 +0000 (23:01 +0000)]
[Scalarizer] Add UnaryOperator visitor to scalarization pass
Differential Revision: https://reviews.llvm.org/D62858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362558
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Brachet [Tue, 4 Jun 2019 22:17:27 +0000 (22:17 +0000)]
[test][llvm-objcopy] Test llvm-objcopy with standard streams
Differential Revision: https://reviews.llvm.org/D62817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362556
91177308-0d34-0410-b5e6-
96231b3b80d8
Amara Emerson [Tue, 4 Jun 2019 21:51:34 +0000 (21:51 +0000)]
[AArch64][GlobalISel] Make extloads to i64 legal.
Although we had the support in the prelegalizer combiner to generate the
G_SEXTLOAD or G_ZEXTLOAD ops, the legalizer definitions for arm64 had them as
lowering back to separate ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362553
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 21:47:50 +0000 (21:47 +0000)]
[X86] Add avx512bw to the avx512 machine-combiner-int-vec.ll to ensure we use zmm for v32i16/v64i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362552
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 21:26:46 +0000 (21:26 +0000)]
[X86] Add vector min/max reassociation tests to machine-combiner-int-vec.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362550
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 21:26:36 +0000 (21:26 +0000)]
[X86] Add 512-bit test cases to machine-combiner-int-vec.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362549
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Tue, 4 Jun 2019 21:08:20 +0000 (21:08 +0000)]
[WebAssembly] Fix ISel crash on sext_inreg/extract type mismatch
Summary:
Adjusts the index and adds a bitcast around the vector operand of
EXTRACT_VECTOR_ELT so that its lane type matches the source type of
its parent sext_inreg. Without this bitcast the ISel patterns do not
match and ISel fails.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362547
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Tue, 4 Jun 2019 20:34:43 +0000 (20:34 +0000)]
[SelectionDAG][FIX] Allow "returned" arguments to be bit-casted
Summary:
An argument that is return by a function but bit-casted before can still
be annotated as "returned". Make sure we do not crash for this case.
Reviewers: sunfish, stephenwlin, niravd, arsenm
Subscribers: wdng, hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362546
91177308-0d34-0410-b5e6-
96231b3b80d8
Johannes Doerfert [Tue, 4 Jun 2019 20:21:46 +0000 (20:21 +0000)]
Introduce Value::stripPointerCastsSameRepresentation
This patch allows current users of Value::stripPointerCasts() to force
the result of the function to have the same representation as the value
it was called on. This is useful in various cases, e.g., (non-)null
checks.
In this patch only a single call site was adjusted to fix an existing
misuse that would cause nonnull where they may be wrong. Uses in
attribute deduction and other areas, e.g., D60047, are to be expected.
For a discussion on this topic, please see [0].
[0] http://lists.llvm.org/pipermail/llvm-dev/2018-December/128423.html
Reviewers: hfinkel, arsenm, reames
Subscribers: wdng, hiraditya, bollu, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362545
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 19:10:08 +0000 (19:10 +0000)]
llvm-undname: Correctly demangle vararg parameters
FunctionSignatureNode already had an IsVariadic field,
but it wasn't used anywhere yet. Set it and use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362541
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 18:49:05 +0000 (18:49 +0000)]
llvm-undname: More coverage-related cleanups
- The loop in demangleFunctionParameterList() only exits
on Error, @, and Z. All 3 cases were handled, so the
rest of the function is DEMANGLE_UNREACHABLE.
- The loop in demangleTemplateParameterList() always returns
on Error, so there's no need to check for that in the loop
header and after the loop.
- Add test cases for invalid function parameter manglings.
- Add a (redundant) test case for a simple template parameter
list mangling.
- Add a test case pointing out that varargs functions aren't
demangled correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362540
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Tue, 4 Jun 2019 18:48:43 +0000 (18:48 +0000)]
Revert r362472 as it is breaking PPC build bots
The patch https://reviews.llvm.org/rL362472 broke PPC LNT buildbots.
Reverting it to bring the bots back to green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362539
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Tue, 4 Jun 2019 18:45:15 +0000 (18:45 +0000)]
[Utils] Clean another duplicated util method.
Summary:
Following the cleanup in D48202, method foldBlockIntoPredecessor has the
same behavior. Replace its uses with MergeBlockIntoPredecessor.
Remove foldBlockIntoPredecessor.
Reviewers: chandlerc, dmgreen
Subscribers: jlebar, javed.absar, zzheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362538
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 18:06:28 +0000 (18:06 +0000)]
llvm-undname: Add test coverage for demangleInitFiniStub()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362536
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 18:03:07 +0000 (18:03 +0000)]
[X86] Mutate fceil/ffloor/ftrunc/fnearbyint/frint into X86ISD::RNDSCALE during PreProcessIselDAG to cut down on pattern permutations
We already need to have patterns for X86ISD::RNDSCALE to support software intrinsics. But we currently have 5 sets of patterns for the 5 rounding operations. For of these 6 patterns we have to support 3 vectors widths, 2 element sizes, sse/vex/evex encodings, load folding, and broadcast load folding. This results in a fair amount of bytes in the isel table.
This patch adds code to PreProcessIselDAG to morph the fceil/ffloor/ftrunc/fnearbyint/frint to X86ISD::RNDSCALE. This way we can remove everything, but the intrinsic pattern while still allowing the operations to be considered Legal for DAGCombine and Legalization. This shrinks the DAGISel by somewhere between 9K and 10K.
There is one complication to this, the STRICT versions of these nodes are currently mutated to their none strict equivalents at isel time when the node is visited. This won't be true in the future since that loses the chain ordering information. For now I've also added support for the non-STRICT nodes to Select so we can change the STRICT versions there after they've been mutated to their non-STRICT versions. We'll probably need a STRICT version of RNDSCALE or something to handle this in the future. Which will take us back to needing 2 sets of patterns for strict and non-strict, but that's still better than the 11 or 12 sets of patterns we'd need.
We can probably do something similar for scalar, but I haven't looked at it yet.
Differential Revision: https://reviews.llvm.org/D62757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362535
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Tue, 4 Jun 2019 18:01:07 +0000 (18:01 +0000)]
[X86] Fold single-use variable into assert. NFC.
Avoids an unused variable warning in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362534
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 4 Jun 2019 17:44:18 +0000 (17:44 +0000)]
[DAGCombiner][X86] Fold (not (neg X)) -> (add X, -1)
This is a special case of a more general transform (not (sub Y, X)) -> (add X, ~Y). InstCombine knows the general form. I've restricted to the special case to fix the motivating case PR42118. I tried handling any case where Y was constant, but got some changes on some Mips tests that I couldn't quickly prove where beneficial.
Fixes PR42118
Differential Revision: https://reviews.llvm.org/D62828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362533
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 4 Jun 2019 17:29:55 +0000 (17:29 +0000)]
[Tests] Autogen a test so future changes are visible
Oddly, I had to change a value name from "tmp0" to "bc0" to get the autogened test to pass. I'm putting this down to an oddity of update_test_checks or FileCheck, but don't understand it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362532
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 17:05:34 +0000 (17:05 +0000)]
[NFC][Codegen][PowerPC] Autogenerate shift-cmp.ll test
Being affected by upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362529
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 17:05:06 +0000 (17:05 +0000)]
[NFC][Codegen][AMDGPU] Autogenerate commute-shifts.ll test
Being affected by upcoming patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362528
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Brachet [Tue, 4 Jun 2019 16:55:30 +0000 (16:55 +0000)]
[MACHO] Replaced calls to getStruct with getStructOrErr in functions returning Error or Expected or similar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362526
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 4 Jun 2019 16:40:04 +0000 (16:40 +0000)]
[x86] split 256-bit store of concatenated vectors
This shows up as a side issue to the main problem for the AVX target example from PR37428:
https://bugs.llvm.org/show_bug.cgi?id=37428 - https://godbolt.org/z/7tpRa3
But as we can see in the pile of existing test diffs, it's actually a widespread problem
that affects any AVX or later target. Apart from a couple of oddballs, I think these are
all improvements for the reasons stated in the code comment: we do not want to enable YMM
unnecessarily (avoid vzeroupper and frequency throttling) and some cores split 256-bit
stores anyway.
We could say that MergeConsecutiveStores() is going overboard on some of these examples,
but that won't solve the problem completely. But that is a reason I'm proposing this as
a lowering rather than a combine: we will infinite loop fighting the merge code if we try
this earlier.
Differential Revision: https://reviews.llvm.org/D62498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362524
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Smith [Tue, 4 Jun 2019 16:35:40 +0000 (16:35 +0000)]
[AArch64][ELF] Add support for PLT decoding with BTI instructions present
Arm Architecture v8.5a introduces Branch Target Identification (BTI). When
enabled all indirect branches must target a bti instruction of the
appropriate form. As PLT sequences may sometimes be the target of an
indirect branch and PLT[0] always is, a static linker may need to generate
PLT sequences that contain "bti c" as the first instruction. In effect:
bti c
adrp x16, page offset to .got.plt
...
Instead of:
adrp x16, page offset to .got.plt
...
At present the PLT decoding assumes the adrp will always be the first
instruction. This patch adds support for a single "bti c" to prefix it. A
test binary has been uploaded with such a PLT sequence. A forthcoming LLD
patch will make heavy use of the PLT decoding code.
Differential Revision: https://reviews.llvm.org/D62598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362523
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 16:25:28 +0000 (16:25 +0000)]
llvm-undname: Yet more coverage for error paths
- For error returns in demangleSpecialTableNode(),
demangleLocalStaticGuard(), RTTITypeDescriptor,
demangleRttiBaseClassDescriptorNode(), demangleUnsigned(),
demangleUntypedVariable() (via RttiBaseClassArray)
- For ?_A and ?_P which are handled at early levels of the
demangler but are not implemented in a later stage; this
is now more obvious
- Replace a "default:" with an explicit list of cases, to
get -Wswitch check we list all cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362520
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikita Popov [Tue, 4 Jun 2019 16:24:09 +0000 (16:24 +0000)]
[LVI][CVP] Add support for urem, srem and sdiv
The underlying ConstantRange functionality has been added in D60952,
D61207 and D61238, this just exposes it for LVI.
I'm switching the code from using a whitelist to a blacklist, as
we're down to one unsupported operation here (xor) and writing it
this way seems more obvious :)
Differential Revision: https://reviews.llvm.org/D62822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362519
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 4 Jun 2019 16:19:34 +0000 (16:19 +0000)]
[Tests] Update a test to consistently use new pass manager and FileCheck the result
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362518
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Tue, 4 Jun 2019 16:15:19 +0000 (16:15 +0000)]
[Tests] Autogen tests so that diffs for a future change are understandable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362516
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 15:47:25 +0000 (15:47 +0000)]
llvm-undname: Add coverage for startsWithLocalScopePattern()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362515
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 15:38:00 +0000 (15:38 +0000)]
llvm-undname: More no-op changes to increase test coverage
- Add test coverage around invalid anon namespaces and
for error paths in demanglePrimitiveType() and in
demangleFullyQualifiedTypeName()
- Use DEMANGLE_UNREACHABLE in two more unreachable places
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362514
91177308-0d34-0410-b5e6-
96231b3b80d8
James Henderson [Tue, 4 Jun 2019 15:34:58 +0000 (15:34 +0000)]
[llvm-symbolizer] Flush output on bad input
One way of using llvm-symbolizer is to interactively within a process
write a line from a parent process to llvm-symbolizer's stdin, and then
read the output, then write the next line, read, etc. This worked as
long as all the lines were good. However, this didn't work prior to this
patch if any of the inputs were bad inputs, because the output is not
flushed after a bad input, meaning the parent process is sat waiting for
output, whilst llvm-symbolizer is sat waiting for input. This patch
flushes the output after every invocation of symbolizeInput when reading
from stdin. It also removes unnecessary flushing when llvm-symbolizer is
not reading addresses from stdin, which should give a slight performance
boost in these situations.
Reviewed by: ikudrin
Differential Revision: https://reviews.llvm.org/D62371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362511
91177308-0d34-0410-b5e6-
96231b3b80d8
Jinsong Ji [Tue, 4 Jun 2019 15:22:23 +0000 (15:22 +0000)]
[PowerPC] P9 Scheduling Model: dispatching rule fixes
This is to address some of the problems in existing P9 resource modeling,
especially about the dispatching rules.
Instead of using a hypothetical DISPATCHER , we try to use the number of
actual dispatch slots, and define SchedWriteRes to model dispatch rules,
then update instruction classes according to dispatch rules.
All the dispatch rules and instruction classes update are made according
to POWER9 User Manual.
Differential Revision: https://reviews.llvm.org/D61873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362509
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 4 Jun 2019 15:15:59 +0000 (15:15 +0000)]
[SelectionDAG][x86] limit post-legalization store merging by type
The proposal in D62498 showed that x86 would benefit from vector
store splitting, but that may conflict with the generic DAG
combiner's store merging transforms.
Add memory type to the existing TLI hook that enables the merging
transforms, so we can limit those changes to scalars only for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362507
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 15:13:30 +0000 (15:13 +0000)]
llvm-undname: Several behavior-preserving changes to increase coverage
- Replace `Error = true` in a few branches that are truly unreachable
with DEMANGLE_UNREACHABLE
- Remove early return early in startsWithLocalScopePattern() because
it's redundant with the next two early returns
- Remove unreachable `case '0'` (it's handled in the branch below)
- Remove an unused bool return
- Add test coverage for several early error returns, mostly in
array type parsing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362506
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 4 Jun 2019 15:02:33 +0000 (15:02 +0000)]
[X86][SSE] Pulled out (sub (xor X, M), M) 'ConditionalNegate' out pattern match code. NFCI.
As discussed on D62777 - we should be able to use this in more SSE41+ cases as well but that requires us to separate it from the OR(AND(),ANDN()) matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362504
91177308-0d34-0410-b5e6-
96231b3b80d8
Shawn Landden [Tue, 4 Jun 2019 14:51:15 +0000 (14:51 +0000)]
[Support] make countLeadingZeros() countTrailingZeros() countLeadingOnes() and countTrailingOnes() return unsigned
This matches APInt's versions of these functions, and there is no need for these to be size_t.
(as well as __builtin_clzll())
Differential Revision: https://reviews.llvm.org/D60823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362503
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 4 Jun 2019 14:40:37 +0000 (14:40 +0000)]
[x86] add test for store merging/splitting; NFC
This is a reduction of a test that would infinite loop with D62498.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362502
91177308-0d34-0410-b5e6-
96231b3b80d8
Shawn Landden [Tue, 4 Jun 2019 14:32:52 +0000 (14:32 +0000)]
[SimplifyCFG] fix last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362501
91177308-0d34-0410-b5e6-
96231b3b80d8
Shawn Landden [Tue, 4 Jun 2019 14:17:46 +0000 (14:17 +0000)]
[SimplifyCFG] NFC; remove bogus test case
Even if one bit is defined, the code is not clear what it is suppose to do.
The test wants to assert that some bits are undef, but that's not what the IR does and I don't think it's even possible to do that in any meaningful way. It was added in D12497, so @reames might want to double check.
Differential Revision: https://reviews.llvm.org/D60859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362499
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 4 Jun 2019 13:42:45 +0000 (13:42 +0000)]
gn build: Merge r362459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362498
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Tue, 4 Jun 2019 12:55:00 +0000 (12:55 +0000)]
Include what you use in PPCRegisterInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362495
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 11:44:50 +0000 (11:44 +0000)]
[NFC][Codegen] D62818 - also add tests with X being constant
For X86, these may be a 'BT' pattern, and in general, can cause
the transform to deadlock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362494
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Smith [Tue, 4 Jun 2019 11:44:33 +0000 (11:44 +0000)]
[AArch64][ELF][llvm-readobj] Add support for BTI and PAC dynamic tags
ELF for the 64-bit Arm Architecture defines two processor-specific dynamic
tags:
DT_AARCH64_BTI_PLT 0x70000001, d_val
DT_AARCH64_PAC_PLT 0x70000003, d_val
These presence of these tags indicate that PLT sequences have been
protected using Branch Target Identification and Pointer Authentication
respectively. The presence of both indicates that the PLT sequences have
been protected with both Branch Target Identification and Pointer
Authentication.
This patch adds the tags and tests for llvm-readobj and yaml2obj.
As some of the processor specific dynamic tags overlap, this patch splits
them up, keeping their original default value if they were not previously
mentioned explicitly in a switch case.
Differential Revision: https://reviews.llvm.org/D62596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362493
91177308-0d34-0410-b5e6-
96231b3b80d8
David Zarzycki [Tue, 4 Jun 2019 11:33:49 +0000 (11:33 +0000)]
Unbreak my hasty "unbreak" cmake fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362492
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Smith [Tue, 4 Jun 2019 11:28:22 +0000 (11:28 +0000)]
[AARCH64][ELF][llvm-readobj] Support for AArch64 .note.gnu.property
ELF for the 64-bit Arm Architecture defines a processor specific property
type GNU_PROPERTY_AARCH64_FEATURE_1_AND as GNU_PROPERTY_LOPROC. This
property works in a similar way to the existing X86 processor specific
property GNU_PROPERTY_GNU_X86_FEATURE_1_AND.
Two feature bits are defined for GNU_PROPERTY_AARCH64_FEATURE_1_AND:
- GNU_PROPERTY_AARCH64_FEATURE_1_BTI 0x1
- GNU_PROPERTY_AARCH64_FEATURE_1_PAC 0x2
This patch defines the property, feature bits and implements support for
printing in llvm-readobj.
Differential Revision: https://reviews.llvm.org/D62595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362490
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 11:06:21 +0000 (11:06 +0000)]
[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
Summary:
This *might* be the last fold for `sink-addsub-of-const.ll`, but i'm not sure yet.
As far as i can tell, there are no regressions here (ignoring x86-32),
all changes are either good or neutral.
This, almost surprisingly to me, fixes the motivational tests (in `shift-amount-mod.ll`)
`@reg32_lshr_by_sub_from_negated` from [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]].
https://rise4fun.com/Alive/vMd3
Reviewers: RKSimon, t.p.northover, craig.topper, spatel, efriedma
Reviewed By: RKSimon
Subscribers: sdardis, javed.absar, arichardson, kristof.beyls, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362488
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Tue, 4 Jun 2019 11:06:08 +0000 (11:06 +0000)]
[DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold
Summary:
All changes except ARM look **great**.
https://rise4fun.com/Alive/R2M
The regression `test/CodeGen/ARM/addsubcarry-promotion.ll`
is recovered fully by D62392 + D62450.
Reviewers: RKSimon, craig.topper, spatel, rogfer01, efriedma
Reviewed By: efriedma
Subscribers: dmgreen, javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362487
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 4 Jun 2019 10:49:06 +0000 (10:49 +0000)]
[SelectionDAG] ComputeNumSignBits - support constant pool values from target
As I mentioned on D61887 we don't get many hits on ComputeNumSignBits as we did on computeKnownBits.
The case we do get is interesting though - it allows us to use the 'ConditionalNegate' combine in combineLogicBlendIntoPBLENDV to remove a select.
It comes too late for SSE41 (BLENDV) cases, but SSE2 tests can hit it now. We should probably try to make use of this for SSE41+ targets as well - avoiding variable blends is usually a good idea. I'll investigate as a followup.
Differential Revision: https://reviews.llvm.org/D62777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362486
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 4 Jun 2019 10:17:56 +0000 (10:17 +0000)]
[SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD comments. NFCI.
Pre-commit requested for D62777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362485
91177308-0d34-0410-b5e6-
96231b3b80d8
Owen Reynolds [Tue, 4 Jun 2019 10:13:03 +0000 (10:13 +0000)]
[llvm-ar] Reapply Fix relative thin archive path handling
Includes a fix for an introduced build failure due to a post c++11 use of std::mismatch.
This fixes some thin archive relative path issues, paths are shortened where possible and paths are output correctly when using the display table command.
Differential Revision: https://reviews.llvm.org/D59491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362484
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 4 Jun 2019 10:04:55 +0000 (10:04 +0000)]
[SelectionDAG] Add fpto[us]i(undef) --> undef constant fold
Follow up to D62807.
Differential Revision: https://reviews.llvm.org/D62811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362483
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikhail Maltsev [Tue, 4 Jun 2019 09:39:55 +0000 (09:39 +0000)]
[ARM] Add FP16 vector insert/extract patterns
This change adds two FP16 extraction and two insertion patterns
(one per possible vector length).
Extractions are handled by copying a Q/D register into one of VFP2
class registers, where single FP32 sub-registers can be accessed. Then
the extraction of even lanes are simple sub-register extractions
(because we don't care about the top parts of registers for FP16
operations). Odd lanes need an additional VMOVX instruction.
Unfortunately, insertions cannot be handled in the same way, because:
* There is no instruction to insert FP16 into an even lane (VINS only
works with odd lanes)
* The patterns for odd lanes will have a form of a DAG (not a tree),
and will not be implementable in pure tablegen
Because of this insertions are handled in the same way as 16-bit
integer insertions (with conversions between FP registers and GPRs
using VMOVHR instructions).
Without these patterns the ARM backend would sometimes fail during
instruction selection.
This patch also adds patterns which combine:
* an FP16 element extraction and a store into a single VST1
instruction
* an FP16 load and insertion into a single VLD1 instruction
Differential Revision: https://reviews.llvm.org/D62651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362482
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Tue, 4 Jun 2019 09:31:07 +0000 (09:31 +0000)]
Silenced a warning "implicit conversion turns string literal into bool" introduced in r362473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362480
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Tue, 4 Jun 2019 09:16:35 +0000 (09:16 +0000)]
Include what you use in PPC.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362477
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Tue, 4 Jun 2019 09:16:31 +0000 (09:16 +0000)]
Include what you use in PPCMachineScheduler.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362476
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Tue, 4 Jun 2019 09:13:08 +0000 (09:13 +0000)]
Include what you use in PPCRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362475
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Tue, 4 Jun 2019 09:04:53 +0000 (09:04 +0000)]
[HWASAN][CMake] Allow instrumenting LLVM/clang
Differential revision: https://reviews.llvm.org/D62813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362474
91177308-0d34-0410-b5e6-
96231b3b80d8
Yevgeny Rouban [Tue, 4 Jun 2019 09:03:39 +0000 (09:03 +0000)]
Make SwitchInstProfUpdateWrapper safer
While prof branch_weights inconsistencies are being fixed patch
by patch (pass by pass) we need SwitchInstProfUpdateWrapper to
be safe with respect to inconsistent metadata that can come from
passes that have not been fixed yet. See the bug found by @nikic
in https://reviews.llvm.org/D62126.
This patch introduces one more state (called Invalid) to the
wrapper class that allows users to work with the underlying
SwitchInst ignoring the prof metadata changes.
Created a unit test for the SwitchInstProfUpdateWrapper class.
Reviewers: davidx, nikic, eraman, reames, chandlerc
Reviewed By: davidx
Differential Revision: https://reviews.llvm.org/D62656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362473
91177308-0d34-0410-b5e6-
96231b3b80d8
QingShan Zhang [Tue, 4 Jun 2019 08:53:53 +0000 (08:53 +0000)]
[DAGCombine] Match a pattern where a wide type scalar value is stored by several narrow stores
This opportunity is found from spec 2017 557.xz_r. And it is used by the sha encrypt/decrypt. See sha-2/sha512.c
static void store64(u64 x, unsigned char* y)
{
for(int i = 0; i != 8; ++i)
y[i] = (x >> ((7-i) * 8)) & 255;
}
static u64 load64(const unsigned char* y)
{
u64 res = 0;
for(int i = 0; i != 8; ++i)
res |= (u64)(y[i]) << ((7-i) * 8);
return res;
}
The load64 has been implemented by https://reviews.llvm.org/D26149
This patch is trying to implement the store pattern.
Match a pattern where a wide type scalar value is stored by several narrow
stores. Fold it into a single store or a BSWAP and a store if the targets
supports it.
Assuming little endian target:
i8 *p = ...
i32 val = ...
p[0] = (val >> 0) & 0xFF;
p[1] = (val >> 8) & 0xFF;
p[2] = (val >> 16) & 0xFF;
p[3] = (val >> 24) & 0xFF;
>
*((i32)p) = val;
i8 *p = ...
i32 val = ...
p[0] = (val >> 24) & 0xFF;
p[1] = (val >> 16) & 0xFF;
p[2] = (val >> 8) & 0xFF;
p[3] = (val >> 0) & 0xFF;
>
*((i32)p) = BSWAP(val);
Differential Revision: https://reviews.llvm.org/D61843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362472
91177308-0d34-0410-b5e6-
96231b3b80d8
QingShan Zhang [Tue, 4 Jun 2019 08:45:07 +0000 (08:45 +0000)]
[NFC] Update the test to check the endianness after the CodeGenPrepare instead of checking the assembly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362471
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Tatham [Tue, 4 Jun 2019 08:28:48 +0000 (08:28 +0000)]
[ARM] Turn some undefined encoding bits into 0s.
The family of 32-bit Thumb instruction encodings that include t2ORR,
t2AND and t2EOR are all listed in the ArmARM as having (0) in bit 15.
The Tablegen descriptions of those instructions listed them as ?. This
change tightens that up by making them into 0 + Unpredictable.
In the specific case of t2ORR, we tighten it up still further by
making the zero bit mandatory. This change comes from Arm v8.1-M, in
which encodings with that bit equal to 1 will now be used for
different instructions.
Reviewers: dmgreen, samparker, SjoerdMeijer, efriedma
Reviewed By: dmgreen, efriedma
Subscribers: efriedma, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362470
91177308-0d34-0410-b5e6-
96231b3b80d8
Chen Zheng [Tue, 4 Jun 2019 06:48:14 +0000 (06:48 +0000)]
[PowerPC] add testcases for reordering LSR and PPCCTRLoops - NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362468
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Mon, 3 Jun 2019 23:00:51 +0000 (23:00 +0000)]
[NFC][X86] Fixup FileCheck prefixes - drop duplicates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362460
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 3 Jun 2019 22:34:15 +0000 (22:34 +0000)]
[X86] Add test cases for 32 and 64 bit versions of PR42118. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362457
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Mon, 3 Jun 2019 22:30:18 +0000 (22:30 +0000)]
[NFC][Codegen] Add tests for hoisting and-by-const from "logical shift", when then eq-comparing with 0
This was initially reported as: https://reviews.llvm.org/D62818
https://rise4fun.com/Alive/oPH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362455
91177308-0d34-0410-b5e6-
96231b3b80d8
Jason Liu [Mon, 3 Jun 2019 22:22:03 +0000 (22:22 +0000)]
Fix DWARF DebugInfo unit test errors when cross-compiling
Summary:
When building with a Default Target set we can experience issues
in the DWARF DebugInfo unit tests because:
They assume we can generate object files for the host platform.
Some tests assume the endianess of the target we are generating
DWARF for and the host match.
This patch correct these issues by ensuring the tests which
generate objects in memory are run with respect to
LVM_DEFAULT_TARGET_TRIPLE and it's endianess.
We also make sure we don't use the hosts address size for line test
and split the triple util function in DwarfUtils into a version
that takes an address size and one that doesn't.
See also for discussion:
http://lists.llvm.org/pipermail/llvm-dev/2019-March/131212.html
Patch by: daltenty
Differential Revision: https://reviews.llvm.org/D62084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362454
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 3 Jun 2019 22:14:54 +0000 (22:14 +0000)]
Revert r362451 "foo" and r362452 "[X86] Add test cases for 32 and 64 bit versions of PR42118. NFC"
I failed to squash these properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362453
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 3 Jun 2019 22:11:40 +0000 (22:11 +0000)]
[X86] Add test cases for 32 and 64 bit versions of PR42118. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362452
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 3 Jun 2019 22:11:30 +0000 (22:11 +0000)]
foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362451
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Mon, 3 Jun 2019 22:02:48 +0000 (22:02 +0000)]
[ORC] Use uint8_t for bitfields in SymbolTableEntry.
This allows for better struct packing on MSVC, and as a bonus will eliminate a
warning on GCC builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362450
91177308-0d34-0410-b5e6-
96231b3b80d8
Cameron McInally [Mon, 3 Jun 2019 21:53:56 +0000 (21:53 +0000)]
[SCCP] Add UnaryOperator visitor to SCCP for unary FNeg
Differential Revision: https://reviews.llvm.org/D62819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362449
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Berg [Mon, 3 Jun 2019 21:53:26 +0000 (21:53 +0000)]
Propagate fmf for setcc in SDAG for select folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362448
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 3 Jun 2019 21:33:22 +0000 (21:33 +0000)]
AMDGPU: Disable stack realignment for kernels
This is something of a workaround, and the state of stack realignment
controls is kind of a mess. Ideally, we would be able to specify the
stack is infinitely aligned on entry to a kernel.
TargetFrameLowering provides multiple controls which apply at
different points. The StackRealignable field is used during
SelectionDAG, and for some reason distinct from this
hook. StackAlignment is a single field not dependent on the
function. It would probably be better to make that dependent on the
calling convention, and the maximum value for kernels.
Currently this doesn't really change anything, since the frame
lowering mostly does its own thing. This helps avoid regressions in a
future change which will rely more heavily on hasFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362447
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Mon, 3 Jun 2019 20:47:20 +0000 (20:47 +0000)]
[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT is fp
Instead of emitting all of the test stuff for a compare when it's only used by
a select, instead, just emit the compare + select. The select will use the
value of NZCV correctly, so we don't need to emit all of the test instructions
etc.
For now, only support fp selects which use G_FCMP. Also only support condition
codes which will only require one select to represent.
Also add a test.
Differential Revision: https://reviews.llvm.org/D62695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362446
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Mon, 3 Jun 2019 20:40:07 +0000 (20:40 +0000)]
gn build: Merge r361896.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362445
91177308-0d34-0410-b5e6-
96231b3b80d8
George Burgess IV [Mon, 3 Jun 2019 19:56:22 +0000 (19:56 +0000)]
CFLAA: reflow comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362442
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 3 Jun 2019 19:35:52 +0000 (19:35 +0000)]
[CFLGraph] Add FAdd to visitConstantExpr.
This looks like an oversight as all the other binary operators are present.
Accidentally noticed while auditing places that need FNeg handling.
No test because as noted in the review it would be contrived and amount to "don't crash"
Differential Revision: https://reviews.llvm.org/D62790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362441
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 3 Jun 2019 19:29:14 +0000 (19:29 +0000)]
[X86] Fix the pattern for merge masked vcvtps2pd.
r362199 fixed it for zero masking, but not zero masking. The load
folding in the peephole pass hid the bug. This patch turns off
the peephole pass on the relevant test to ensure coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362440
91177308-0d34-0410-b5e6-
96231b3b80d8