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Bjorn Helgaas [Thu, 7 Sep 2017 18:24:20 +0000 (13:24 -0500)]
Merge branch 'pci/trivial' into next
* pci/trivial:
PCI: Fix typos and whitespace errors
PCI: Remove unused "res" variable from pci_resource_io()
PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:19 +0000 (13:24 -0500)]
Merge branch 'pci/resource' into next
* pci/resource:
microblaze/PCI: Remove pcibios_setup_bus_{self/devices} dead code
ARC: Remove empty kernel/pcibios.c
PCI: Add a generic weak pcibios_align_resource()
PCI: Add a generic weak pcibios_fixup_bus()
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:18 +0000 (13:24 -0500)]
Merge branch 'pci/pm' into next
* pci/pm:
PCI/PM: Expand description of pci_set_power_state()
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:18 +0000 (13:24 -0500)]
Merge branch 'pci/msi' into next
* pci/msi:
PCI/MSI: Assume MSIs use real Requester ID, not an alias
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:16 +0000 (13:24 -0500)]
Merge branch 'pci/misc' into next
* pci/misc:
PCI: Fix PCIe capability sizes
PCI: Convert to using %pOF instead of full_name()
PCI: Constify endpoint pci_epf_type device_type
PCI: Constify bin_attribute structures
PCI: Constify hotplug pci_device_id structures
PCI: Constify hotplug attribute_group structures
PCI: Constify label attribute_group structures
PCI: Constify sysfs attribute_group structures
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:16 +0000 (13:24 -0500)]
Merge branch 'pci/irq-fixups' into next
* pci/irq-fixups:
PCI: Inline and remove pcibios_update_irq()
PCI: Remove unused pci_fixup_irqs() function
sparc/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
unicore32/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
tile/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
MIPS: PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
m68k/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
sh/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks
sh/PCI: Remove __init optimisations from IRQ mapping functions/data
MIPS: PCI: Fix pcibios_scan_bus() NULL check code path
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:15 +0000 (13:24 -0500)]
Merge branch 'pci/hotplug' into next
* pci/hotplug:
PCI: pciehp: Report power fault only once until we clear it
PCI: shpchp: Enable bridge bus mastering if MSI is enabled
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:14 +0000 (13:24 -0500)]
Merge branch 'pci/enumeration' into next
* pci/enumeration:
PCI: Warn periodically while waiting for non-CRS ("device ready") status
PCI: Wait up to 60 seconds for device to become ready after FLR
PCI: Factor out pci_bus_wait_crs()
PCI: Add pci_bus_crs_vendor_id() to detect CRS response data
PCI: Always check for non-CRS response before timeout
PCI: Avoid race while enabling upstream bridges
PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:13 +0000 (13:24 -0500)]
Merge branch 'pci/dpc' into next
* pci/dpc:
PCI/DPC: Add local struct device pointers
PCI/DPC: Add eDPC support
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:12 +0000 (13:24 -0500)]
Merge branch 'pci/aer' into next
* pci/aer:
PCI/AER: Reformat AER register definitions
PCI/portdrv: Move error handler methods to struct pcie_port_service_driver
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:11 +0000 (13:24 -0500)]
Merge branch 'pci/endpoint' into next
* pci/endpoint:
tools: PCI: Add a missing option help line
misc: pci_endpoint_test: Enable/Disable MSI using module param
misc: pci_endpoint_test: Avoid using hard-coded BAR sizes
misc: pci_endpoint_test: Add support to not enable MSI interrupts
misc: pci_endpoint_test: Add support to provide aligned buffer addresses
misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR
PCI: designware-ep: Do not disable BARs during initialization
PCI: dra7xx: Reset all BARs during initialization
PCI: dwc: designware: Provide page_size to pci_epc_mem
PCI: endpoint: Remove the ->remove() callback
PCI: endpoint: Add support to poll early for host commands
PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs
PCI: endpoint: Do not reset *command* inadvertently
PCI: endpoint: Add "volatile" to pci_epf_test_reg
PCI: endpoint: Add support for configurable page size
PCI: endpoint: Make ->remove() callback optional
PCI: endpoint: Add an API to get matching "pci_epf_device_id"
PCI: endpoint: Use of_dma_configure() to set initial DMA mask
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:11 +0000 (13:24 -0500)]
Merge branch 'pci/host-xilinx' into next
* pci/host-xilinx:
PCI: xilinx-nwl: Fix platform_get_irq() error handling
PCI: xilinx: Allow build on MIPS platforms
PCI: xilinx: Don't enable config completion interrupts
PCI: xilinx: Unify INTx & MSI interrupt decode
PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3
PCI: xilinx: Translate INTx range to hwirqs 0-3
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:10 +0000 (13:24 -0500)]
Merge branch 'pci/host-xgene' into next
* pci/host-xgene:
PCI: xgene: Clean up whitespace
PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset
PCI: xgene: Fix platform_get_irq() error handling
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:09 +0000 (13:24 -0500)]
Merge branch 'pci/host-vmd' into next
* pci/host-vmd:
iommu/vt-d: Prevent VMD child devices from being remapping targets
x86/PCI: Use is_vmd() rather than relying on the domain number
x86/PCI: Move VMD quirk to x86 fixups
MAINTAINERS: Add Jonathan Derrick as VMD maintainer
PCI: vmd: Remove IRQ affinity so we can allocate more IRQs
PCI: vmd: Free up IRQs on suspend path
PCI: vmd: Assign vector zero to all bridges
PCI: vmd: Reserve IRQ pre-vector for better affinity
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:08 +0000 (13:24 -0500)]
Merge branch 'pci/host-tegra' into next
* pci/host-tegra:
PCI: tegra: Explicitly request exclusive reset control
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:07 +0000 (13:24 -0500)]
Merge branch 'pci/host-spear13xx' into next
* pci/host-spear13xx:
PCI: spear13xx: Fix platform_get_irq() error handling
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:07 +0000 (13:24 -0500)]
Merge branch 'pci/host-rockchip' into next
* pci/host-rockchip:
PCI: rockchip: Fix platform_get_irq() error handling
PCI: rockchip: Umap IO space if probe fails
PCI: rockchip: Remove IRQ domain if probe fails
PCI: rockchip: Disable vpcie0v9 if resume_noirq fails
PCI: rockchip: Clean up PHY if driver probe or resume fails
PCI: rockchip: Factor out rockchip_pcie_deinit_phys()
PCI: rockchip: Factor out rockchip_pcie_disable_clocks()
PCI: rockchip: Factor out rockchip_pcie_enable_clocks()
PCI: rockchip: Factor out rockchip_pcie_setup_irq()
PCI: rockchip: Use gpiod_set_value_cansleep() to allow reset via expanders
PCI: rockchip: Use PCI_NUM_INTX
PCI: rockchip: Explicitly request exclusive reset control
dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model
dt-bindings: PCI: rockchip: Convert to per-lane PHY model
arm64: dts: rockchip: convert PCIe to use per-lane PHYs for rk3339
PCI: rockchip: Idle inactive PHY(s)
phy: rockchip-pcie: Reconstruct driver to support per-lane PHYs
PCI: rockchip: Add per-lane PHY support
PCI: rockchip: Factor out rockchip_pcie_get_phys()
PCI: rockchip: Control optional 12v power supply
dt-bindings: PCI: rockchip: Add vpcie12v-supply for Rockchip PCIe controller
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:05 +0000 (13:24 -0500)]
Merge branch 'pci/host-rcar' into next
* pci/host-rcar:
PCI: rcar: Add device tree support for r8a7743/5
PCI: rcar: Fix memory leak when no PCIe card is inserted
PCI: rcar: Fix error exit path
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:05 +0000 (13:24 -0500)]
Merge branch 'pci/host-qcom' into next
* pci/host-qcom:
PCI: qcom: Add support for IPQ8074 PCIe controller
dt-bindings: PCI: qcom: Add support for IPQ8074
PCI: qcom: Use block IP version for operations
PCI: qcom: Explicitly request exclusive reset control
PCI: qcom: Use gpiod_set_value_cansleep() to allow reset via expanders
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:04 +0000 (13:24 -0500)]
Merge branch 'pci/host-mvebu' into next
* pci/host-mvebu:
PCI: mvebu: Remove unneeded gpiod NULL check
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:03 +0000 (13:24 -0500)]
Merge branch 'pci/host-mediatek' into next
* pci/host-mediatek:
PCI: mediatek: Use PCI_NUM_INTX
PCI: mediatek: Add MSI support for MT2712 and MT7622
PCI: mediatek: Use bus->sysdata to get host private data
dt-bindings: PCI: Add support for MT2712 and MT7622
PCI: mediatek: Add controller support for MT2712 and MT7622
dt-bindings: PCI: Cleanup MediaTek binding text
dt-bindings: PCI: Rename MediaTek binding
PCI: mediatek: Switch to use platform_get_resource_byname()
PCI: mediatek: Add a structure to abstract the controller generations
PCI: mediatek: Rename port->index and mtk_pcie_parse_ports()
PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 training
PCI: mediatek: Explicitly request exclusive reset control
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:02 +0000 (13:24 -0500)]
Merge branch 'pci/host-layerscape' into next
* pci/host-layerscape:
PCI: layerscape: Add support for ls1088a
PCI: layerscape: Add support for ls2088a
PCI: artpec6: Stop enabling writes to DBI read-only registers
PCI: layerscape: Remove unnecessary class code fixup
PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates
PCI: dwc: Add accessors for write permission of DBI read-only registers
PCI: layerscape: Disable outbound windows configured by bootloader
PCI: layerscape: Refactor ls1021_pcie_host_init()
PCI: layerscape: Move generic init functions earlier in file
PCI: layerscape: Add class code and multifunction fixups for ls1021a
PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket
PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:01 +0000 (13:24 -0500)]
Merge branch 'pci/host-kirin' into next
* pci/host-kirin:
PCI: kirin: Constify dw_pcie_host_ops structure
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:01 +0000 (13:24 -0500)]
Merge branch 'pci/host-keystone' into next
* pci/host-keystone:
PCI: keystone: Use PCI_NUM_INTX
PCI: keystone: Remove duplicate MAX_*_IRQS defs
PCI: keystone-dw: Remove unused ks_pcie, pci variables
Bjorn Helgaas [Thu, 7 Sep 2017 18:24:00 +0000 (13:24 -0500)]
Merge branch 'pci/host-iproc' into next
* pci/host-iproc:
PCI: iproc: Clean up whitespace
PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP
PCI: iproc: Add 500ms delay during device shutdown
PCI: iproc: Work around Stingray CRS defects
PCI: iproc: Factor out memory-mapped config access address calculation
PCI: iproc: Remove unused struct iproc_pcie *pcie
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:59 +0000 (13:23 -0500)]
Merge branch 'pci/host-imx6' into next
* pci/host-imx6:
PCI: imx6: Explicitly request exclusive reset control
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:59 +0000 (13:23 -0500)]
Merge branch 'pci/host-hv' into next
* pci/host-hv:
PCI: hv: Do not sleep in compose_msi_msg()
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:58 +0000 (13:23 -0500)]
Merge branch 'pci/host-hisi' into next
* pci/host-hisi:
PCI: hisi: Constify dw_pcie_host_ops structure
PCI: hisi: Remove unused variable driver
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:57 +0000 (13:23 -0500)]
Merge branch 'pci/host-faraday' into next
* pci/host-faraday:
PCI: faraday: Use PCI_NUM_INTX
PCI: faraday: Fix of_irq_get() error check
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:56 +0000 (13:23 -0500)]
Merge branch 'pci/host-exynos' into next
* pci/host-exynos:
PCI: exynos: Fix platform_get_irq() error handling
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:55 +0000 (13:23 -0500)]
Merge branch 'pci/host-dra7xx' into next
* pci/host-dra7xx:
PCI: dra7xx: Fix platform_get_irq() error handling
PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe()
PCI: dra7xx: Use PCI_NUM_INTX
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:55 +0000 (13:23 -0500)]
Merge branch 'pci/host-designware' into next
* pci/host-designware:
PCI: dwc: Clear MSI interrupt status after it is handled, not before
PCI: qcom: Allow ->post_init() to fail
PCI: qcom: Don't unroll init if ->init() fails
PCI: dwc: designware: Handle ->host_init() failures
PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically
PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:54 +0000 (13:23 -0500)]
Merge branch 'pci/host-artpec6' into next
* pci/host-artpec6:
PCI: artpec6: Fix platform_get_irq() error handling
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:53 +0000 (13:23 -0500)]
Merge branch 'pci/host-armada' into next
* pci/host-armada:
PCI: armada8k: Fix platform_get_irq() error handling
PCI: armada8k: Check the return value from clk_prepare_enable()
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:53 +0000 (13:23 -0500)]
Merge branch 'pci/host-altera' into next
* pci/host-altera:
PCI: altera: Fix platform_get_irq() error handling
PCI: altera: Use size=4 IRQ domain for legacy INTx
PCI: altera: Remove unused num_of_vectors variable
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:52 +0000 (13:23 -0500)]
Merge branch 'pci/host-aardvark' into next
* pci/host-aardvark:
PCI: aardvark: Use PCI_NUM_INTX
Bjorn Helgaas [Thu, 7 Sep 2017 18:23:51 +0000 (13:23 -0500)]
Merge branch 'pci/irq-intx' into next
* pci/irq-intx:
PCI: Add pci_irqd_intx_xlate()
PCI: Move enum pci_interrupt_pin to linux/pci.h
Bjorn Helgaas [Tue, 5 Sep 2017 18:09:05 +0000 (13:09 -0500)]
PCI: xgene: Clean up whitespace
Use tabs (not spaces) for indentation. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Tue, 5 Sep 2017 17:58:03 +0000 (12:58 -0500)]
PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset
Apparently the PCIe capability is at address 0x40 in config space of X-Gene
v1 Root Ports. Add a definition of that and use the generic PCI_EXP_RTCTL
offset into the capability. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:06 +0000 (14:52 -0300)]
PCI: xgene: Fix platform_get_irq() error handling
When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Duc Dang <dhdang@apm.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:10 +0000 (14:52 -0300)]
PCI: xilinx-nwl: Fix platform_get_irq() error handling
When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:09 +0000 (14:52 -0300)]
PCI: rockchip: Fix platform_get_irq() error handling
When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:07 +0000 (14:52 -0300)]
PCI: altera: Fix platform_get_irq() error handling
platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ley Foon Tan <lftan@altera.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:05 +0000 (14:52 -0300)]
PCI: spear13xx: Fix platform_get_irq() error handling
platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:04 +0000 (14:52 -0300)]
PCI: artpec6: Fix platform_get_irq() error handling
platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Niklas Cassel <niklas.cassel@axis.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:03 +0000 (14:52 -0300)]
PCI: armada8k: Fix platform_get_irq() error handling
platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:02 +0000 (14:52 -0300)]
PCI: dra7xx: Fix platform_get_irq() error handling
When platform_get_irq() fails we should propagate the real error value
instead of always returning -EINVAL.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Fabio Estevam [Thu, 31 Aug 2017 17:52:01 +0000 (14:52 -0300)]
PCI: exynos: Fix platform_get_irq() error handling
platform_get_irq() returns a negative number on failure, so adjust the
logic to detect such condition and propagate the real error value on
failure.
Reported-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Bjorn Helgaas [Tue, 5 Sep 2017 17:33:33 +0000 (12:33 -0500)]
PCI: iproc: Clean up whitespace
Use tabs (not spaces) for indentation. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Tue, 5 Sep 2017 17:27:11 +0000 (12:27 -0500)]
PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP
PCI_EXP_CAP is an iProc-specific value, so rename it to IPROC_PCI_EXP_CAP
to make it obvious that it's not related to the generic values like
PCI_EXP_RTCTL, etc. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Oza Pawandeep [Mon, 28 Aug 2017 21:43:35 +0000 (16:43 -0500)]
PCI: iproc: Add 500ms delay during device shutdown
During soft reset (e.g., "reboot" from Linux) on some iProc-based SOCs, the
LCPLL clock and PERST both go off simultaneously. This seems in accordance
with the PCIe Card Electromechanical spec, r2.0, sec 2.2.3, which says the
clock goes inactive after PERST# goes active, but doesn't specify how long
the clock should be valid after PERST#.
However, we have observed that with the iProc Stingray, some Intel NVMe
endpoints, e.g., the P3700 400GB series, are not detected correctly upon
the next boot sequence unless the clock remains valid for some time after
PERST# is asserted.
Delay 500ms after asserting PERST# before performing a reboot. The 500ms
is experimentally determined.
Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com>
[bhelgaas: changelog, add spec reference, fold in iproc_pcie_shutdown()
export from Arnd Bergmann <arnd@arndb.de>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Bjorn Helgaas [Fri, 1 Sep 2017 21:35:50 +0000 (16:35 -0500)]
PCI: Fix typos and whitespace errors
Fix various typos and whitespace errors:
s/Synopsis/Synopsys/
s/Designware/DesignWare/
s/Keystine/Keystone/
s/gpio/GPIO/
s/pcie/PCIe/
s/phy/PHY/
s/confgiruation/configuration/
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Shawn Lin [Fri, 1 Sep 2017 21:35:30 +0000 (16:35 -0500)]
PCI: Remove unused "res" variable from pci_resource_io()
The "res" variable in pci_resource_io() is never used. Remove it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Shawn Lin [Fri, 1 Sep 2017 21:35:20 +0000 (16:35 -0500)]
PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag()
The kernel-doc comments don't match the arguments, so fix the comments.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Thu, 31 Aug 2017 19:12:39 +0000 (14:12 -0500)]
PCI/AER: Reformat AER register definitions
Reformat so comments fit on same line as definition. No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jon Derrick [Wed, 30 Aug 2017 21:05:59 +0000 (15:05 -0600)]
iommu/vt-d: Prevent VMD child devices from being remapping targets
VMD child devices must use the VMD endpoint's ID as the requester. Because
of this, there needs to be a way to link the parent VMD endpoint's IOMMU
group and associated mappings to the VMD child devices such that attaching
and detaching child devices modify the endpoint's mappings, while
preventing early detaching on a singular device removal or unbinding.
The reassignment of individual VMD child devices devices to VMs is outside
the scope of VMD, but may be implemented in the future. For now it is best
to prevent any such attempts.
Prevent VMD child devices from returning an IOMMU, which prevents it from
exposing an iommu_group sysfs directory and allowing subsequent binding by
userspace-access drivers such as VFIO.
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jon Derrick [Thu, 17 Aug 2017 18:10:13 +0000 (12:10 -0600)]
x86/PCI: Use is_vmd() rather than relying on the domain number
Use the is_vmd() predicate to identify devices below a VMD host rather than
relying on the domain number.
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jon Derrick [Thu, 17 Aug 2017 18:10:12 +0000 (12:10 -0600)]
x86/PCI: Move VMD quirk to x86 fixups
VMD currently only exists for Intel x86 products, so move the VMD quirk to
arch/x86.
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jon Derrick [Thu, 17 Aug 2017 18:10:11 +0000 (12:10 -0600)]
MAINTAINERS: Add Jonathan Derrick as VMD maintainer
Add Jonathan Derrick as VMD maintainer.
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Keith Busch <keith.busch@intel.com>
Keith Busch [Wed, 30 Aug 2017 16:15:04 +0000 (12:15 -0400)]
PCI: vmd: Remove IRQ affinity so we can allocate more IRQs
VMD hardware has to share its vectors among child devices in its PCI
domain so we should allocate as many as possible rather than just ones
that can be affinitized.
pci_alloc_irq_vectors_affinity() limits the number of affinitized IRQs to
the number of present CPUs (see irq_calc_affinity_vectors()). But we'd
prefer to have more vectors, even if they aren't distributed across the
CPUs, so use pci_alloc_irq_vectors() instead.
Reported-by: Brad Goodman <Bradley.Goodman@dell.com>
Signed-off-by: Keith Busch <keith.busch@intel.com>
[bhelgaas: add irq_calc_affinity_vectors() reference to changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Biju Das [Thu, 24 Aug 2017 09:35:44 +0000 (10:35 +0100)]
PCI: rcar: Add device tree support for r8a7743/5
Add internal PCI bridge support for r8a7743/5 SoC. The Renesas RZ/G1[ME]
(R8A7743/5) internal PCI bridge is identical to the R-Car Gen2 family.
This doesn't change the driver, so it does nothing by itself. But it does
mean that checkpatch won't complain about a future patch that adds
"renesas,pci-r8a7743" to a DT, which helps ensure that shipped DTs use
documented compatibility strings.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
[bhelgaas: add explanatory note]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Honghui Zhang [Wed, 30 Aug 2017 01:19:14 +0000 (09:19 +0800)]
PCI: mediatek: Use PCI_NUM_INTX
Switch from using custom INTX_NUM macro to the generic PCI_NUM_INTX definition
for the number of INTx interrupts.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: use subject/changelog from similar patches]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Honghui Zhang [Mon, 14 Aug 2017 13:04:28 +0000 (21:04 +0800)]
PCI: mediatek: Add MSI support for MT2712 and MT7622
MT2712 and MT7622's PCIe host controller support MSI, but only 32-bit MSI
addresses are supported. It connects to GIC with the same IRQ number as the
INTx IRQ, so it shares the same IRQ with INTx IRQ.
Add MSI support for MT2712 and MT7622.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: changes to follow rcar & tegra: rename to mtk_pcie_msi_alloc(),
add mtk_pcie_msi_free(), free hwirq if irq_create_mapping() fails, call
irq_dispose_mapping() from mtk_msi_teardown_irq()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Honghui Zhang [Mon, 14 Aug 2017 13:04:27 +0000 (21:04 +0800)]
PCI: mediatek: Use bus->sysdata to get host private data
75983c6d1f38 ("PCI: mediatek: Add controller support for MT2712 and
MT7622") has put the mtk_pcie * into bus->sysdata. Take advantage of that
to get the private data and simplify the code.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
Ryder Lee [Thu, 10 Aug 2017 06:35:00 +0000 (14:35 +0800)]
dt-bindings: PCI: Add support for MT2712 and MT7622
Add controller support for MT2712/MT7622 and update related properties.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Ryder Lee [Thu, 10 Aug 2017 06:34:59 +0000 (14:34 +0800)]
PCI: mediatek: Add controller support for MT2712 and MT7622
MT2712 and MT7622 using a new IP block of Gen2 controller which has two
root ports and shares the same probing flow with MT2701/MT7623.
Both MT2712 and MT7622 have the same per-port control registers, but
there are slight differences between them:
- MT7622 has more clocks than MT2712.
- MT7622 has shared control registers which are used to enable LTSSM and
ASPM while MT2712 does not.
Add host controller support for MT2712/MT7622.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: folded in fix from http://lkml.kernel.org/r/
1502715868-17651-2-git-send-email-honghui.zhang@mediatek.com]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Ryder Lee [Thu, 10 Aug 2017 06:34:58 +0000 (14:34 +0800)]
dt-bindings: PCI: Cleanup MediaTek binding text
To accommodate other SoC generations, regroup specific properties by SoC,
and remove redundant descriptions.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: split into a rename patch and a cleanup patch]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Ryder Lee [Thu, 10 Aug 2017 22:14:26 +0000 (17:14 -0500)]
dt-bindings: PCI: Rename MediaTek binding
To accommodate other SoC generations, rename mediatek,mt7623-pcie.txt to
mediatek-pcie.txt.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
[bhelgaas: split rename to separate patch so updates are obvious]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Ryder Lee [Thu, 10 Aug 2017 06:34:57 +0000 (14:34 +0800)]
PCI: mediatek: Switch to use platform_get_resource_byname()
This is a transitional patch. We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further patches.
Switch this function to use the platform_get_resource_byname() so that the
binding can be agnostic of the resource order.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Honghui Zhang [Thu, 10 Aug 2017 06:34:56 +0000 (14:34 +0800)]
PCI: mediatek: Add a structure to abstract the controller generations
Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate some
SoC-dependent related setting. In doing so, the common code which will be
reused by future chips.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Honghui Zhang [Thu, 10 Aug 2017 06:34:55 +0000 (14:34 +0800)]
PCI: mediatek: Rename port->index and mtk_pcie_parse_ports()
Rename "port->index" to "port->slot" since the ports are hardwired at
PCI_SLOT. Also rename "mtk_pcie_parse_ports()" to "mtk_pcie_parse_port()"
since it parses one port each time.
No functional change in this patch.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Ryder Lee [Thu, 10 Aug 2017 06:34:54 +0000 (14:34 +0800)]
PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 training
Wait for Gen2 training with readl_poll_timeout(), and simplify the hardware
assert logical by merging it into a new mtk_pcie_startup_port() interface.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Philipp Zabel [Wed, 19 Jul 2017 15:26:00 +0000 (17:26 +0200)]
PCI: mediatek: Explicitly request exclusive reset control
Commit
a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls to
explicitly state whether the driver needs exclusive or shared reset control
behavior. Convert all drivers requesting exclusive resets to the explicit
API call so the temporary transition helpers can be removed.
No functional changes.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Hou Zhiqiang [Fri, 4 Aug 2017 06:41:34 +0000 (14:41 +0800)]
PCI: layerscape: Add support for ls1088a
Add support for ls1088a.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Hou Zhiqiang [Fri, 4 Aug 2017 06:41:33 +0000 (14:41 +0800)]
PCI: layerscape: Add support for ls2088a
The ls2088a PCIe controller's register addresses are different from
ls2080a, so add a match entry to identify ls2088a PCIe.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:53:01 +0000 (18:53 +0800)]
PCI: artpec6: Stop enabling writes to DBI read-only registers
Previously we enabled writes to the DBI read-only registers so the Class
Code fix in dw_pcie_setup_rc() would work. But now dw_pcie_setup_rc()
enables write permission itself, so we don't need to do it here.
Stop enabling writes to the DBI read-only registers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:53:01 +0000 (18:53 +0800)]
PCI: layerscape: Remove unnecessary class code fixup
Now that the Class Code fixup in dw_pcie_setup_rc() works, remove the fixup
from the Layerscape driver.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:53:00 +0000 (18:53 +0800)]
PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
Pin registers, but the fixes don't actually work because these registers
are read-only.
Enable write permission before updating the Class Code and Interrupt
Pin.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:52:59 +0000 (18:52 +0800)]
PCI: dwc: Add accessors for write permission of DBI read-only registers
The read-only DBI registers can be written only when the "Write to RO
Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.
Add accessors to enable and disable write permission, and use them instead
of accessing MISC_CONTROL_1_OFF directly.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:52:58 +0000 (18:52 +0800)]
PCI: layerscape: Disable outbound windows configured by bootloader
Disable all the outbound windows to avoid one transaction hitting multiple
outbound windows. dw_pcie_setup_rc() will reconfigure the outbound
windows, which may conflict with windows configured by the bootloader.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:52:57 +0000 (18:52 +0800)]
PCI: layerscape: Refactor ls1021_pcie_host_init()
ls1021_pcie_host_init() duplicated the code in the generic
ls_pcie_host_init(). Call ls_pcie_host_init() instead of duplicating the
code.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Stan Drozd [Fri, 18 Aug 2017 14:58:10 +0000 (20:28 +0530)]
tools: PCI: Add a missing option help line
Add a missing option help line for performing legacy interrupt test.
Signed-off-by: Stan Drozd <drozdziak1@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:09 +0000 (20:28 +0530)]
misc: pci_endpoint_test: Enable/Disable MSI using module param
In certain platforms like TI's DRA7 SoCs, use of legacy PCI interrupt is
exclusive with use of MSI (Section 24.9.4.6.2.1 Legacy PCI Interrupts in
http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf).
However pci_endpoint_test driver enables MSI by default in probe. In order
for pci_endpoint_test to be able to test legacy interrupt, MSI should be
disabled. Add a module param 'no_msi' to disable MSI (only when legacy
interrupt has to be tested).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[bhelgaas: folded in static fix from Colin Ian King <colin.king@canonical.com>]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:08 +0000 (20:28 +0530)]
misc: pci_endpoint_test: Avoid using hard-coded BAR sizes
BAR sizes are hard-coded in pci_endpoint_test driver corresponding to the
sizes used in pci-epf-test function driver. This might break if the sizes
in pci-epf-test function driver are modified (and the corresponding change
is not done in pci_endpoint_test PCI driver).
To avoid hard coding BAR sizes, use pci_resource_len() API.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:07 +0000 (20:28 +0530)]
misc: pci_endpoint_test: Add support to not enable MSI interrupts
Some platforms like TI's K2G have a restriction that the host side buffer
address should be aligned to either 1MB/2MB/4MB or 8MB addresses depending
on how it is configured in the endpoint (Ref: 11.14.4.9.1 Outbound Address
Translation in K2G TRM SPRUHY8F January 2016 – Revised May 2017). This
restriction also applies to the MSI addresses provided by the RC. However
it's not possible for the RC to know about this restriction and it may not
provide 1MB/2MB/4MB or 8MB aligned address. So MSI interrupts should be
disabled even if the K2G EP has MSI capabiltiy register.
Add support to not enable MSI interrupts in pci_endpoint_test driver so
that it can be used to test K2G EP.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:06 +0000 (20:28 +0530)]
misc: pci_endpoint_test: Add support to provide aligned buffer addresses
Some platforms like TI's K2G have a restriction that the host side buffer
address should be aligned to either 1MB/2MB/4MB or 8MB (Ref: 11.14.4.9.1
Outbound Address Translation in K2G TRM SPRUHY8F January 2016 – Revised May
2017) addresses depending on how it is configured in the endpoint.
Add support to provide such aligned address here so that pci_endpoint_test
driver can be used to test K2G EP.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:05 +0000 (20:28 +0530)]
misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR
pci_endpoint_test driver assumes the PCI_ENDPOINT_TEST registers will
always be mapped to BAR_0. This need not always be the case like in TI's
K2G where BAR_0 is mapped to PCI controller application registers.
Add support so that PCI_ENDPOINT_TEST registers can be mapped to any BAR.
Change the bar_size used for BAR test accordingly.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:04 +0000 (20:28 +0530)]
PCI: designware-ep: Do not disable BARs during initialization
Some platforms like K2G has reserved use of BAR_0 which shouldn't be
disabled by software. Avoid disabling all BARs during initialization.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:03 +0000 (20:28 +0530)]
PCI: dra7xx: Reset all BARs during initialization
dra7xx has all base address registers (BAR) enabled by default. Reset all
BARs during initialization and so that BARs are enabled only if they are
actually used.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:02 +0000 (20:28 +0530)]
PCI: dwc: designware: Provide page_size to pci_epc_mem
Use the newly introduced __pci_epc_mem_init() instead of pci_epc_mem_init()
to provide page_size to pci_epc_mem. This is in preparation for
adding EP support to K2G which has a restriction that the
address region should be either divided into 1MB/2MB/4MB or 8MB
sizes (Ref: 11.14.4.9.1 Outbound Address Translation in K2G TRM SPRUHY8F
January 2016 – Revised May 2017).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Shawn Lin [Fri, 18 Aug 2017 14:58:01 +0000 (20:28 +0530)]
PCI: endpoint: Remove the ->remove() callback
epf_test is allocated using devm_kzalloc(). Hence it's not required to
explicitly free it in remove() callback. Since ->remove() callback doesn't
do anything other than freeing epf_test, remove the ->remove() callback.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:58:00 +0000 (20:28 +0530)]
PCI: endpoint: Add support to poll early for host commands
Certain platforms like TI's K2G doesn't support link-up notification. Add
support to poll early (without waiting for the linkup notification) for
commands from the host.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:57:59 +0000 (20:27 +0530)]
PCI: endpoint: Add support to use _any_ BAR to map PCI_ENDPOINT_TEST regs
pci_epf_test always maps the PCI_ENDPOINT_TEST registers to BAR_0. But if
BAR_0 is reserved for some other purpose (like in TI's K2G BAR_0 is mapped
to application registers and cannot be used to map any other regions),
PCI_ENDPOINT_TEST registers cannot be mapped making pci_epf_test unusable.
Add support to use any BAR to map PCI_ENDPOINT_TEST registers.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:57:58 +0000 (20:27 +0530)]
PCI: endpoint: Do not reset *command* inadvertently
pci_epf_test_cmd_handler() is the delayed work function which reads
*command* (set by the host) and performs various actions requested by the
host periodically. If the value in *command* is '0', it goes to the
reset_handler where it resets *command* to '0' and queues
pci_epf_test_cmd_handler().
However if the host writes a value to the *command* just after the
pci-epf-test driver checks *command* for '0' and before the control goes to
reset_handler, the *command* will be reset to '0' and the pci-epf-test
driver won't be able to perform the actions requested by the host. Fix it
here by not resetting the *command* in the reset_handler.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:57:57 +0000 (20:27 +0530)]
PCI: endpoint: Add "volatile" to pci_epf_test_reg
struct pci_epf_test_reg is the MEMSPACE of pci-epf-test function driver
that will be accessed by the "host" for programming the pci-epf-test
device. So this structure shouldn't be subjected to compiler optimization
in pci_epf_test_cmd_handler() since the values can be changed by code
outside the scope of current code at any time.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:57:56 +0000 (20:27 +0530)]
PCI: endpoint: Add support for configurable page size
pci-epc-mem uses a page size equal to *PAGE_SIZE* (usually 4KB) to manage
the address space. However certain platforms like TI's K2G have a
restriction that this address space should be either divided into
1MB/2MB/4MB or 8MB sizes (Ref: 11.14.4.9.1 Outbound Address Translation in
K2G TRM SPRUHY8F January 2016 – Revised May 2017). Add support to handle
different page sizes here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Kishon Vijay Abraham I [Fri, 18 Aug 2017 14:57:55 +0000 (20:27 +0530)]
PCI: endpoint: Make ->remove() callback optional
Make ->remove() callback optional so that endpoint function drivers don't
have to populate empty ->remove() callback functions.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:52:56 +0000 (18:52 +0800)]
PCI: layerscape: Move generic init functions earlier in file
We will use the generic ls_pcie_link_up() and ls_pcie_host_init() from
device-specific routines. Move the generic functions earlier in the file
so we won't need forward declarations. This is strictly a code move with
no functional change intended.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:52:55 +0000 (18:52 +0800)]
PCI: layerscape: Add class code and multifunction fixups for ls1021a
The current code depends on class code and multifunction fixups done by the
bootloader. Perform these fixups in ls1021_pcie_host_init() to remove this
dependency.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>
Hou Zhiqiang [Mon, 28 Aug 2017 10:52:54 +0000 (18:52 +0800)]
PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket
The STRFMR1 is not a DBI read-only register, so move it out from the
write-enable bracket.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Roy Zang <tie-fei.zang@freescale.com>