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Samuel Iglesias Gonsalvez [Fri, 18 Jul 2014 09:16:14 +0000 (11:16 +0200)]
i965/gen6/gs: Setup SOL surfaces for user-provided geometry shaders
Update gen6_gs_binding_table and gen6_sol_surface to use user-provided
geometry program information when present. This is necessary to implement
transform feedback support.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsalvez [Fri, 18 Jul 2014 09:11:00 +0000 (11:11 +0200)]
i965/gen6/gs: implement transform feedback support in gen6_gs_visitor
This takes care of generating code required to handle transform feedback.
Notice that transform feedback isn't enabled yet, since that requires
additional setups in other parts of the code that will come in later patches.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsalvez [Wed, 23 Jul 2014 08:51:35 +0000 (10:51 +0200)]
i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.
We will use this parameter in later patches to provide information relevant
to transform feedback that needs to be set as part of the FF_SYNC message.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsalvez [Wed, 23 Jul 2014 10:56:53 +0000 (12:56 +0200)]
i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcode
This opcode will be used when filling FF_SYNC header before
emitting vertices and their data.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsalvez [Fri, 18 Jul 2014 08:47:15 +0000 (10:47 +0200)]
i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcode
This opcode generates code to copy the specified destination index
into subregister 5 of the MRF message header.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsalvez [Fri, 18 Jul 2014 08:36:10 +0000 (10:36 +0200)]
i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcode
This opcode will be used when sending SVB WRITE messages to save
transform feedback outputs into Streamed Vertex Buffers.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 30 Jul 2014 07:08:48 +0000 (09:08 +0200)]
i965/gen6/gs: Enable texture units and upload sampler state.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Mon, 28 Jul 2014 08:05:57 +0000 (10:05 +0200)]
i965/gen6/gs: Assign geometry shader VUE map properly.
So far in gen6 we only used geometry shaders to implement transform feedback
in vertex shaders, so we assumed that the VUE map for the geometry shader
stage was always the same as for the vertex shader stage. This is no longer
true now that we support user provided geometry shaders in gen6 too.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Thu, 24 Jul 2014 10:18:47 +0000 (12:18 +0200)]
i965/gen6/gs: Implement support for gl_PrimitiveIdIn.
For this we will need to move PrimitiveID information, delivered in the thread
payload in r0.1, to a separate register (we use GS_OPCODE_SET_PRIMITIVE_ID
for this), then map the corresponding varying slot to that register in the
setup_payload() method.
Notice that we cannot use a virtual register as the destination for the
PrimitiveID because we need to map all input attributes to hardware registers
in setup_payload(), which happens before virtual registers are mapped to
hardware registers. We could work around that issue if we were able to compute
the first non-payload register in emit_prolog() and move the PrimitiveID
information to that register, but we can't because at that point we still
don't know the final number uniforms that will be included in the payload.
So, what we do is to place PrimitiveID information in r1, which is always
delivered as part of the payload but its only populated with data
relevant for transform feedback when we set GEN6_GS_SVBI_PAYLOAD_ENABLE
in the 3DSTATE_GS state packet.
When we implement transform feedback, we wil make sure to move the value of r1
to another register before we overwrite it with the PrimitiveID.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Thu, 24 Jul 2014 10:14:27 +0000 (12:14 +0200)]
i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.
In gen6 the geometry shader payload includes the PrimitiveID information in
r0.1. When the shader code uses glPimitiveIdIn we will have to move this to
a separate hardware register where we can map this attribute. This opcode
takes the selected destination register and moves r0.1 there.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Mon, 21 Jul 2014 09:48:42 +0000 (11:48 +0200)]
i965/gen6/gs: Handle the case where a geometry shader emits no output.
In gen6 we need to end the thread differently depending on whether we have
emitted at least one vertex or not. In case we did, the EOT message must
always include the COMPLETE flag or else the GPU hangs. If we have not
produced any output, however, we can't use the COMPLETE flag.
This would lead us to end the program with an ENDIF opcode, which we want
to avoid (and actually is not permitted since it hits an assertion), so
instead what we do is that we always request a new VUE handle every time we do
an URB WRITE, even for the last vertex we emit. With this we make sure that
whether we have emitted at least one vertex or none at all we have to finish the
thread without writing to the URB, which works for both cases by setting the
COMPLETE and UNUSED flags in the EOT message.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Mon, 21 Jul 2014 07:18:52 +0000 (09:18 +0200)]
i965/gen6/gs: Make sure we complete the last primitive.
Just in case the GS algorithm does not call EndPrimitive() for the last
primitive produced. This is relevant only for non point outputs, since for
this we are already setting the PrimEnd flag on each vertex we emit.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Fri, 18 Jul 2014 14:38:55 +0000 (16:38 +0200)]
i965/gen6/gs: Implement geometry shaders for outputs other than points.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 16 Jul 2014 07:10:35 +0000 (09:10 +0200)]
i965/gen6/gs: Add initial implementation for a gen6 geometry shader visitor.
Geometry shaders in gen6 are significantly different from gen7+ so it is better
to have them implemented in a different file rather than adding gen6 branching
paths all over brw_vec4_gs_visitor.cpp.
This commit adds an initial implementation that only handles point output, which
is the simplest case.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Thu, 17 Jul 2014 14:59:10 +0000 (16:59 +0200)]
i965: Generalize emit_urb_slot() to emit to any dst_reg.
In gen7+ we emit vertices as they come, however in gen6 geometry shaders we
have to buffer vertex data for all vertices and then emit it all in one go
at the end. To achieve this we need to generalize emit_urb_slot() to store
vertex data in general purpose registers and not only MRF registers.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 16 Jul 2014 08:00:34 +0000 (10:00 +0200)]
i965: Provide means to create registers of a given size.
Implemented by Ilia Mirkin <imirkin@alum.mit.edu>.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Thu, 17 Jul 2014 06:54:03 +0000 (08:54 +0200)]
i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.
We had GS_OPCODE_SET_DWORD_2_IMMED but this required its source argument to be
an immediate. In gen6 we need to set dword 2 of the URB write message header
from values stored in separate register, so we need something more flexible.
This change replaces GS_OPCODE_SET_DWORD_2_IMMED with GS_OPCODE_SET_DWORD_2.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Tue, 15 Jul 2014 09:26:45 +0000 (11:26 +0200)]
i965/gen6/gs: Upload binding table for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Thu, 10 Jul 2014 15:00:21 +0000 (17:00 +0200)]
i965/gen6/gs: Enable URB space for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Tue, 1 Jul 2014 11:08:25 +0000 (13:08 +0200)]
i965/gen6/gs: Compute URB entry size for user-provided geometry shaders.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 9 Jul 2014 13:32:57 +0000 (15:32 +0200)]
i965/gen6/gs: Add instruction URB flags to geometry shaders EOT message.
Gen6 seems to require that EOT messages include the complete flag too or else
the GPU hangs. We add will this flag to the instruction when we emit the
thread end opcode.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 9 Jul 2014 14:28:30 +0000 (16:28 +0200)]
i965/gen6/gs: Implement GS_OPCODE_URB_WRITE_ALLOCATE.
Gen6 geometry shaders need to allocate URB handles for each new vertex they
emit after the first (the URB handle for the first vertex is obtained via the
FF_SYNC message).
This opcode adds the URB allocation mechanism to regular URB writes.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Iago Toral Quiroga [Wed, 9 Jul 2014 06:46:17 +0000 (08:46 +0200)]
i965/gen6/gs: Implement GS_OPCODE_FF_SYNC.
This implements the FF_SYNC message required in gen6 geometry shaders to
get the initial URB handle.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsalvez [Wed, 2 Jul 2014 12:52:40 +0000 (14:52 +0200)]
i965/gs: Reuse gen6 constant push buffers setup code in gen7+.
The code required for gen6 and gen7+ is almost the same, so reuse it.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Thu, 3 Jul 2014 14:33:32 +0000 (16:33 +0200)]
i965/gen6/gs: Setup constant push buffers for gen6 geometry shaders.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Iglesias Gonsalvez [Wed, 30 Jul 2014 13:17:15 +0000 (15:17 +0200)]
i965/gen6/gs: Set brw->gs.enabled to FALSE in gen6_blorp_emit_gs_disable()
See
7dfb4b2d00ddb8e5ee24d4c58eb9415dc4ccc21c for more details.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Iglesias Gonsalvez [Tue, 1 Jul 2014 06:52:47 +0000 (08:52 +0200)]
i965/gen6/gs: use brw_gs_prog atom instead of brw_ff_gs_prog
This is needed to support user-provided geometry shaders, since the
brw_ff_gs_prog atom in gen6 only takes care of implementing transform feedback
for vertex shaders.
If there is no user-provided geometry shader the implementation falls back to
the original code.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Iglesias Gonsalvez [Tue, 1 Jul 2014 06:43:57 +0000 (08:43 +0200)]
i965/gen6/gs: Skeleton for user GS program support
Currently, gen6 only uses geometry shaders for transform feedback so the state
we emit is not suitable to accomodate general purpose, user-provided geometry
shaders. This patch paves the way to add these support and the needed
3DSTATE_GS packet modifications for it.
Previous code that emitted state to implement transform feedback in gen6 goes
to upload_gs_state_adhoc_tf().
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 1 Jul 2014 06:52:31 +0000 (08:52 +0200)]
i965/gs: Use single dispatch mode as fallback to dual object mode when possible.
Currently, when a geometry shader can't use dual object mode we fall back to
dual instance mode, however, when invocations == 1, single dispatch mode is
more performant and equally efficient in terms of register pressure.
Single dispatch mode requires that the driver can handle interleaving of
input registers, but this is already supported (dual instance mode has
the same requirement). However, to take full advantage of single dispatch mode
to reduce register pressure we would also need the ability to store two
separate vec4 output values into vec8 registers, which would approximately
double our capacity to store temporary values, but currently the vec4 visitor
and generator classes do not support this, so at the moment register pressure
in single and dual instance modes is the same.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chia-I Wu [Fri, 19 Sep 2014 07:40:31 +0000 (15:40 +0800)]
ilo: rename ILO_DEBUG=3d
It has been a bad name since we added the builder. Rename it to
ILO_DEBUG=batch to match i965, and call ilo_builder_decode() from
ilo_cp_submit_internal().
Chia-I Wu [Fri, 19 Sep 2014 07:24:23 +0000 (15:24 +0800)]
ilo: rename ilo_cp_flush()
"Flush" is used for too many things already: pipe resource flush, pipe context
flush, pipe transfer region flush, and hardware pipeline flush. Rename it to
ilo_cp_submit(). As such, ILO_DEBUG=flush is renamed to ILO_DEBUG=submit.
Chia-I Wu [Fri, 19 Sep 2014 06:37:56 +0000 (14:37 +0800)]
ilo: remove ilo_cp_empty()
Call ilo_builder_batch_used() directly.
Chia-I Wu [Fri, 19 Sep 2014 05:42:08 +0000 (13:42 +0800)]
ilo: simplify ilo_cp_set_owner()
The simplification allows us to get rid of ilo_cp_set_ring() and
ilo_cp_implicit_flush(). The 3D query code is refactored for the
simplification.
Kenneth Graunke [Mon, 15 Sep 2014 05:38:14 +0000 (22:38 -0700)]
mesa: Delete VAO _MaxElement code and index buffer bounds checking.
Fredrik's implementation of ARB_vertex_attrib_binding introduced new
gl_vertex_attrib_array and gl_vertex_buffer_binding structures, and
converted Mesa's older gl_client_array to be derived state. Ultimately,
we'd like to drop gl_client_array and use those structures directly.
One hitch is that gl_client_array::_MaxElement doesn't correspond to
either structure (unlike every other field), so we'd have to figure out
where to store it. The _MaxElement computation uses values from both
structures, so it doesn't really belong in either place. We could put
it in the VAO, but we'd have to pass it around everywhere.
It turns out that it's only used when ctx->Const.CheckArrayBounds is
set, which is only set by the (rarely used) classic swrast driver.
It appears that drivers/x11 used to set it as well, which was intended
to avoid segmentation faults on out-of-bounds memory access in the X
server (probably for indirect GLX clients). However, ajax deleted that
code in 2010 (commit
1ccef926be46dce3b6b5c76e812e2fae4e205ce7).
The bounds checking apparently doesn't actually work, either. Non-VBO
attributes arbitrarily set _MaxElement to 2 * 1000 * 1000 * 1000.
vbo_save_draw and vbo_exec_draw remark /* ??? */ when setting it, and
the i965 code contains a comment noting that _MaxElement is often bogus.
Given that the code is complex, rarely used, and dubiously functional,
it doesn't seem worth maintaining going forward. This patch drops it.
This will probably mean the classic swrast driver may begin crashing on
out of bounds vertex buffer access in some cases, but I believe that is
allowed by OpenGL (and probably happened for non-VBO accesses anyway).
There do not appear to be any Piglit regressions, either.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Roland Scheidegger <sroland@vmware.com>
Eric Anholt [Thu, 18 Sep 2014 19:22:07 +0000 (12:22 -0700)]
vc4: Add support for stencil operations.
While depth test state is passed through the fragment shader as sideband,
data, the stencil test state has to be set by the fragment shader itself.
Many tests are still failing, but this gets most of hiz/ passing.
Eric Anholt [Thu, 18 Sep 2014 18:02:59 +0000 (11:02 -0700)]
vc4: Actually implement VC4_DEBUG=cl.
Roland Scheidegger [Thu, 18 Sep 2014 14:11:04 +0000 (16:11 +0200)]
draw: (trivial) remove duplicated lines
Brian Paul [Tue, 16 Sep 2014 21:14:19 +0000 (15:14 -0600)]
mesa: fix prog_optimize.c assertions triggered by SWZ opcode
The SWZ instruction can have swizzle terms >4 (SWIZZLE_ZERO, SWIZZLE_ONE).
These swizzle terms caused a few assertions to fail.
This started happening after the commit "mesa: Actually use the Mesa IR
optimizer for ARB programs." when replaying some apitrace files.
A new piglit test (tests/asmparsertest/shaders/ARBfp1.0/swz-08.txt)
exercises this.
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Eric Anholt [Tue, 16 Sep 2014 23:03:39 +0000 (16:03 -0700)]
vc4: Allow copy propagation of uniforms.
Fixes 12 piglit tests (and 8 more crash -> fail) from reducing register
pressure.
Eric Anholt [Wed, 17 Sep 2014 00:24:03 +0000 (17:24 -0700)]
vc4: Make sure thread end doesn't have a uniform read.
Prevents regression when I start doing copy propagation on uniforms.
Eric Anholt [Tue, 16 Sep 2014 23:02:27 +0000 (16:02 -0700)]
vc4: Allow dead code elimination of instructions that read uniforms.
Eric Anholt [Tue, 16 Sep 2014 22:58:32 +0000 (15:58 -0700)]
vc4: Add support for reordering the uniform stream after optimization.
This allows for introducing dead code eliminating of uniforms, copy
propagation of uniforms, and instruction rescheduling between instructions
that both read uniforms.
Eric Anholt [Wed, 17 Sep 2014 20:10:51 +0000 (13:10 -0700)]
vc4: Initialize the various qreg arrays when allocating them.
This is particularly important for outputs, where we try to MOV the whole
vec4 to the VPM, even if only 1-3 components had been set up. It might
also be important for temporaries, if the shader reads components before
writing them.
Eric Anholt [Wed, 17 Sep 2014 20:37:53 +0000 (13:37 -0700)]
vc4: Fix stray disable of the CSE pass.
Somehow I slipped this in with the original commit of CSE.
rconde [Wed, 17 Sep 2014 16:30:23 +0000 (18:30 +0200)]
gallivm,tgsi: fix idiv by zero crash
While the result of signed integer division by zero is undefined by glsl
(and doesn't exist with d3d10), we must not crash, so need to make sure we
don't get sigfpe much like udiv already does.
Unlike udiv where we return 0xffffffff (as required by d3d10) there is
no requirement right now to return anything specific so we use zero.
Roland Scheidegger [Tue, 16 Sep 2014 01:48:45 +0000 (03:48 +0200)]
gallivm: add texture target information for sample opcodes to tgsi info
sample opcodes don't have valid texture target information (and I don't think
this should be changed), however it would be nice if we had that information
ready elsewhere, so stuff that information into the tgsi info when analyzing
a shader.
v2: Ilja Mirkin spotted some bugs wrt not handling msaa resources. So add them
and while there also add them to the tex opcode analysis this was cloned from
as well (plus get rid of some bug not detecting indirect textures there in some
cases too).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Richard Sandiford [Tue, 22 Jul 2014 10:02:11 +0000 (11:02 +0100)]
st/mesa: Fix handling of 8888 SNORM and SRGB formats for big-endian
MESA_FORMAT_x8y8z8w8 puts the x channel in the least significant part of
the containing 32-bit integer, which is equivalent to PIPE_FORMAT_xyzw8888.
PIPE_FORMAT_x8y8z8w8 puts the x channel first in memory.
This patch fixes up the mesa<->gallium mapping accordingly.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 09:51:18 +0000 (10:51 +0100)]
st/mesa: Fix handling of LA and RG formats for big-endian
MESA_FORMAT_LnAn puts the luminance in the least significant part of
the containing integer, which is equivalent to PIPE_FORMAT_LAnn.
PIPE_FORMAT_LnAn puts the luminance first in memory.
This patch fixes up the mesa<->gallium mapping accordingly.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 10:02:10 +0000 (11:02 +0100)]
mesa: Add MESA_FORMAT_{A8R8G8B8, X8R8G8B8, X8B8G8R8}_SRGB (v2)
This means that each 8888 SRGB format has a reversed counterpart,
which is necessary for handling big-endian mesa<->gallium mappings.
v2: fix missing i965 additions. (Jason)
fix 127->255 max alpha for SRGB formats. (Jason)
v1: Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 09:51:17 +0000 (10:51 +0100)]
mesa: Add MESA_FORMAT_A8L8_{SNORM,SRGB}
The associated UNORM format already existed.
This means that each LnAn format has a reversed counterpart,
which is necessary for handling big-endian mesa<->gallium mappings.
[airlied: rebased onto current master]
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 10:02:06 +0000 (11:02 +0100)]
gallium: Define PIPE_FORMAT_xyzw8888_{SNORM, SRGB} aliases
...i.e. formats in which the first listed component is in the least
significant byte of the integer. The corresponding UNORM aliases already exist.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 10:02:05 +0000 (11:02 +0100)]
gallium: Add PIPE_FORMAT_x8B8G8R8_SNORM formats
This means that each RnGnBnxn format has a reversed counterpart,
which is necessary for handling big-endian mesa<->gallium mappings.
The associated UNORM and SRGB formats already exist.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 09:51:16 +0000 (10:51 +0100)]
gallium: Define PIPE_FORMAT_{LA, AL, RG, GR}nn aliases
...i.e. formats in which the first listed component is in the least
significant half of the integer.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 22 Jul 2014 09:51:15 +0000 (10:51 +0100)]
gallium: Add PIPE_FORMAT_AnLn and PIPE_FORMAT_GnRn formats
...i.e. formats in which the alpha or green channel is first in memory.
This means that each LnAn and RnGn format has a reversed counterpart,
which is necessary for handling big-endian mesa<->gallium mappings.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 17 Sep 2014 01:56:47 +0000 (11:56 +1000)]
mesa: fix SRGB alpha channel value in pack_float_R8G8B8X8_SRGB
Jason pointed out the bug on review adding new formats,
but the existing format also appears to have the bug, so
use 255 as the max, these are SRGB no SNORM.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 16 Sep 2014 06:27:57 +0000 (16:27 +1000)]
swrast: Fix handling of MESA_FORMAT_L8A8_SRGB for big-endian
Luminance is the least-significant byte of the uint16, rather than the
lowest byte in memory. Other parts of mesa already handle this correctly
for big-endian, and swrast already handles other MESA_FORMAT_x8y8 formats
correctly. This case was just an odd-one-out.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 16 Sep 2014 06:28:04 +0000 (16:28 +1000)]
mesa: Tweak unpack name for MESA_FORMAT_R8G8B8X8_SNORM
MESA_FORMAT_R8G8B8X8_SNORM used a function called unpack_X8B8G8R8_SNORM
while MESA_FORMAT_R8G8B8X8_SRGB used a function called unpack_R8G8B8X8_SRGB.
This patch renames the SNORM function to have the same order as the
MESA_FORMAT name, like the SRGB function does.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Tue, 16 Sep 2014 06:28:05 +0000 (16:28 +1000)]
mesa: Fix alpha component in unpack_R8G8B8X8_SRGB.
The function was using the "X" component as the alpha channel,
rather than setting alpha to 1.0.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 16 Sep 2014 05:33:29 +0000 (15:33 +1000)]
util: move shared rgtc code to util (v2)
This was being shared using a ../../ get out of gallium into
mesa, and I swore when I did it I'd fix things when we got a util
dir, we did, so I have.
v2: move RGTC_DEBUG define
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Thu, 28 Aug 2014 21:44:54 +0000 (14:44 -0700)]
vc4: Claim ARB_fbo.
This gets a ton of piglit working that crashes in waffle context
management stuff otherwise. Actually supporting mismatched FB sizes is at
best going to require some more load/store generals for color buffers, but
if I can't manage to do that I'll want to just have state_tracker reject
those FBOs as unsupported, rather than deny GL 2.1.
Eric Anholt [Mon, 15 Sep 2014 18:48:02 +0000 (11:48 -0700)]
vc4: Fix memory leaks in register allocation.
Eric Anholt [Mon, 15 Sep 2014 18:45:56 +0000 (11:45 -0700)]
vc4: Move register allocation to a separate file.
I'm going to be rewriting it all, and having it mixed up with the
QIR-to-QPU opcode translation was messy.
Chris Forbes [Tue, 9 Sep 2014 07:55:29 +0000 (19:55 +1200)]
glsl: fix error message for redeclaring gl_PerVertex as output
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Forbes [Tue, 9 Sep 2014 07:55:28 +0000 (19:55 +1200)]
i965/vec4: slightly improve insn dumping with no srcs
Previously, we would get a trailing ', ' which looked strange.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 16 Sep 2014 19:55:16 +0000 (12:55 -0700)]
vc4: Add support for computed depth writes.
Fixes piglit glsl-1.10-fragdepth and early-z.
Eric Anholt [Tue, 16 Sep 2014 18:20:52 +0000 (11:20 -0700)]
vc4: Restructure depth input/output in fragment shaders.
The goal here is to have an argument for the depth write opcode so that I
can do computed depth. In the process, this makes the calculations that
will be emitted more obvious in the QIR.
Ilia Mirkin [Tue, 16 Sep 2014 01:42:01 +0000 (21:42 -0400)]
freedreno: add a standalone ir3_compiler binary for building TGSI
Compiler taken from the combo old/new compiler comparer + simulator.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 16 Sep 2014 01:42:00 +0000 (21:42 -0400)]
freedreno: add default .dir-locals.el for emacs settings
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Gwenole Beauchesne [Tue, 9 Sep 2014 08:56:24 +0000 (10:56 +0200)]
i965: add support for RGBA dma_buf imports.
This allows for importing foreign buffers in RGB32 native endian
byte order, i.e. DRM_FORMAT_XBGR8888, and DRM_FORMAT_ABGR8888.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Sat, 13 Sep 2014 00:45:30 +0000 (17:45 -0700)]
i965: Mark delta_x/y as BAD_FILE if remapped away completely.
Commit
afe3d1556f6b77031f7025309511a0eea2a3e8df (i965: Stop doing
remapping of "special" regs.) stopped remapping delta_x/delta_y, and
additionally stopped considering them always-live. We later realized
delta_x was used in register allocaiton, so we actually needed to remap
it, which was fixed in commit
23d782067ae834ad53522b46638ea21c62e94ca3
(i965/fs: Keep track of the register that hold delta_x/delta_y.).
However, that commit didn't restore the "always consider it live" part.
If all the code using delta_x was eliminated, fs_visitor::delta_x would
be left pointing at its old register number. Later code in register
allocation would handle that register number specially...even though it
wasn't actually delta_x.
To combat this, set delta_x/y to BAD_FILE if they're eliminated, and
check for that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83127
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Mon, 1 Sep 2014 23:51:56 +0000 (09:51 +1000)]
st_glsl_to_tgsi: init have_sqrt field.
Coverity reported this.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 15 Sep 2014 04:41:04 +0000 (14:41 +1000)]
llvmpipe: fix rast debugging output
The triangle_32_ rast functions never made it into the debug output,
confused me for a few seconds.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:32:38 +0000 (16:32 +0100)]
util: Add big-endian layout for a number of formats.
This patch builds on
6c8f547f66e68b495c708f8ffcb67370caa5ffe8 and
previous patches by allowing u_format.csv to specify separate big-endian
and little-endian layouts. It then uses this to specify the correct layouts
for various depth/stencil formats. Later patches handle other formats.
To recap, the idea is that u_format.csv lists the channels for an N-byte
value as though it were an N-byte integer. For little-endian targets
the channels are listed starting at the least-significant bit of the
integer while for big-endian targets the channels are listed starting
at the most-significant bit. This means that for something like
PIPE_FORMAT_B8G8R8A8_UNORM (blue in first byte of memory, alpha in last
byte of memory) the orders are the same for both endiannesses. But for
something like PIPE_FORMAT_S8_UINT_Z24_UNORM, where the stencil is in
the least significant byte of a 32-bit integer, there need to be separate
channel definitions for each endianness.
The effect of this patch is to make the affected PIPE_FORMAT_*s have
the same layout as the associated MESA_FORMAT_*s for big-endian.
The MESA_FORMAT_*s are already handled correctly.
Fixes various piglit tests on z. No regressions on x86_64.
[airlied: squash subsequent patches]
util: Add big-endian layout for 5551 and 565 formats
util: Add big-endian layout for 10/10/10/2 formats
util: Add big-endian layout for 4444 formats
util: Add big-endian layout for 233 format
util: Add big-endian layout for 44 formats
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:53:36 +0000 (16:53 +0100)]
llvmpipe: Fix PIPE_FORMAT_Z32_FLOAT_S8X24_UINT handling for big-endian.
llvmpipe treats PIPE_FORMAT_Z32_FLOAT_S8X24_UINT as a bit of a special case,
handling it as two 32-bit pieces rather than a single 64-bit block:
/* 64bit d/s format is special already extracted 32 bits */
total_bits = format_desc->block.bits > 32 ? 32 : format_desc->block.bits;
The format_desc describes the whole 64-bit block, so the z shift
will be 32 for big-endian. But since we're accessing the z channel
as a 32-bit value rather than a 64-bit value, we need to mask the shift
with 31.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:53:35 +0000 (16:53 +0100)]
gallivm: Fix uses of 2^24
Fallback cases in lp_bld_arit.c used 2^24 to mean "2 to the power 24",
but in C it's "2 xor 24", i.e. 26. Fixed by using 1<< instead.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:53:34 +0000 (16:53 +0100)]
gallivm: Add SNORM clamping to lp_build_{add, sub}
...fixing the associated TODO.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Rafael Ávila de Espíndola [Tue, 16 Sep 2014 01:46:02 +0000 (03:46 +0200)]
gallivm: attach DataLayout to module too, not just pass manager.
It looks like it was possible to attach it to both for a long time, however
since llvm r217548 attaching it to just the pass manager is no longer
sufficient and causes bugs (see http://llvm.org/bugs/show_bug.cgi?id=20903).
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 15 Sep 2014 17:10:10 +0000 (19:10 +0200)]
gallivm: handle SAMPLE opcode in aos sampling
This is just a very limited version, in particular sampler and sampler view
index must be the same. It cannot handle any modifiers neither.
Works much the same as soa version otherwise, to figure out the target we
need to store the sampler view dcls.
While here, also handle (no-op) RET and get rid of a couple bogus deprecated
comments.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 15 Sep 2014 16:44:57 +0000 (18:44 +0200)]
tgsi: accept offsets for sample opcodes too in the text parser
sample opcodes are a little oddly represented in the opcode_info, since
they don't count as texture instructions - they don't have valid target
information, but they may have offsets (unlike "ordinary" texture
instructions, the texture token may be optional for them).
So just make sure with these opcodes the optional offsets are accepted.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Fri, 12 Sep 2014 22:29:56 +0000 (00:29 +0200)]
tgsi: don't print texture target for sample opcodes
sample opcodes don't encode a texture target, it would thus always
print UNKNOWN, which is not helpful (and wouldn't parse when giving
back the shader text to tgsi).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Mon, 15 Sep 2014 20:32:18 +0000 (13:32 -0700)]
vc4: Bump maximum ARB program temporaries to match Intel/AMD.
This query has always been useless, but we could potentially reject
well-formed, runnable programs if we expose a value that's too low.
Eric Anholt [Mon, 15 Sep 2014 20:26:24 +0000 (13:26 -0700)]
vc4: Bump maximum uniforms count to match other drivers.
We don't have any specific limits in the hardware, just like the other
GPUs, so match their behavior. Fixes minmax_gles2 and several other
piglit tests relying on the specced uniform minmax values.
Eric Anholt [Mon, 15 Sep 2014 19:02:43 +0000 (12:02 -0700)]
vc4: Dynamically allocate the TGSI-to-qreg arrays.
Fixes buffer overflows in some piglit tests (which are still failing to
register allocate anyway).
Eric Anholt [Mon, 15 Sep 2014 19:19:28 +0000 (12:19 -0700)]
vc4: Fix memory leaks of struct qinst.
Eric Anholt [Mon, 15 Sep 2014 19:15:02 +0000 (12:15 -0700)]
vc4: Fix memory leaks of some vc4_compile contents.
Eric Anholt [Mon, 15 Sep 2014 19:04:32 +0000 (12:04 -0700)]
vc4: Reuse the util header instead of defining our own ARRAY_SIZE.
Fixes redefinition warnings if you end up including this header before
util stuff.
Brian Paul [Fri, 12 Sep 2014 16:00:09 +0000 (10:00 -0600)]
mesa: move i, j var decls into SWIZZLE_CONVERT_LOOP() macro
Put macro code in do {} while loop and put semicolons on macro calls
so auto indentation works properly.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Fri, 12 Sep 2014 14:31:15 +0000 (08:31 -0600)]
mesa: break up _mesa_swizzle_and_convert() to reduce compile time
This reduces gcc -O3 compile time to 1/4 of what it was on my system.
Reduces MSVC release build time too.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kalyan Kondapally [Thu, 11 Sep 2014 03:20:23 +0000 (20:20 -0700)]
Generate a warning when not writing gl_Position with GLES.
With GLES we don't give any kind of warning in case we don't
write to gl_position. This patch makes changes so that we
generate a warning in case of GLES (VER < 300) and an error
in case of GL.
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tapani Pälli [Fri, 12 Sep 2014 07:36:08 +0000 (10:36 +0300)]
mesa: check that uniform exists in glUniform* functions
Remap table for uniforms may contain empty entries when using explicit
uniform locations. If no active/inactive variable exists with given
location, remap table contains NULL.
v2: move remap table bounds check before existence check (Ian Romanick)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83574
Chia-I Wu [Mon, 15 Sep 2014 01:09:54 +0000 (09:09 +0800)]
ilo: clean up 3D/media functions
Mostly style changes to set dw[0] directly.
Chia-I Wu [Mon, 15 Sep 2014 01:00:26 +0000 (09:00 +0800)]
ilo: fix gen6_3DSTATE_MULTISAMPLE()
There was a typo introduced by
90f4b131fccae3a950864ed9ba15eea8edce915f.
Rob Clark [Sat, 13 Sep 2014 12:25:51 +0000 (08:25 -0400)]
freedreno/a3xx: 3d/array textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 13 Sep 2014 02:20:07 +0000 (22:20 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Chia-I Wu [Sat, 13 Sep 2014 16:15:20 +0000 (00:15 +0800)]
ilo: trust vertex element count more
We might run into ve->count == 0 and last_velement_edgeflag == true in
gen6_3DSTATE_VERTEX_ELEMENTS() when the state tracker sets an invalid
combination of VS and VE (does not seem to happen with st/mesa). Do not
assume ve->count is positive when last_velement_edgeflag is true.
Reported by Coverity.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Sat, 13 Sep 2014 14:15:46 +0000 (22:15 +0800)]
ilo: simplify src operand gathering in disassembler
Always initialize the operand array to point to src0, src1, and src2.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Sat, 13 Sep 2014 15:10:42 +0000 (23:10 +0800)]
ilo: derive 3-src instructions from the opcode table
One less switch statement to maintain.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Ilia Mirkin [Sat, 13 Sep 2014 15:28:28 +0000 (11:28 -0400)]
nouveau: check for mesa context init failure
Reported by Coverity
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 13 Sep 2014 15:06:17 +0000 (11:06 -0400)]
nouveau: avoid leaking screen on initialization fail
Reported by Coverity
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 13 Sep 2014 14:45:08 +0000 (10:45 -0400)]
nouveau: change internal variables to avoid conflicts with macro args
Reported by Coverity
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>