OSDN Git Service
Manman Ren [Fri, 6 Sep 2013 18:13:59 +0000 (18:13 +0000)]
Debug Info Testing: Updated to use null instead of "i32 0" for containing-type
field of DICompositeType.
This will help the follow-on patch of using DITypeRef for containing-type field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190187
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Adrian Prantl [Fri, 6 Sep 2013 18:12:01 +0000 (18:12 +0000)]
debuginfo-tests: Add support for an lldb wrapper script
to be used on darwin in lieu of gdb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190186
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Andrew Trick [Fri, 6 Sep 2013 17:32:47 +0000 (17:32 +0000)]
mi-sched: cleanup register pressure update, remove a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190181
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Andrew Trick [Fri, 6 Sep 2013 17:32:44 +0000 (17:32 +0000)]
mi-sched: improve regpressure tracing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190180
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Andrew Trick [Fri, 6 Sep 2013 17:32:42 +0000 (17:32 +0000)]
mi-sched: print tree size in -view-misched-dags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190179
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Andrew Trick [Fri, 6 Sep 2013 17:32:39 +0000 (17:32 +0000)]
mi-sched: register pressure update tracing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190178
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Andrew Trick [Fri, 6 Sep 2013 17:32:36 +0000 (17:32 +0000)]
mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190177
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Andrew Trick [Fri, 6 Sep 2013 17:32:34 +0000 (17:32 +0000)]
Added MachineSchedPolicy.
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190176
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Hans Wennborg [Fri, 6 Sep 2013 17:05:46 +0000 (17:05 +0000)]
msbuild integration: provide separate files for VS2010 and VS2012
The previous msbuild integration only worked if VS2010 was installed. This patch
renames the current integration to LLVM-vs2010 and adds LLVM-vs2012.
Differential Revision: http://llvm-reviews.chandlerc.com/D1614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190173
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Matthias Braun [Fri, 6 Sep 2013 16:44:32 +0000 (16:44 +0000)]
avoid unnecessary direct access to LiveInterval::ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190170
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Matthias Braun [Fri, 6 Sep 2013 16:44:29 +0000 (16:44 +0000)]
remove unused argument from LiveRanges::join()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190169
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Matthias Braun [Fri, 6 Sep 2013 16:44:27 +0000 (16:44 +0000)]
remove pointless assert
The if above it ensures the property anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190168
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Matthias Braun [Fri, 6 Sep 2013 16:44:25 +0000 (16:44 +0000)]
fix comment
There's no 'B3' in the example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190167
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Matthias Braun [Fri, 6 Sep 2013 16:19:22 +0000 (16:19 +0000)]
fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190165
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Daniel Sanders [Fri, 6 Sep 2013 13:25:06 +0000 (13:25 +0000)]
[mips][msa] Indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190156
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Daniel Sanders [Fri, 6 Sep 2013 13:15:05 +0000 (13:15 +0000)]
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190155
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Vladimir Medic [Fri, 6 Sep 2013 13:08:00 +0000 (13:08 +0000)]
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154
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Daniel Sanders [Fri, 6 Sep 2013 13:01:47 +0000 (13:01 +0000)]
[mips][msa] Made the operand register sets optional for the VEC formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190153
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Vladimir Medic [Fri, 6 Sep 2013 12:53:21 +0000 (12:53 +0000)]
This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152
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Daniel Sanders [Fri, 6 Sep 2013 12:50:52 +0000 (12:50 +0000)]
[mips][msa] Made the operand register sets optional for the ELM_INSVE formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190151
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Daniel Sanders [Fri, 6 Sep 2013 12:44:13 +0000 (12:44 +0000)]
[mips][msa] Made the operand register sets optional for the 3RF_4RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190150
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Vladimir Medic [Fri, 6 Sep 2013 12:41:17 +0000 (12:41 +0000)]
This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148
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Tim Northover [Fri, 6 Sep 2013 12:38:12 +0000 (12:38 +0000)]
SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.
The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190147
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Daniel Sanders [Fri, 6 Sep 2013 12:32:57 +0000 (12:32 +0000)]
[mips][msa] Made the operand register sets optional for the 3RF formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190146
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Daniel Sanders [Fri, 6 Sep 2013 12:30:43 +0000 (12:30 +0000)]
[mips][msa] Made the operand register sets optional for the 3R_4R format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190145
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Vladimir Medic [Fri, 6 Sep 2013 12:30:36 +0000 (12:30 +0000)]
This patch adds support for microMIPS disassembler and disassembler make check tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144
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Daniel Sanders [Fri, 6 Sep 2013 12:28:13 +0000 (12:28 +0000)]
[mips][msa] Made the operand register sets optional for the 2RF format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143
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Daniel Sanders [Fri, 6 Sep 2013 12:25:47 +0000 (12:25 +0000)]
[mips][msa] Made the operand register sets optional for the I8 format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190142
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Daniel Sanders [Fri, 6 Sep 2013 12:23:19 +0000 (12:23 +0000)]
[mips][msa] Made the operand register sets optional for the I5 and SI5 formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190141
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Daniel Sanders [Fri, 6 Sep 2013 12:10:24 +0000 (12:10 +0000)]
[mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190140
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Richard Sandiford [Fri, 6 Sep 2013 11:51:39 +0000 (11:51 +0000)]
[SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands. The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account. The code
to do that was getting increasingly hairy and was also making some bad
decisions. E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.
This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138
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Daniel Sanders [Fri, 6 Sep 2013 11:01:38 +0000 (11:01 +0000)]
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190134
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Daniel Sanders [Fri, 6 Sep 2013 10:59:24 +0000 (10:59 +0000)]
[mips][msa] Made the operand register sets optional for the 3R format
Their default is to be the same as the result register set.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190133
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Daniel Sanders [Fri, 6 Sep 2013 10:55:15 +0000 (10:55 +0000)]
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment.
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190131
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Richard Sandiford [Fri, 6 Sep 2013 10:25:07 +0000 (10:25 +0000)]
[SystemZ] Use XC for a memset of 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190130
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Matt Arsenault [Fri, 6 Sep 2013 00:37:24 +0000 (00:37 +0000)]
Use type helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190113
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Matt Arsenault [Fri, 6 Sep 2013 00:18:43 +0000 (00:18 +0000)]
Teach CodeGenPrepare about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190112
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Tom Stellard [Thu, 5 Sep 2013 23:55:13 +0000 (23:55 +0000)]
R600: Coding style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190110
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Juergen Ributzka [Thu, 5 Sep 2013 23:02:56 +0000 (23:02 +0000)]
[X86] Perform VSELECT DAG combines also before DAG type legalization.
If the DAG already has only legal types, then the second round of DAG combines
is skipped. In this case VSELECT+SETCC patterns that match a more efficient
instruction (e.g. min/max) are never recognized.
This fix allows VSELECT+SETCC combines if the types are already legal before DAG
type legalization.
Reviewer: Nadav
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190105
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Kevin Enderby [Thu, 5 Sep 2013 20:25:06 +0000 (20:25 +0000)]
Fixed a crash in the integrated assembler for Mach-O when a symbol difference
expression uses an assembler temporary symbol from an assignment. Â In this case
the symbol does not have a fragment so the use of getFragment() would be NULL
and caused a crash. In the case of an assembler temporary symbol we want to use
the AliasedSymbol (if any) which will create a local relocation entry, but if
it is not an assembler temporary symbol then let it use that symbol with an
external relocation entry.
rdar://
9356266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190096
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Matt Arsenault [Thu, 5 Sep 2013 19:48:28 +0000 (19:48 +0000)]
Consistently use dbgs() in debug printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190093
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Manman Ren [Thu, 5 Sep 2013 19:44:52 +0000 (19:44 +0000)]
Trying to un-break the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190092
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Matt Arsenault [Thu, 5 Sep 2013 19:41:10 +0000 (19:41 +0000)]
R600: Fix i64 to i32 trunc on SI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190091
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Rafael Espindola [Thu, 5 Sep 2013 19:15:21 +0000 (19:15 +0000)]
Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190090
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Yunzhong Gao [Thu, 5 Sep 2013 19:14:26 +0000 (19:14 +0000)]
Improve handling of .file, .include and .incbin directives to
allow escaped octal character sequences.
The patch was discussed in Phabricator. See:
http://llvm-reviews.chandlerc.com/D1289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190089
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Manman Ren [Thu, 5 Sep 2013 18:48:31 +0000 (18:48 +0000)]
Debug Info: Use identifier to reference DIType in base type field of
ptr_to_member.
We introduce a new class DITypeRef that represents a reference to a DIType.
It wraps around a Value*, which can be either an identifier in MDString
or an actual MDNode. The class has a helper function "resolve" that
finds the actual MDNode for a given DITypeRef.
We specialize getFieldAs to return a field that is a reference to a
DIType. To correctly access the base type field of ptr_to_member,
getClassType now calls getFieldAs<DITypeRef> to return a DITypeRef.
Also add a typedef for DITypeIdentifierMap and a helper
generateDITypeIdentifierMap in DebugInfo.h. In DwarfDebug.cpp, we keep
a DITypeIdentifierMap and call generateDITypeIdentifierMap to actually
populate the map.
Verifier is updated accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190081
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Tom Stellard [Thu, 5 Sep 2013 18:38:09 +0000 (18:38 +0000)]
R600: Add support for local memory atomic add
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080
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Tom Stellard [Thu, 5 Sep 2013 18:38:03 +0000 (18:38 +0000)]
R600: Expand SELECT nodes rather than custom lowering them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190079
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Tom Stellard [Thu, 5 Sep 2013 18:37:57 +0000 (18:37 +0000)]
R600: Fix incorrect LDS size calculation
GlobalAdderss nodes that appeared in more than one basic block were
being counted twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190078
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Tom Stellard [Thu, 5 Sep 2013 18:37:52 +0000 (18:37 +0000)]
R600/SI: Don't emit S_WQM_B64 instruction for compute shaders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190077
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Tom Stellard [Thu, 5 Sep 2013 18:37:45 +0000 (18:37 +0000)]
R600: Fix segfault in R600TextureIntrinsicReplacer
This pass was segfaulting when it ran into a non-intrinsic function
call. Function calls are not supported, so now instead of segfaulting,
we will get an assertion failure with a nice error message.
I'm not sure how to test this using lit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190076
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Eric Christopher [Thu, 5 Sep 2013 18:20:16 +0000 (18:20 +0000)]
Move accelerator table defines and constants to Dwarf.h since
we're proposing it for DWARF5.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190074
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Eric Christopher [Thu, 5 Sep 2013 16:55:35 +0000 (16:55 +0000)]
Rename enums to match convention and remove superfluous "dwarf" in names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190067
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Eric Christopher [Thu, 5 Sep 2013 16:46:43 +0000 (16:46 +0000)]
Reformat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190064
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Joey Gouly [Thu, 5 Sep 2013 16:05:45 +0000 (16:05 +0000)]
[ARMv8] Add some missing tests for DSB/DMB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190060
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Joey Gouly [Thu, 5 Sep 2013 15:35:24 +0000 (15:35 +0000)]
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055
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Richard Barton [Thu, 5 Sep 2013 14:14:19 +0000 (14:14 +0000)]
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053
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Tilmann Scheller [Thu, 5 Sep 2013 11:59:43 +0000 (11:59 +0000)]
Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047
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Tilmann Scheller [Thu, 5 Sep 2013 11:10:31 +0000 (11:10 +0000)]
ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.
Patch by Daniel Stewart!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043
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Richard Sandiford [Thu, 5 Sep 2013 10:36:45 +0000 (10:36 +0000)]
[SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which
all operands are memory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041
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Nick Lewycky [Thu, 5 Sep 2013 08:19:58 +0000 (08:19 +0000)]
Declare missing dependency on AliasAnalysis. Patch by Liu Xin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190035
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Nick Lewycky [Thu, 5 Sep 2013 06:53:59 +0000 (06:53 +0000)]
Fix typos in assert message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190034
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Venkatraman Govindaraju [Thu, 5 Sep 2013 05:32:16 +0000 (05:32 +0000)]
[Sparc] Correctly handle call to functions with ReturnsTwice attribute.
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.
This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190033
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Reid Kleckner [Thu, 5 Sep 2013 02:09:34 +0000 (02:09 +0000)]
msbuild: Add clang's compiler-rt libs to the LibraryPath
This allows linking libraries like the asan RTL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190028
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Bill Wendling [Thu, 5 Sep 2013 00:54:52 +0000 (00:54 +0000)]
Fix comments to reflect reality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190021
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Eric Christopher [Thu, 5 Sep 2013 00:22:35 +0000 (00:22 +0000)]
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190019
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Eric Christopher [Thu, 5 Sep 2013 00:01:17 +0000 (00:01 +0000)]
Clean up some whitespace and comment formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190015
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Andrew Trick [Wed, 4 Sep 2013 23:54:00 +0000 (23:54 +0000)]
mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190014
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Nick Kledzik [Wed, 4 Sep 2013 23:53:44 +0000 (23:53 +0000)]
Add names for mach-o permissions bits and use the symbol names in place of magic numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190013
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Eric Christopher [Wed, 4 Sep 2013 23:38:29 +0000 (23:38 +0000)]
Move default dwarf version enum into the llvm dwarf constants rather
than the spec dwarf constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190011
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Nick Kledzik [Wed, 4 Sep 2013 23:27:21 +0000 (23:27 +0000)]
fix typo in enum name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190009
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Bill Wendling [Wed, 4 Sep 2013 22:35:41 +0000 (22:35 +0000)]
Add missing header line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190004
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Bill Wendling [Wed, 4 Sep 2013 22:35:29 +0000 (22:35 +0000)]
Use ArrayRef instead of explicit container.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190003
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Eric Christopher [Wed, 4 Sep 2013 22:21:24 +0000 (22:21 +0000)]
Remove hack ensuring that darwin didn't produce dwarf > 3 for modules
without a limiting factor.
Update all testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190002
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Eric Christopher [Wed, 4 Sep 2013 21:36:52 +0000 (21:36 +0000)]
Revert "Revert r189902 as the workaround shouldn't be necessary anymore."
Needs testcase updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190000
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Eric Christopher [Wed, 4 Sep 2013 21:26:56 +0000 (21:26 +0000)]
Revert r189902 as the workaround shouldn't be necessary anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189999
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Eric Christopher [Wed, 4 Sep 2013 21:23:23 +0000 (21:23 +0000)]
Expand and rewrite comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189998
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Andrew Trick [Wed, 4 Sep 2013 21:12:05 +0000 (21:12 +0000)]
comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189997
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Andrew Trick [Wed, 4 Sep 2013 21:00:20 +0000 (21:00 +0000)]
Remove dead subtree limit code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189995
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Andrew Trick [Wed, 4 Sep 2013 21:00:18 +0000 (21:00 +0000)]
-view-misched-dags, better pruning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189994
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Andrew Trick [Wed, 4 Sep 2013 21:00:16 +0000 (21:00 +0000)]
mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189993
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Andrew Trick [Wed, 4 Sep 2013 21:00:13 +0000 (21:00 +0000)]
80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189992
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Andrew Trick [Wed, 4 Sep 2013 21:00:11 +0000 (21:00 +0000)]
mi-sched: Suppress register pressure tracking when the scheduling window is too small.
If the instruction window is < NumRegs/2, pressure tracking is not
likely to be effective. The scheduler has to process a very large
number of tiny blocks. We want this to be fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189991
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Andrew Trick [Wed, 4 Sep 2013 21:00:08 +0000 (21:00 +0000)]
mi-sched: Load clustering is a bit to expensive to enable unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189990
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Andrew Trick [Wed, 4 Sep 2013 21:00:05 +0000 (21:00 +0000)]
mi-sched: Reuse an invalid HazardRecognizer to save compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189989
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Andrew Trick [Wed, 4 Sep 2013 21:00:02 +0000 (21:00 +0000)]
mi-sched: bypass heuristic checks when regpressure tracking is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189988
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Andrew Trick [Wed, 4 Sep 2013 20:59:59 +0000 (20:59 +0000)]
Added -misched-regpressure option.
Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189987
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Arnold Schwaighofer [Wed, 4 Sep 2013 20:51:06 +0000 (20:51 +0000)]
Change swift/vldm test case to be less dependent on allocation order
'Force' values in registers using the calling convention. Now, we only depend on
the calling convention and that the allocator performs copy coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189985
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Rafael Espindola [Wed, 4 Sep 2013 20:08:46 +0000 (20:08 +0000)]
Rename some variables to match the style guide.
I am about to patch this code, and this makes the diff far more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189982
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Vincent Lejeune [Wed, 4 Sep 2013 19:53:54 +0000 (19:53 +0000)]
R600: Use shared op optimization when checking cycle compatibility
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189981
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Vincent Lejeune [Wed, 4 Sep 2013 19:53:46 +0000 (19:53 +0000)]
R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980
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Vincent Lejeune [Wed, 4 Sep 2013 19:53:30 +0000 (19:53 +0000)]
R600: Use SchedModel enum for is{Trans,Vector}Only functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189979
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Vincent Lejeune [Wed, 4 Sep 2013 19:53:22 +0000 (19:53 +0000)]
R600: Remove fmul.v4f32.ll test which is redundant with fmul.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189978
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Eric Christopher [Wed, 4 Sep 2013 19:53:21 +0000 (19:53 +0000)]
Unify and clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189977
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Rafael Espindola [Wed, 4 Sep 2013 19:19:32 +0000 (19:19 +0000)]
Merge these 2 tests in a single file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189975
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Jim Grosbach [Wed, 4 Sep 2013 19:08:44 +0000 (19:08 +0000)]
ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.
I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).
PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189972
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Rafael Espindola [Wed, 4 Sep 2013 18:53:21 +0000 (18:53 +0000)]
Small simplification given that insert of an empty range is a nop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189971
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Bill Wendling [Wed, 4 Sep 2013 18:48:12 +0000 (18:48 +0000)]
Remove 'param' label from comments. They aren't used properly here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189970
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Rafael Espindola [Wed, 4 Sep 2013 18:37:36 +0000 (18:37 +0000)]
Refactor duplicated logic to a helper function.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189969
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Rafael Espindola [Wed, 4 Sep 2013 18:16:02 +0000 (18:16 +0000)]
Remove dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189967
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