radeon uvd add uvd fw version for amdgpu

Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

nv50/ir: print EMIT subops in debug mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: print RSQ/RCP subops in debug mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: print PIXLD subops in debug mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: print SHFL subops in debug mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965: Removing PCI IDs that are no longer listed as Kabylake.

This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.

However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.

So it is better removing them before they become used in any
other future platform.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

i956: Add more Kabylake PCI IDs.

The spec has been updated adding new PCI IDs.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

gallium/radeon: remove zombie textures kept alive by DCC stat gathering

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: don't re-create queries for DCC stat gathering

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: assume X11 DRI3 can use at most 5 back buffers

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: separate DCC starts as disabled (ps_draw_ratio = 0)

DRI3:
- Only slows clears can enable it for the first frame.
- A good PS/draw ratio can enable it for other frames.

DRI2:
- Only slows clears can enable it for a frame.
- Page-flipped color buffers are unref'd at the end of each frame,
  so it can't be enabled in any other way.
- Relying on slow clears is sufficient for our synthetic benchmarks.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: R600_DEBUG=nodccfb disables separate DCC

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add and use r600_texture_reference

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add a HUD query for PS draw ratio stats from separate DCC

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add a heuristic enabling DCC for scanout surfaces (v2)

DCC for displayable surfaces is allocated in a separate buffer and is
enabled or disabled based on PS invocations from 2 frames ago (to let
queries go idle) and the number of slow clears from the current frame.

At least an equivalent of 5 fullscreen draws or slow clears must be done
to enable DCC. (PS invocations / (width * height) + num_slow_clears >= 5)

Pipeline statistic queries are always active if a color buffer that can
have separate DCC is bound, even if separate DCC is disabled. That means
the window color buffer is always monitored and DCC is enabled only when
the situation is right.

The tracking of per-texture queries in r600_common_context is quite ugly,
but I don't see a better way.

The first fast clear always enables DCC. DCC decompression can disable it.
A later fast clear can enable it again. Enable/disable typically happens
only once per frame.

The impact is expected to be negligible because games usually don't have
a high level of overdraw. DCC usually activates when too much blending
is happening (smoke rendering) or when testing glClear performance and
CMASK isn't supported (Stoney).

v2: rename stuff, add assertions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add state setup for a separate DCC buffer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: always calculate DCC info even if it's not used immediately

for a later use

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: unreference framebuffer state with set_framebuffer_state

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add flag R600_QUERY_HW_FLAG_BEGIN_RESUMES

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965: Use intel_get_param() more often

Replace some open-coded ioctls with intel_get_param().

This is just a cleanup. No change in behavior.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Refactor intel_get_param()

Replace the function's __DRIscreen parameter with struct intel_screen.
The callsites feel more natural that way.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeonsi: don't advertise multisample shader images

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable distributed tess on multi-SE parts only

ported from Vulkan

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set optimal VGT_HS_OFFCHIP_PARAM

ported from Vulkan

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable CU0 in each SE for LS-HS execution

Offchip-only tessellation allows this.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use conformant line rasterization

AA lines are not completely correct (see TODO), but everything else
should be.

+ 3 linestipple piglits

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Android: add missing u_math.h include path for libmesa_isl

Commit 87d062a94080 ("i965: Fix shared local memory size for Gen9+.")
added u_math.h include which broke the Android build:

In file included from external/mesa3d/src/intel/isl/isl_storage_image.c:25:
In file included from external/mesa3d/src/mesa/drivers/dri/i965/brw_compiler.h:29:
external/mesa3d/src/mesa/main/macros.h:35:10: fatal error: 'util/u_math.h' file not found
         ^

Add the missing include paths for libmesa_isl.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Kenneth Garunke <kenneth@whitecape.org>

svga: force direct map for transfering multiple slices

With commit fb9fe35, we start using transfer_inline_write
for memcpy of TexSubImage. But SurfaceDMA command does not work
well with texture array. This patch forces direct map when
transfering multiple slices of a texture array.

Fixes piglit regression "texelFetch fs sampler1DArray"

Tested with MTT piglit, glretrace, conform.

Reviewed-by: Sinclair Yeh <syeh@vmware.com>

svga: whitespace, line wrapping fixes in svga_surface.c

gm107/ir: make sure that flagsDef is set when emitting setcond

Rely on the existence of a second destination when emitting a setcond
flag is dangerous, because this doesn't mean that the flag has been
correctly set. Instead rely on flagsDef like what emitX() does
for flagsSrc.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

doc: improve INTEL_DEBUG documentation

Remove 'reg' option that does not actually exist, elaborate more about
'sync' and add the missing options.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: set PA_SU_SMALL_PRIM_FILTER_CNTL register on Polaris

This was missing.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

radeon/vce: use vce structure for vce 52 firmware

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

radeon/vce: add vce structures

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

st/omx: fix decoder fillout for the OMX result buffer

The call for vl_video_buffer_adjust_size is with wrong order of
arguments, apparently it will have problem when interlaced false;

The size of OMX result buffer depends on real size of clips, vl buffer
dimension is aligned with 16, so 1080p(1920*1080) video will overflow
the OMX buffer

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>

pipe_loader_sw: Fix fd leak when instantiated via pipe_loader_sw_probe_kms

Make pipe_loader_sw_probe_kms take ownership of the passed in fd,
like pipe_loader_drm_probe_fd does.

The only caller is dri_kms_init_screen which passes in a dupped fd,
just like dri2_init_screen passes in a dupped fd to
pipe_loader_drm_probe_fd.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

clover: Fix kernel metadata retrieval after clang r273425

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Acked-by: Francisco Jerez <currojerez@riseup.net>

clover/llvm: Fix copyright attribution of invocation.cpp.

This file still only has my name on the copyright notice even though
most of the code (likely more than 90% of it) was authored by various
contributors -- It doesn't seem right to have the whole file
attributed to myself.

Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Serge Martin <edb+mesa@sigluy.net>

i965: Print EOT in fs_visitor::dump_instruction().

This was useful when debugging the previous commit's issue.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Make emit_urb_writes() not produce an EOT message for GS.

emit_urb_writes() contains code to emit an EOT write with no actual
data when there are no output varyings.  This makes sense for the VS
and TES stages, where it's called once at the end of the program.

However, in the geometry shader stage, emit_urb_writes() is called once
for every EmitVertex().  We explicitly emit a URB write with EOT set at
the end of the shader, separately from this path.  So we'd better not
terminate the thread.  This could get us into trouble for shaders which
do EmitVertex() with no varyings followed by SSBO/image/atomic writes.

It also caused us to emit multiple sends with EOT set, which apparently
confuses the register allocator into not using g112-g127 for all but
the first one.  This caused EU validation failures in OglGSCloth
shaders in shader-db.  (The actual application was fine, but shader-db
thinks there are no outputs because it doesn't understand transform
feedback.)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

glsl: Ignore ir_texture in lower_const_arrays_to_uniforms.

The only part of an ir_texture which can be an array is the
offsets array in textureGatherOffsets() calls.  We don't want
to lower those, because they're required to remain constants.

Fixes textureGatherOffsets with Gallium drivers such as llvmpipe,
which commit ef78df8d3b0cf540e5f08c8c2f6caa338b64a6c7 regressed.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: add missing setcond flags for LOP variants

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

gm107/ir: make use of LOP32I for all immediates

LOP only allows to emit 19-bits immediates.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

virgl: reduce some limits for now

These need to be passed from the host in caps structure if they
are larger, this fixes a bunch of tests on Intel hw, that I'd
put the limits too high for.

Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/omx: count number of slices

Used by nouveau driver.
Similar patch was done for st/va:
851e7e12aa628d6781b5a3af2f2fc16ee73f435f

Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/omx: add support for nouveau / interlaced

Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/omx: retrieve preferred interlaced and buffer_formats

Interlaced can be true for nouveau driver.

Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi: use optimal WD settings for primitive restart on Polaris

ported from Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/va: Check NULL pointer

Call to handle_table_get in vlVaDestroySurfaces can
return NULL on failure.

CID: 1243522

Signed-off-by: Gurkirpal Singh <gurkirpal204@gmail.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>

nir: Fix copy_prop_src when src is an indirect access on a reg.

The intent was to continue down the indirect chain, not to call ourselves
with unchanged input arguments.  Found by code inspection, and comparison
to copy_prop_alu_src().

We haven't hit this because callers of NIR's copy prop are doing so in
SSA, before indirect variable dereferences have been lowered to registers.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

gm107/ir: make use of MOV32I for all immediates

MOV only allows to emit 19-bits immediates. This is similar to the
previous fix I did for IMUL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

i965: Use miptree to decide format on multi-plane images for gen < 7

This wasn't handled correctly for multi-plane images on gen < 7 in
727a9b24933d384f5440ed4318fb720ed11d6dd1.

Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96674
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nvc0: update "derived" state function names

derived_1/2/etc aren't too informative. Instead name them based on the
state they're derived from.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: provide support for unscaled poly offset units

On at least Kepler hardware, the units differ based on RT format. Emit a
properly scaled value for Z16 depth buffers vs other formats, to help
out st/nine.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: make use of IMUL32I for all immediates

IMUL only allows to emit 19-bits immediates. This is similar to
d30768025a2283d4cc57930b784798bf278969da which fixed the same thing
for the GK110 emitter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

radeonsi: make si_is_format_supported static

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: boolean -> bool, TRUE -> true, FALSE -> false

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> false

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> false

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: use r600_resource_reference

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nir: Add a NIR_VALIDATE environment variable

It defaults to true so default behavior doesn't change but it allows you to
do NIR_VALIDATE=false if you don't want validation.  Disabling validation
can substantially speed up shader compiles so you frequently want to turn
it off if compiler invariants aren't in question.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>

st/nine: Use offset_units_unscaled

offset_units_unscaled enables proper support
for depth bias for gallium nine. Use it
if available.

Solves issues with some games using depth bias.
For example:
https://github.com/iXit/Mesa-3D/issues/220

Signed-off-by: Axel Davy <axel.davy@ens.fr>

r600g: Implement POLYGON_OFFSET_UNITS_UNSCALED

Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.

PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALED

Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.

PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeon: Remove useless pa_su_poly_offset_db_fmt_cntl

pa_su_poly_offset_db_fmt_cntl usages were removed in
previous patches.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for evergreen

Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.

v2: Increase the num_dw field for the poly offset atom

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600

Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.

v2: Increase the num_dw field for the poly offset atom

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states

Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with rasterizer poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: Add a cap for offset_units_unscaled

D3D9 has a different behaviour for depth bias.

For OGL/D3D1X, the depth bias unit is the
minimal resolvable value for the depth buffer,
which depends on the format (and has different
behaviour for float depth buffers).

For D3D9, the depth bias unit is 1.0f.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Skip update_texture_surface when the plane doesn't exist

Reported-by: Grazvydas Ignotas <notasas@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96607
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chad Versace <chad.versace@intel.com>

i965: Validate a few SEND-from-GRF requirements.

We recently had a mistake where we emitted SEND instructions with EOT
set, but from g107 rather than g112-g127.  Adding validation code should
prevent these sorts of problems from slipping back in.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Delete send-from-GRF only opcodes from implied_mrf_writes().

These only exist post-Sandybridge, and always use send-from-GRF.
So inst->base_mrf will be -1, and we will have already returned 0.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Drop unnecessary inst->base_mrf = -1 assignments.

These are now unnecessary, as base_mrf is -1 by default.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Set fs_inst::base_mrf = -1 by default.

On MRF platforms, we need to set base_mrf to the first MRF value we'd
like to use for the message.  On send-from-GRF platforms, we set it to
-1 to indicate that the operation doesn't use MRFs.

As MRF platforms are becoming increasingly a thing of the past, we've
forgotten to bother with this.  It makes more sense to set it to -1 by
default, so we don't have to think about it for new code.

I searched the code for every instance of 'mlen =' in brw_fs*cpp, and
it appears that all MRF-based messages correctly program a base_mrf.

Forgetting to set base_mrf = -1 can confuse the register allocator,
causing it to think we have a large fake-MRF region.  This ends up
moving the send-with-EOT registers earlier, sometimes even out of
the g112-g127 range, which is illegal.  For example, this fixes
illegal sends in Piglit's arb_gpu_shader_fp64-layout-std430-fp64-shader,
which had SSBO messages with mlen > 0 but base_mrf == 0.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Drop unused return value from intel_finalize_mipmap_tree().

The old return type of GLuint was wonky - it should have been bool.
But nothing actually uses the return value anyway, so we can just drop
that and make it a void function.

In theory, it might make sense to ask whether the texture validated
successfully, but just checking intel_obj->mt != NULL works for that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move contents of brw_tex.c into intel_tex_validate.c.

brw_tex.c is a tiny file containing a single function.  It's closely
tied to the validation logic in intel_tex_validate.c, so it makes sense
to put both in the same file.

While we're at it, update the function to our modern style.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

radeonsi: fix fractional odd tessellation spacing for Polaris

ported from Vulkan (and no source explains why this is needed)

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set some VGT context registers on SI-CI

the kernel sets them, but other UMDs can change them

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: optimize rendering to linear color buffers

loosely ported from Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set almost optimal settings in SC_MODE_CNTL_1

ported from Vulkan

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: let drivers specify SC_MODE_CNTL_1 fields

radeonsi will set more fields

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: disable complicated point clipping against user clip planes

Nothing in the GL spec says that we should expand points to triangles.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix a compute shader hang with big threadgroups on SI & CI

ported from Vulkan

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nvc0: when mapping directly, provide accurate xfer info + start

We were ignoring the incoming box parameters, and were providing totally
bogus stride/layer stride, and other bits, for when a non-full-surface
map was requested.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>

st/mesa: don't assume that the whole surface gets mapped

Under some circumstances, the driver may choose to return a temporary
surface instead of a pointer to the original. Make sure to pass the
actual view volume to be mapped to the transfer function rather than
adjusting the map pointer after-the-fact.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: drop the DRAW_PREAMBLE packet on Polaris

It will be removed from the firmware for the Polaris.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use DRAW_(INDEX_)INDIRECT_MULTI on Polaris

The non-MULTI variants will be removed in Polaris firmware.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: handle negative _ColorDrawBufferIndexes values correctly

Signed-off-by: Marek Olšák <marek.olsak@amd.com>

winsys/radeon: add guard pages when R600_DEBUG=check_vm is enabled

This should help flush out GPU VM faults.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/amdgpu: add guard pages when R600_DEBUG=check_vm is enabled

This should help flush out GPU VM faults.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: report a failure to parse dmesg instead of asserting

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeon: check VM faults from DMA flush

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: move gfx fence wait out of si_check_vm_faults

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: extract IB and bo list saving into separate functions

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: fix readpixels regression with MESA_pack_invert

Fixes an error introduced in commit 3948cd37973696dc319170877382676809659465.

Reported-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: set LLVM denormal flags

- make sure FP32 denormals will stay disabled in LLVM in the future
  (the current default is disabled)
- tell LLVM that FP64 denormals are enabled

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: emit 1/sqrt for RSQ

We don't need the clamped version and we don't have to use any intrinsic.

Stats on Tonga:

15382 shaders in 9128 tests
Totals:
SGPRS: 1230560 -> 1230560 (0.00 %)
VGPRS: 469577 -> 462504 (-1.51 %)
Code Size: 22089908 -> 21730052 (-1.63 %) bytes
LDS: 598 -> 598 (0.00 %) blocks
Scratch: 283648 -> 281600 (-0.72 %) bytes per wave
Max Waves: 125664 -> 126969 (1.04 %)
Wait states: 0 -> 0 (0.00 %)

Totals from affected shaders:
SGPRS: 547280 -> 547280 (0.00 %)
VGPRS: 269132 -> 262059 (-2.63 %)
Code Size: 15709604 -> 15349748 (-2.29 %) bytes
LDS: 198 -> 198 (0.00 %) blocks
Scratch: 74752 -> 72704 (-2.74 %) bytes per wave
Max Waves: 47840 -> 49145 (2.73 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g: Enable FMA on chips that support it

v2: Merge with PIPE_SHADER_CAP_DOUBLES
    Add CHIP_HEMLOCK

v3: only set the instruction on EG and CM

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

gallium/u_queue: allow the execute function to differ per job

so that independent types of jobs can use the same queue.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/u_queue: reduce the number of mutexes by 2

by converting semaphores to condvars and using the main mutex

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>