OSDN Git Service
Tim Northover [Thu, 8 May 2014 10:30:56 +0000 (10:30 +0000)]
ARM64: make sure FastISel emits SSA MachineInstrs
We need to use a temporary register for a 2-step operation like REM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297
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Evgeniy Stepanov [Thu, 8 May 2014 09:55:24 +0000 (09:55 +0000)]
[asan] Preserve flags in asm instrumentation.
Patch by Yuri Gorshenin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208296
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Daniel Sanders [Thu, 8 May 2014 09:29:28 +0000 (09:29 +0000)]
Use a vector of unique_ptrs to fix a memory leak introduced in r208179.
Also removed an inaccurate comment that stated that a DenseMap was used as
storage for the ListInit*'s. It's currently using a FoldingSet.
I expect there's a better way to fix this but I haven't found it yet. FoldingSet
is incompatible with the Pool template and I'm not sure if FoldingSet can be
safely replaced with a DenseMap of computed FoldingSetID's to ListInit*'s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208293
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Hal Finkel [Thu, 8 May 2014 09:14:44 +0000 (09:14 +0000)]
Move late partial-unrolling thresholds into the processor definitions
The old method used by X86TTI to determine partial-unrolling thresholds was
messy (because it worked by testing target features), and also would not
correctly identify the target CPU if certain target features were disabled.
After some discussions on IRC with Chandler et al., it was decided that the
processor scheduling models were the right containers for this information
(because it is often tied to special uop dispatch-buffer sizes).
This does represent a small functionality change:
- For generic x86-64 (which uses the SB model and, thus, will get some
unrolling).
- For AMD cores (because they still currently use the SB scheduling model)
- For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump
the default threshold to 50; we're working on a test case for this).
Otherwise, nothing has changed for any other targets. The logic, however, has
been moved into BasicTTI, so other targets may now also opt-in to this
functionality simply by setting LoopMicroOpBufferSize in their processor
model definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208289
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Tobias Grosser [Thu, 8 May 2014 07:55:34 +0000 (07:55 +0000)]
Revert "SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time"
as committed in r208282. The original commit was incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208286
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Hao Liu [Thu, 8 May 2014 07:38:13 +0000 (07:38 +0000)]
AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208284
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Tobias Grosser [Thu, 8 May 2014 07:12:44 +0000 (07:12 +0000)]
SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208282
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Richard Smith [Thu, 8 May 2014 02:34:32 +0000 (02:34 +0000)]
[modules] Add missing #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208276
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Saleem Abdulrasool [Thu, 8 May 2014 01:41:04 +0000 (01:41 +0000)]
test: fix silly typo
Oh silly Darwin and your case insensitive file system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208274
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Saleem Abdulrasool [Thu, 8 May 2014 01:35:57 +0000 (01:35 +0000)]
ARM: support FK_SecRel_2 relocations on WoA
This adds FK_SecRel_2 relocation support to ARM. This enables the building of
object files for armv7-windows-msvc which enables CodeView line tables for
debugging as opposed to armv7-windows-itanium which currently uses DWARF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208273
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Richard Smith [Thu, 8 May 2014 01:08:43 +0000 (01:08 +0000)]
Simplify and fix incorrect comment. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208272
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Filipe Cabecinhas [Thu, 8 May 2014 00:25:16 +0000 (00:25 +0000)]
Lower certain build_vectors to insertps instructions
Summary:
Vectors built with zeros and elements in the same order as another
(source) vector are optimized to be built using a single insertps
instruction.
Also optimize when we move one element in a vector to a different place
in that vector while zeroing out some of the other elements.
Further optimizations are possible, described in TODO comments.
I will be implementing at least some of them in the near future.
Added some tests for different cases where this optimization triggers.
Reviewers: nadav, delena, craig.topper
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D3521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208271
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Lang Hames [Wed, 7 May 2014 23:35:53 +0000 (23:35 +0000)]
Back out r208257 while I investigate tester failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208267
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Duncan P. N. Exon Smith [Wed, 7 May 2014 23:00:22 +0000 (23:00 +0000)]
GlobalValue: Assert symbols with local linkage have default visibility
The change to ExtractGV.cpp has no functionality change except to avoid
the asserts. Existing testcases already cover this, so I didn't add a
new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208264
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Duncan P. N. Exon Smith [Wed, 7 May 2014 22:57:20 +0000 (22:57 +0000)]
IR: Don't allow non-default visibility on local linkage
Visibilities of `hidden` and `protected` are meaningless for symbols
with local linkage.
- Change the assembler to reject non-default visibility on symbols
with local linkage.
- Change the bitcode reader to auto-upgrade `hidden` and `protected`
to `default` when the linkage is local.
- Update LangRef.
<rdar://problem/
16141113>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208263
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Duncan P. N. Exon Smith [Wed, 7 May 2014 22:55:46 +0000 (22:55 +0000)]
LTO: Assert visibility of local linkage when merging symbols
`ModuleLinker::getLinkageResult()` shouldn't create symbols with local
linkage and non-default visibility -- in fact, symbols with local
linkage shouldn't be merged at all. Assert to that effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208262
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Duncan P. N. Exon Smith [Wed, 7 May 2014 22:53:14 +0000 (22:53 +0000)]
LTO: Check local linkage first
Since visibility is meaningless for symbols with local linkage, check
local linkage before visibility when setting symbol attributes.
When linkage is `internal` and the visibility is `hidden`, the exposed
attribute is now `LTO_SYMBOL_SCOPE_INTERNAL` instead of
`LTO_SYMBOL_SCOPE_HIDDEN`. Although the bitfield allows *both* to be
specified, the combination is nonsense anyway.
Given changes (in progress) to drop visibility when a symbol has local
linkage, this almost has no functionality change: it's mostly a cleanup
to clarify the logic.
The exception is when something has `appending` linkage. Before this
change, such symbols would be advertised as `LTO_SYMBOL_SCOPE_INTERNAL`;
now, they'll be given `LTO_SYMBOL_SCOPE_COMMON`.
Unfortunately this is really awkward to test. This only changes what we
advertise to linkers (before running LTO), not what the final object
looks like. In theory I could add `DEBUG` output to `llvm-lto` (and
test with "REQUIRES: asserts"), but follow-up commits to disallow
`internal hidden` simplify this anyway.
<rdar://problem/
16141113>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208261
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Quentin Colombet [Wed, 7 May 2014 22:52:58 +0000 (22:52 +0000)]
[X86] Add a test case for r208252.
Prior to r208252, the FMA 231 family was marked as isCommutable. However the
memory variants of this family are not commutable. Therefore, we did not
implemented the findCommutedOpIndices for those variants and missed that
the default implementation (more or less: commute indices 1 and 2) was
firing behind our back.
As a result, as demonstrated in the test case before the fix, we were
transforming a = b * c + a into a = a * c + b.
I.e., before r208252 we were generating for this test case:
vmovaps %xmm0, %xmm1
vmoss (%rsi), %xmm0
vfmadd231ss (%rdi), %xmm1, %xmm0
Instead of:
vmoss (%rsi), %xmm1
vfmadd231ss (%rdi), %xmm1, %xmm0
<rdar://problem/
16800495>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208260
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Lang Hames [Wed, 7 May 2014 22:34:08 +0000 (22:34 +0000)]
[RuntimeDyld] Make RuntimeDyldImpl::resolveExternalSymbols preserve the
relocation entries it applies.
Prior to this patch, RuntimeDyldImpl::resolveExternalSymbols discarded
relocations for external symbols once they had been applied. This causes issues
if the client calls MCJIT::finalizeLoadedModules more than once, and updates the
location of any symbols in between (e.g. by calling MCJIT::mapSectionAddress).
No test case yet: None of our in-tree memory managers support moving sections
around. I'll have to hack up a dummy memory manager before I can write a unit
test.
Fixes <rdar://problem/
16764378>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208257
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Hal Finkel [Wed, 7 May 2014 22:25:18 +0000 (22:25 +0000)]
[X86TTI] Remove the unrolling branch limits
The loop stream detector (LSD) on modern Intel cores, which optimizes the
execution of small loops, has limits on the number of taken branches in
addition to uop-count limits (modern AMD cores have similar limits).
Unfortunately, at the IR level, estimating the number of branches that will be
taken is difficult. For one thing, it strongly depends on later passes (block
placement, etc.). The original implementation took a conservative approach and
limited the maximal BB DFS depth of the loop. However, fairly-extensive
benchmarking by several of us has revealed that this is the wrong approach. In
fact, there are zero known cases where the branch limit prevents a detrimental
unrolling (but plenty of cases where it does prevent beneficial unrolling).
While we could improve the current branch counting logic by incorporating
branch probabilities, this further complication seems unjustified without a
motivating regression. Instead, unless and until a regression appears, the
branch counting will be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208255
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Justin Bogner [Wed, 7 May 2014 21:50:43 +0000 (21:50 +0000)]
llvm-cov: Fix some funny indentation (NFC)
Noticed by Duncan Exon Smith. Thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208253
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Quentin Colombet [Wed, 7 May 2014 21:43:35 +0000 (21:43 +0000)]
[X86] Selectively mark the FMA variants inside a family as isCommutable.
Given a FMA family (e.g., 213, 231), not all the variants (i.e., register or
memory) are commutable.
E.g., for the 213 family (with the syntax src1, src2, src3):
fmaXXX213 A, B, reg3/mem3 == fmaXXX213 B, A, reg3/mem3
Now consider the 231 family:
fmaXXX231 A, B, reg3 == fmaXXX231 A, reg3, B
But
fmaXXX231 A, B, mem3 != fmaXXX231 A, mem3, B
Indeed, mem3 cannot be the second argument of the memory variant of fmaXXX231.
Working on a reduced test case!
<rdar://problem/
16800495>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208252
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Eric Christopher [Wed, 7 May 2014 21:05:47 +0000 (21:05 +0000)]
Reformat a couple of functions for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208248
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Nico Weber [Wed, 7 May 2014 19:55:38 +0000 (19:55 +0000)]
Let OnDiskHashTable call the destructor of its Items.
OnDiskHashTable::insert() calls the Item constructor via placement new, but
nothing called the destructor. This matters in cases when the Info template
parameter has key_type or data_type typedefs that have a destructor, for
example like IdentifierIndexWriterTrait in clang's GlobalModuleIndex.cpp.
This fixes a 5-year old bug that's been around since the OnDiskHashTable code
was added in r64192. Bug found by LSan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208243
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Rafael Espindola [Wed, 7 May 2014 19:52:32 +0000 (19:52 +0000)]
Replace a virtual with an override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208242
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Jyotsna Verma [Wed, 7 May 2014 19:07:34 +0000 (19:07 +0000)]
[Hexagon] Add New TSFlags to be used in the upcoming patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208239
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Sebastian Pop [Wed, 7 May 2014 19:00:37 +0000 (19:00 +0000)]
avoid segfaulting
*Quotient and *Remainder don't have to be initialized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208238
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Sebastian Pop [Wed, 7 May 2014 19:00:32 +0000 (19:00 +0000)]
do not collect undef terms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208237
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Matt Arsenault [Wed, 7 May 2014 18:26:58 +0000 (18:26 +0000)]
Fix using wrong result type for setcc.
When reducing the bitwidth of a comparison against a constant, the
original setcc's result type was used, which was incorrect.
No test since I don't think any other in tree targets change the
bitwidth of the setcc type depending on the bitwidth of the compared
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208236
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Eric Christopher [Wed, 7 May 2014 18:19:04 +0000 (18:19 +0000)]
Debug.h already includes raw_ostream.h, no need to include it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208235
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Adam Nemet [Wed, 7 May 2014 18:16:02 +0000 (18:16 +0000)]
[Test] Remove c-index-test from the list of substitutions
All the tests are under the clang tests and none should be under llvm moving
forward.
The topic was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-
20140428/214905.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208234
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Sebastian Pop [Wed, 7 May 2014 18:01:20 +0000 (18:01 +0000)]
split delinearization pass in 3 steps
To compute the dimensions of the array in a unique way, we split the
delinearization analysis in three steps:
- find parametric terms in all memory access functions
- compute the array dimensions from the set of terms
- compute the delinearized access functions for each dimension
The first step is executed on all the memory access functions such that we
gather all the patterns in which an array is accessed. The second step reduces
all this information in a unique description of the sizes of the array. The
third step is delinearizing each memory access function following the common
description of the shape of the array computed in step 2.
This rewrite of the delinearization pass also solves a problem we had with the
previous implementation: because the previous algorithm was by induction on the
structure of the SCEV, it would not correctly recognize the shape of the array
when the memory access was not following the nesting of the loops: for example,
see polly/test/ScopInfo/multidim_only_ivs_3d_reverse.ll
; void foo(long n, long m, long o, double A[n][m][o]) {
;
; for (long i = 0; i < n; i++)
; for (long j = 0; j < m; j++)
; for (long k = 0; k < o; k++)
; A[i][k][j] = 1.0;
Starting with this patch we no longer delinearize access functions that do not
contain parameters, for example in test/Analysis/DependenceAnalysis/GCD.ll
;; for (long int i = 0; i < 100; i++)
;; for (long int j = 0; j < 100; j++) {
;; A[2*i - 4*j] = i;
;; *B++ = A[6*i + 8*j];
these accesses will not be delinearized as the upper bound of the loops are
constants, and their access functions do not contain SCEVUnknown parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208232
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Chandler Carruth [Wed, 7 May 2014 17:37:03 +0000 (17:37 +0000)]
[x86] Make the 'x86-64' cpu, what I see as and many use as the generic
default architecture for reasonable modern x86 processors, actually be
modern. This processor model should essentially be "tuned" for modern
x86 chips as much as possible without undue penalties on any specific
architecture. Previously we weren't even using the nice scheduling
models. There are a few other tweaks needed here, but this change at
least I have benchmarked across a decent swatch of chips (intel's
clovertown, westmere, and sandybridge; amd's istanbul) and seen no
significant regressions.
If anyone has suggested ways to test this, just let me know. Somewhat
alarmingly, no existing tests failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208230
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Chandler Carruth [Wed, 7 May 2014 17:36:59 +0000 (17:36 +0000)]
Tidy up whitespace with clang-format prior to making significant
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208229
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Simon Atanasyan [Wed, 7 May 2014 17:06:38 +0000 (17:06 +0000)]
[yaml2obj] Support ELF x86 relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208228
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Rafael Espindola [Wed, 7 May 2014 17:04:45 +0000 (17:04 +0000)]
Style update: don't duplicate the function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208227
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Alexey Samsonov [Wed, 7 May 2014 16:54:00 +0000 (16:54 +0000)]
[CMake] Add build rules for llvm-PerfectShuffle utility
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208225
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Rafael Espindola [Wed, 7 May 2014 16:43:23 +0000 (16:43 +0000)]
Style update: don't duplicate the function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208224
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Chad Rosier [Wed, 7 May 2014 16:41:55 +0000 (16:41 +0000)]
[ARM64][fast-isel] Disable target specific optimizations at -O0. Functionally,
this patch disables the dead register elimination pass and the load/store pair
optimization pass at -O0. The ILP optimizations don't require the optimization
level to be checked because the call to addILPOpts is predicated with the
necessary check. The AdvSIMDScalar pass is disabled by default at all
optimization levels. This patch leaves that pass disabled by default.
Also, move command-line options into ARM64TargetMachine.cpp and add a few
additional flags to aid in debugging. This fixes an issue with the
-debug-pass=Structure flag where passes were printed, but not actually run
(i.e., AdvSIMDScalar pass).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208223
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Daniel Sanders [Wed, 7 May 2014 16:25:22 +0000 (16:25 +0000)]
[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).
The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.
Reviewers: vmedic
Subscribers: emaste, llvm-commits
Differential Revision: http://reviews.llvm.org/D3569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208221
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Justin Bogner [Wed, 7 May 2014 16:01:27 +0000 (16:01 +0000)]
llvm-cov: Explicitly namespace llvm::make_unique to keep MSVC happy
This is a followup to r208171, where a call to make_unique was
disambiguated for MSVC. Disambiguate two more calls, and remove the
comment about it since this is what we do everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208219
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Rafael Espindola [Wed, 7 May 2014 14:53:32 +0000 (14:53 +0000)]
Use range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208218
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Michael Zolotukhin [Wed, 7 May 2014 14:30:18 +0000 (14:30 +0000)]
[InstCombine] Add optimization of redundant insertvalue instructions.
rdar://problem/
11861387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208214
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Daniel Sanders [Wed, 7 May 2014 14:25:43 +0000 (14:25 +0000)]
[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates
Summary:
No functional change (confirmed by diffing tablegen-erated files).
Depends on D3642
Reviewers: vmedic, dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208213
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Daniel Sanders [Wed, 7 May 2014 14:11:46 +0000 (14:11 +0000)]
[mips] Add INSN_<name> adverbs and start using them instead of AdditionalPredicates overrides
Summary:
No functional change
Depends on D3641
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208212
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Evgeniy Stepanov [Wed, 7 May 2014 14:10:51 +0000 (14:10 +0000)]
[msan] Fix -fsanitize=memory -fno-integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208211
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Tim Northover [Wed, 7 May 2014 14:10:27 +0000 (14:10 +0000)]
AArch64/ARM64: optimise vector selects & enable test
When performing a scalar comparison that feeds into a vector select,
it's actually better to do the comparison on the vector side: the
scalar route would be "CMP -> CSEL -> DUP", the vector is "CM -> DUP"
since the vector comparisons are all mask based.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208210
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Daniel Sanders [Wed, 7 May 2014 13:57:22 +0000 (13:57 +0000)]
[mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides
Summary:
One small functional change. The recently added PAUSE instruction now has
the HasStdEnc predicate which was accidentally removed by a Requires<>.
Depends on D3640
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208209
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Rafael Espindola [Wed, 7 May 2014 13:00:43 +0000 (13:00 +0000)]
Remove the UseCFI option from createAsmStreamer.
We were already always passing true, this just removes the option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208205
91177308-0d34-0410-b5e6-
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Ed Maste [Wed, 7 May 2014 12:49:08 +0000 (12:49 +0000)]
DebugInfo: Use enum instead of unsigned
This makes debuging DebugInfo generation with LLDB a little more pleasant.
Differential Revision: http://reviews.llvm.org/D3626
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208202
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Daniel Sanders [Wed, 7 May 2014 12:48:37 +0000 (12:48 +0000)]
[mips] Continue splitting Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates
No functional change (confirmed by diffing tablegen-erated files).
Depends on D3639
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208201
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James Molloy [Wed, 7 May 2014 12:33:55 +0000 (12:33 +0000)]
[ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208200
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James Molloy [Wed, 7 May 2014 12:33:48 +0000 (12:33 +0000)]
[ARM64-BE] Fix variable-argument saving.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208199
91177308-0d34-0410-b5e6-
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James Molloy [Wed, 7 May 2014 12:33:41 +0000 (12:33 +0000)]
[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
The AAPCS states that values passed in registers must have a value as though
they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is,
loading scalars to vector registers and loading 1-element vectors is equivalent.
The logic implemented here is to ensure that at all call boundaries and during
formal argument lowering all vectors are treated as their bitwidth-based floating
point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64,
v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be
generated during code generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208198
91177308-0d34-0410-b5e6-
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Daniel Sanders [Wed, 7 May 2014 12:27:46 +0000 (12:27 +0000)]
[mips] Move IsFP64bit/NotFP64bit to the front of the AdditionalPredicates list
Summary:
This makes it easier to prove a more complicated change in the next commit
is non-functional.
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208197
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James Molloy [Wed, 7 May 2014 11:28:53 +0000 (11:28 +0000)]
[ARM64-BE] Implement the crazy bitcast handling for big endian vectors.
Because we've canonicalised on using LD1/ST1, every time we do a bitcast
between vector types we must do an equivalent lane reversal.
Consider a simple memory load followed by a bitconvert then a store.
v0 = load v2i32
v1 = BITCAST v2i32 v0 to v4i16
store v4i16 v2
In big endian mode every memory access has an implicit byte swap. LDR and
STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
is, they treat the vector as a sequence of elements to be byte-swapped.
The two pairs of instructions are fundamentally incompatible. We've decided
to use LD1/ST1 only to simplify compiler implementation.
LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
the original code sequence: v0 = load v2i32
v1 = REV v2i32 (implicit)
v2 = BITCAST v2i32 v1 to v4i16
v3 = REV v4i16 v2 (implicit)
store v4i16 v3
But this is now broken - the value stored is different to the value loaded
due to lane reordering. To fix this, on every BITCAST we must perform two
other REVs:
v0 = load v2i32
v1 = REV v2i32 (implicit)
v2 = REV v2i32
v3 = BITCAST v2i32 v2 to v4i16
v4 = REV v4i16
v5 = REV v4i16 v4 (implicit)
store v4i16 v5
This means an extra two instructions, but actually in most cases the two REV
instructions can be combined into one. For example:
(REV64_2s (REV64_4h X)) === (REV32_4h X)
There is also no 128-bit REV instruction. This must be synthesized with an
EXT instruction.
Most bitconverts require some sort of conversion. The only exceptions are:
a) Identity conversions - vNfX <-> vNiX
b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
Even though there are hundreds of changed lines, I have a fairly high confidence
that they are somewhat correct. The changes to add two REV instructions per
bitcast were pretty mechanical, and once I'd done that I threw the resulting
.td at a script I wrote which combined the two REVs together (and added
an EXT instruction, for f128) based on an instruction description I gave it.
This was much less prone to error than doing it all manually, plus my brain
would not just have melted but would have vapourised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208194
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James Molloy [Wed, 7 May 2014 11:28:45 +0000 (11:28 +0000)]
[ARM64-BE] Predicate VLDR/VSTR for vectors as little-endian only. We must use LD1/ST1 on big-endian.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208193
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James Molloy [Wed, 7 May 2014 11:28:36 +0000 (11:28 +0000)]
[ARM64-BE] Make big endian (scalar) argument passing work correctly.
This completes the port of r204814 (cpirker "AArch64_BE function argument
passing for ARM ABI") from AArch64 to ARM64, and fixes a bunch of issues
found during later development along the way. The biggest of these was
that the alignment fixup logic wasn't replicated into all the places it
should have been.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208192
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Stepan Dyatkovskiy [Wed, 7 May 2014 11:11:39 +0000 (11:11 +0000)]
MergeFunctions Pass, introduced total ordering among values.
This is a third patch of patch series that improves MergeFunctions
performance time from O(N*N) to O(N*log(N)).
This patch description:
Being comparing functions we need to compare values we meet at left and
right sides.
Its easy to sort things out for external values. It just should be
the same value at left and right.
But for local values (those were introduced inside function body)
we have to ensure they were introduced at exactly the same place,
and plays the same role.
In short, patch introduces values serial numbering and comparison routine.
The last one compares two values by their serial numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208189
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Tim Northover [Wed, 7 May 2014 10:47:04 +0000 (10:47 +0000)]
AArch64/ARM64: run test on ARM64 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208188
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Tim Northover [Wed, 7 May 2014 10:47:00 +0000 (10:47 +0000)]
AArch64/ARM64: put annotation in test
It makes finding already covered tests much easier with "grep -L
arm64".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208187
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Tim Northover [Wed, 7 May 2014 10:42:06 +0000 (10:42 +0000)]
AArch64/ARM64: disable test directory if ARM64 not present
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208186
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Daniel Sanders [Wed, 7 May 2014 10:27:09 +0000 (10:27 +0000)]
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.
This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.
It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.
No functional change (confirmed by diffing tablegen-erated files).
Depends on D3549, D3506
Reviewers: vmedic
Differential Revision: http://reviews.llvm.org/D3550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208184
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Daniel Sanders [Wed, 7 May 2014 10:13:19 +0000 (10:13 +0000)]
[tablegen] Add !listconcat operator with the similar semantics as !strconcat
Summary:
It concatenates two or more lists. In addition to the !strconcat semantics
the lists must have the same element type.
My overall aim is to make it easy to append to Instruction.Predicates
rather than override it. This can be done by concatenating lists passed as
arguments, or by concatenating lists passed in additional fields.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: hfinkel, llvm-commits
Differential Revision: http://reviews.llvm.org/D3506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208183
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Daniel Sanders [Wed, 7 May 2014 09:58:05 +0000 (09:58 +0000)]
[mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.
No functional change.
Depends on D3506
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208179
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Zinovy Nis [Wed, 7 May 2014 09:51:22 +0000 (09:51 +0000)]
[BUG][REFACTOR]
1) Fix for printing debug locations for absolute paths.
2) Location printing is moved into public method DebugLoc::print() to avoid re-inventing the wheel.
Differential Revision: http://reviews.llvm.org/D3513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208177
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Stepan Dyatkovskiy [Wed, 7 May 2014 09:05:10 +0000 (09:05 +0000)]
Second patch of patch series that improves MergeFunctions performance time from O(N*N) to
O(N*log(N)). The idea is to introduce total ordering among functions set.
It allows to build binary tree and perform function look-up procedure in O(log(N)) time.
This patch description:
Introduced total ordering among constants implemented in cmpConstants method.
Method performs lexicographical comparison between constants represented as
hypothetical numbers of next format:
<bitcastability-trait><raw-bit-contents>
Please, read cmpConstants declaration comments for more details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208173
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Timur Iskhodzhanov [Wed, 7 May 2014 08:52:13 +0000 (08:52 +0000)]
Work-around MSVS build breakage due to r208148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208171
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Evgeniy Stepanov [Wed, 7 May 2014 07:54:11 +0000 (07:54 +0000)]
[asan] Add a flag to control asm instrumentation.
With this change, asm instrumentation is disabled by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208167
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Joerg Sonnenberger [Wed, 7 May 2014 07:49:34 +0000 (07:49 +0000)]
Allow using normal .eh_frame based unwinding on ARM. Use the same
encodings as x86. Use this exception model for NetBSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208166
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David Blaikie [Wed, 7 May 2014 06:08:28 +0000 (06:08 +0000)]
PR19562: DebugInfo temporary MDNode leak: Don't include a temporary node to replace with a variable list for methods, since they're always declarations and thus never include variables
This field is used for a list of variables to ensure they are not lost
during optimization (they're only included when optimizations are
enabled).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208159
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Tobias Grosser [Wed, 7 May 2014 06:07:47 +0000 (06:07 +0000)]
[C++11] Add NArySCEV->Operands iterator range
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208158
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Simon Atanasyan [Wed, 7 May 2014 05:18:51 +0000 (05:18 +0000)]
[obj2yaml] Recognize input file format using llvm::object::ObjectFile
interface methods isCOFF().
The '-coff' command line option has been removed. It was not used in any
test cases.
The patch reviewed by Michael Spencer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208157
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Saleem Abdulrasool [Wed, 7 May 2014 03:03:31 +0000 (03:03 +0000)]
ARM: mark additional instructions as MachineFrameSetup
Mark up additional instructions which are part of the function prologue as
MachineFrameSetup. These instructions are part of the function prologue,
emitted by the PEI pass to setup the stack for use in the activating frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208153
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Saleem Abdulrasool [Wed, 7 May 2014 03:03:27 +0000 (03:03 +0000)]
ARM: fix WoA PEI instruction selection
The ARM::BLX instruction is an ARM mode instruction. The Windows on ARM target
is limited to Thumb instructions. Correctly use the thumb mode tBLXr
instruction. This would manifest as an errant write into the object file as the
instruction is 4-bytes in length rather than 2. The result would be a corrupted
object file that would eventually result in an executable that would crash at
runtime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208152
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Justin Bogner [Wed, 7 May 2014 02:33:58 +0000 (02:33 +0000)]
llvm-cov: Document --no-output in the command guide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208151
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Justin Bogner [Wed, 7 May 2014 02:11:23 +0000 (02:11 +0000)]
llvm-cov: Handle missing source files as GCOV does
If the source files referenced by a gcno file are missing, gcov
outputs a coverage file where every line is simply /*EOF*/. This also
occurs for lines in the coverage that are past the end of a file that
is found.
This change mimics gcov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208149
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Justin Bogner [Wed, 7 May 2014 02:11:18 +0000 (02:11 +0000)]
llvm-cov: Implement --no-output
In gcov, there's a -n/--no-output option, which disables the writing
of any .gcov files, so that it emits only the summary info on stdout.
This implements the same behaviour in llvm-cov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208148
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Argyrios Kyrtzidis [Tue, 6 May 2014 23:30:56 +0000 (23:30 +0000)]
[Support/MemoryBuffer] Remove the assertion that the file size did not shrink.
This can happen in practice with the user changing files and we can recover from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208143
91177308-0d34-0410-b5e6-
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Nico Weber [Tue, 6 May 2014 23:17:26 +0000 (23:17 +0000)]
Fix ASan init function detection after clang r208128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208141
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Rafael Espindola [Tue, 6 May 2014 22:44:30 +0000 (22:44 +0000)]
Special case aliases in GlobalValue::getSection.
This is similar to the getAlignment patch, but is done just for
completeness. It looks like we never call getSection on an alias. All the
tests still pass if the if is replaced with an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208139
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Andrew Trick [Tue, 6 May 2014 22:18:43 +0000 (22:18 +0000)]
Update an embarassing out-of-date comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208137
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Eric Christopher [Tue, 6 May 2014 21:20:29 +0000 (21:20 +0000)]
Use a range based for loop for the SubtargetFeatures print function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208132
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David Blaikie [Tue, 6 May 2014 21:07:17 +0000 (21:07 +0000)]
Revert "Try simplifying LexicalScopes ownership again."
Speculatively reverting due to a suspicious failure on a Windows
buildbot.
This reverts commit
10c37a012ea11596d44cd9059fe09c959caf30c8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208131
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Eric Christopher [Tue, 6 May 2014 21:04:27 +0000 (21:04 +0000)]
Fix odd formatting that snuck into last patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208130
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Joerg Sonnenberger [Tue, 6 May 2014 20:43:01 +0000 (20:43 +0000)]
If a function needs a frame pointer, but r11 (aka fp) has not been used,
remove it from the list of unspilled registers. Otherwise the following
attempt to keep the stack aligned by picking an extra GPR register to
spill will not work as it picks up r11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208129
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 6 May 2014 20:23:04 +0000 (20:23 +0000)]
ArrayRef-ize the Feature and Processor tables for SubtargetFeatures.
This removes arguments passed everywhere and allows the use of
standard iteration over lists.
Should be no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208127
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Reid Kleckner [Tue, 6 May 2014 20:08:20 +0000 (20:08 +0000)]
Copy the full TailCallKind in CallInst::clone_impl
Split from the musttail inliner change. This will be covered by an opt
test when the inliner change lands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208126
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Diego Novillo [Tue, 6 May 2014 19:14:00 +0000 (19:14 +0000)]
Do not make -pass-remarks additive.
Summary:
When I initially introduced -pass-remarks, I thought it would be a
neat idea to make it additive. So, if one used it as:
$ llc -pass-remarks=inliner --pass-remarks=loop.*
the compiler would build the regular expression '(inliner)|(loop.*)'.
The more I think about it, the more I regret it. This is not how
other flags work. The standard semantics are right-to-left overrides.
This is how clang interprets -Rpass. And I think the two should be
compatible in this respect.
Reviewers: qcolombet
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D3614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208122
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Benjamin Kramer [Tue, 6 May 2014 18:36:23 +0000 (18:36 +0000)]
TTI: Estimate @llvm.fmuladd cost as fmul + fadd when FMA's aren't legal on the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208115
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Andrea Di Biagio [Tue, 6 May 2014 17:09:03 +0000 (17:09 +0000)]
[X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa).
Before this patch, the backend always emitted a store+load sequence to
bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that
performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting
i64 node was then used to build a v2i32 vector.
With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from
MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free"
bitcast to type MVT::v4i32. The elements of the resulting
v4i32 are then extracted to build a v2i32 vector (which is illegal and
therefore promoted to MVT::v2i64).
This is in general cheaper than emitting a stack store+load sequence
to bitconvert the operand from type f64 to type i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107
91177308-0d34-0410-b5e6-
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Renato Golin [Tue, 6 May 2014 16:51:25 +0000 (16:51 +0000)]
Implememting named register intrinsics
This patch implements the infrastructure to use named register constructs in
programs that need access to specific registers (bare metal, kernels, etc).
So far, only the stack pointer is supported as a technology preview, but as it
is, the intrinsic can already support all non-allocatable registers from any
architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 6 May 2014 16:48:58 +0000 (16:48 +0000)]
Special case aliases in GlobalValue::getAlignment.
An alias has the address of what it points to, so it also has the same
alignment.
This allows a few optimizations to see past aliases for free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208103
91177308-0d34-0410-b5e6-
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Eric Christopher [Tue, 6 May 2014 16:29:50 +0000 (16:29 +0000)]
Have the SubtargetFeature help routine just not return a number and
fall back to the normal path without a cpu. While doing this fix
llc to just exit when we don't have a module to process instead of
asserting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208102
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Bob Wilson [Tue, 6 May 2014 15:58:06 +0000 (15:58 +0000)]
Add some details to the llvm-cov documentation. <rdar://problem/
15819496>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208098
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Rafael Espindola [Tue, 6 May 2014 14:59:14 +0000 (14:59 +0000)]
Be more strict about not allowing setSection on aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208095
91177308-0d34-0410-b5e6-
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Rafael Espindola [Tue, 6 May 2014 14:51:36 +0000 (14:51 +0000)]
Be more strict about not calling setAlignment on global aliases.
The fact that GlobalAlias::setAlignment exists at all is a side effect of
how the classes are organized, it should never be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208094
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Tim Northover [Tue, 6 May 2014 14:15:14 +0000 (14:15 +0000)]
AArch64/ARM64: implement diagnosis of unpredictable loads & stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208091
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Tue, 6 May 2014 12:50:58 +0000 (12:50 +0000)]
AArch64/ARM64: add two more MC tests to ARM64 set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208085
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Tue, 6 May 2014 12:50:55 +0000 (12:50 +0000)]
AArch64/ARM64: enable MC-level diagnostic tests for NEON insts.
Obviously we can't expect the two backends to produce identical diagnostics,
since what's possible depends quite a bit on how the .td files are structured.
I think the ARM64 diagnostics are basically of the same quality in all the
changed cases, so I've split the CHECK lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208084
91177308-0d34-0410-b5e6-
96231b3b80d8