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Petar Jovanovic [Mon, 24 Sep 2018 10:01:24 +0000 (10:01 +0000)]
[deadargelim] Update dbg.value of 'unused' parameters
DeadArgElim pass marks unused function arguments as ‘undef’ without updating
existing dbg.values referring to it. As a consequence the debug info
metadata in the final executable was wrong.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D51968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342871
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Sam Parker [Mon, 24 Sep 2018 09:34:06 +0000 (09:34 +0000)]
[ARM] bottom-top mul support ARMParallelDSP
Originally committed in rL342210 but was reverted in rL342260 because
it was causing issues in vectorized code, because I had forgotten to
ensure that we're operating on scalar values.
Original commit message:
On failing to find sequences that can be converted into dual macs,
try to find sequential 16-bit loads that are used by muls which we
can then use smultb, smulbt, smultt with a wide load.
Differential Revision: https://reviews.llvm.org/D51983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342870
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Clement Courbet [Mon, 24 Sep 2018 08:39:48 +0000 (08:39 +0000)]
[llvm-exegesis] Fix PR39021.
Summary:
The `set` statements was incorrectly reading the value of the local variable and
setting the value of the parent variable.
Reviewers: tycho, gchatelet, john.brawn
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342865
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Hans Wennborg [Mon, 24 Sep 2018 08:34:17 +0000 (08:34 +0000)]
Fix llvm-diff anon-func.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342864
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Hans Wennborg [Mon, 24 Sep 2018 08:18:47 +0000 (08:18 +0000)]
Remove debug printf leftover from r342397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342863
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Craig Topper [Mon, 24 Sep 2018 05:46:01 +0000 (05:46 +0000)]
[X86] Add 512-bit test cases to setcc-wide-types.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342860
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Dean Michael Berris [Mon, 24 Sep 2018 05:28:01 +0000 (05:28 +0000)]
[XRay] Clean up XRay build configuration
Summary:
This change spans both LLVM and compiler-rt, where we do the following:
- Add XRay to the LLVMBuild system, to allow for distributing the XRay
trace loading library along with the LLVM distributions.
- Use `llvm-config` better in the compiler-rt XRay implementation, to
depend on the potentially already-distributed LLVM XRay library.
While this is tested with the standalone compiler-rt build, it does
require that the LLVMXRay library (and LLVMSupport as well) are
available during the build. In case the static libraries are available,
the unit tests will build and work fine. We're still having issues with
attempting to use a shared library version of the LLVMXRay library since
the shared library might not be accessible from the standard shared
library lookup paths.
The larger change here is the inclusion of the LLVMXRay library in the
distribution, which allows for building tools around the XRay traces and
profiles that the XRay runtime already generates.
Reviewers: echristo, beanz
Subscribers: mgorny, hiraditya, mboerger, llvm-commits
Differential Revision: https://reviews.llvm.org/D52349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342859
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Matt Arsenault [Mon, 24 Sep 2018 04:42:14 +0000 (04:42 +0000)]
Fix asserts when linking wrong address space declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342858
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Matt Arsenault [Mon, 24 Sep 2018 04:42:13 +0000 (04:42 +0000)]
llvm-diff: Fix crash on anonymous functions
Not sure what the correct behavior is for this.
Skip them and report how many there were.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342857
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Craig Topper [Mon, 24 Sep 2018 02:03:11 +0000 (02:03 +0000)]
[DAGCombiner] Remove some dead code from ConstantFoldBITCASTofBUILD_VECTOR
This code handled SCALAR_TO_VECTOR being returned by the recursion, but the code that used to return SCALAR_TO_VECTOR was removed in 2015.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342856
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Lang Hames [Sun, 23 Sep 2018 21:30:05 +0000 (21:30 +0000)]
[ORC] Add some debugging output to Core.h/Core.cpp
Core now logs when materialization units are dispatched or return to JITDylibs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342853
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Simon Pilgrim [Sun, 23 Sep 2018 21:19:15 +0000 (21:19 +0000)]
[X86] Split WriteShift/WriteRotate schedule classes by CL usage.
Variable Shifts/Rotates using the CL register have different behaviours to the immediate instructions - split accordingly to help remove yet more repeated overrides from the schedule models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342852
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Craig Topper [Sun, 23 Sep 2018 21:17:56 +0000 (21:17 +0000)]
[DAGCombiner] Clarify a comment. NFC
This comment was misleading about why we were restricting to before legalize types. The reason given would only apply to before legalize ops. But there is a before legalize types reason that should also be listed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342851
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Craig Topper [Sun, 23 Sep 2018 21:17:55 +0000 (21:17 +0000)]
[LegalizeTypes] Fix bad indentation. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342850
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Simon Pilgrim [Sun, 23 Sep 2018 19:33:58 +0000 (19:33 +0000)]
[X86] Remove unnecessary WriteRotate override. NFCI.
SNB was the last override for ROT(L|R)r(1|i) - they now all use WriteRotate correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342848
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Simon Pilgrim [Sun, 23 Sep 2018 19:16:32 +0000 (19:16 +0000)]
Fix line ending mismatches. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342847
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Simon Pilgrim [Sun, 23 Sep 2018 19:16:01 +0000 (19:16 +0000)]
[X86] ROR*mCL instruction models should match ROL*mCL etc.
Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models.
Yet another step on the scheduler model cleanup marathon......
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342846
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Benjamin Kramer [Sun, 23 Sep 2018 18:43:28 +0000 (18:43 +0000)]
[Aarch64] Fix memcpy that was copying 4x too many bytes
Found by asan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342845
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Sanjay Patel [Sun, 23 Sep 2018 18:41:38 +0000 (18:41 +0000)]
[DAGCombiner][x86] extend decompose of integer multiply into shift/add with negation
This is an alternative to https://reviews.llvm.org/D37896. We can't decompose
multiplies generically without a target hook to tell us when it's profitable.
ARM and AArch64 may be able to remove some existing code that overlaps with
this transform.
This extends D52195 and may resolve PR34474:
https://bugs.llvm.org/show_bug.cgi?id=34474
(still an open question about transforming legal vector multiplies, but we
could open another bug report for those)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342844
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Simon Pilgrim [Sun, 23 Sep 2018 17:40:24 +0000 (17:40 +0000)]
[X86] Added missing RCL/RCR schedule overrides to the generic SNB model
The SandyBridge model was missing schedule values for the RCL/RCR values - instead using the (incredibly optimistic) WriteShift (now WriteRotate) defaults.
I've added overrides with more realistic (slow) values, based on a mixture of Agner/instlatx64 numbers and what later Intel models do as well.
This is necessary to allow WriteRotate to be updated to remove other rotate overrides.
It'd probably be a good idea to investigate a WriteRotateCarry class at some point but its not high priority given the unusualness of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342842
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Simon Pilgrim [Sun, 23 Sep 2018 16:53:02 +0000 (16:53 +0000)]
[X86] Remove unnecessary WriteRotate overrides. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342841
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Simon Pilgrim [Sun, 23 Sep 2018 16:17:13 +0000 (16:17 +0000)]
[X86] Move RORX instructions back to WriteShift schedule class
Despite being rotates, these more modern instructions avoid many of the quirks of the regular x86 rotate instructions and consistently have a schedule closer to shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342839
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Sanjay Patel [Sun, 23 Sep 2018 16:07:46 +0000 (16:07 +0000)]
[x86] add tests for mul decomposition with negative constant; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342838
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Simon Pilgrim [Sun, 23 Sep 2018 15:12:10 +0000 (15:12 +0000)]
[X86] Add WriteRotate schedule class, splitting off from WriteShift.
NFCI for now, but it should make it easier to remove a lot of unnecessary overrides in a future commit.
Now that funnel shift intrinsics are coming online we need to get this cleaned up to make vectorization costs from scalar rotate patterns more straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342837
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Eugene Leviant [Sun, 23 Sep 2018 13:27:47 +0000 (13:27 +0000)]
[WholeProgramDevirt] Don't process declarations when building type id map
Differential revision: https://reviews.llvm.org/D52175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342836
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Simon Pilgrim [Sun, 23 Sep 2018 11:28:47 +0000 (11:28 +0000)]
Build PassBuilder.cpp with /bigobj to try and appease MSVC EXPENSIVE_CHECKS buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342835
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Craig Topper [Sun, 23 Sep 2018 06:49:48 +0000 (06:49 +0000)]
[X86] Add isel pattern for (v8i16 (sext (v8i1))) with DQI and no BWI.
Our lowering that tries to avoid this sign extend can be defeated by the DAG combine folding it with a truncate.
The pattern needs to extend to an v8i32 then truncate back down to v8i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342830
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Craig Topper [Sun, 23 Sep 2018 06:49:47 +0000 (06:49 +0000)]
[X86] Fix a few typos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342829
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Lang Hames [Sun, 23 Sep 2018 02:09:18 +0000 (02:09 +0000)]
[ORC] Update ORC C bindings to use the new llvm::Error C API.
This replaces instances of the LLVMOrcErrorCode type with LLVMErrorRef,
simplifying the implementation of the OrcCBindingsStack class and ORC
C API bindings and making it possible to return arbitrary (wrapped)
llvm::Errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342828
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Craig Topper [Sat, 22 Sep 2018 23:12:34 +0000 (23:12 +0000)]
[DAGCombiner] Simplify some code in visitBITCAST. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342826
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Tri Vo [Sat, 22 Sep 2018 22:17:50 +0000 (22:17 +0000)]
[AArch64] Support adding X[8-15,18] registers as CSRs.
Summary:
Specifying X[8-15,18] registers as callee-saved is used to support
CONFIG_ARM64_LSE_ATOMICS in Linux kernel. As part of this patch we:
- use custom CSR list/mask when user specifies custom CSRs
- update Machine Register Info's list of CSRs with additional custom CSRs in
LowerCall and LowerFormalArguments.
Reviewers: srhines, nickdesaulniers, efriedma, javed.absar
Reviewed By: nickdesaulniers
Subscribers: kristof.beyls, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342824
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Craig Topper [Sat, 22 Sep 2018 18:03:14 +0000 (18:03 +0000)]
[DAGCombiner] Rewrite r331896 in a different way to address a FIXME. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342809
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Yonghong Song [Sat, 22 Sep 2018 17:31:01 +0000 (17:31 +0000)]
[bpf] Test case for symbol information in object file
This patch tests the change introduced in r342556.
Signed-off-by: Paul Chaignon <paul.chaignon@orange.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342807
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Sanjay Patel [Sat, 22 Sep 2018 14:43:55 +0000 (14:43 +0000)]
[InstCombine][x86] try even harder to convert blendv intrinsic to generic IR (PR38814)
Follow-up to rL342324 (D52059):
Missing optimizations with blendv are shown in:
https://bugs.llvm.org/show_bug.cgi?id=38814
This is an easier and more powerful solution than adding pattern matching for a few
special cases in the backend. The potential danger with this transform in IR is that
the condition value can get separated from the select, and the backend might not be
able to make a blendv out of it again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342806
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George Rimar [Sat, 22 Sep 2018 07:36:20 +0000 (07:36 +0000)]
[lib/MC] - Set SHF_EXCLUDE flag for .dwo sections.
DWARF5 spec says about single file split case:
"The sections that do not require relocation, however, can be written
to the relocatable object (.o) file but ignored by the
the linker or they can be written to a separate DWARF object (.dwo) file
that need not be accessed by the linker."
Nice way to make linker to ignore them is to set SHF_EXCLUDE flag.
It seems to be not harmful to always set it for .dwo sections.
That is what this patch does.
Differential revision: https://reviews.llvm.org/D52303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342800
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Simon Atanasyan [Sat, 22 Sep 2018 06:04:32 +0000 (06:04 +0000)]
[mips] Provide more detailed description for MIPS targets. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342799
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Simon Atanasyan [Sat, 22 Sep 2018 06:04:26 +0000 (06:04 +0000)]
[mips] Remove obsoleted "experimental" tag from MIPS 64-bit targets. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342798
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Craig Topper [Sat, 22 Sep 2018 05:53:27 +0000 (05:53 +0000)]
[InstCombine] Fold (min/max ~X, Y) -> ~(max/min X, ~Y) when Y is freely invertible
Summary: This restores the combine that was reverted in r341883. The infinite loop from the failing test no longer occurs due to changes from r342163.
Reviewers: spatel, dmgreen
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342797
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Craig Topper [Sat, 22 Sep 2018 05:16:35 +0000 (05:16 +0000)]
[X86] Fix inline expansion for memset in x32
Summary: Similar to D51893 which was for memcpy
Reviewers: efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342796
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Craig Topper [Sat, 22 Sep 2018 05:08:38 +0000 (05:08 +0000)]
[X86] Fold (movmsk (setne (and X, (1 << C)), 0)) -> (movmsk (X << C)) for vXi8 vectors.
We don't have a vXi8 shift left so we need to bitcast to a vXi16 vector to perform the shift. If we let lowering legalize the vXi8 shift we get an extra and that we don't need and fail to remove.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342795
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Vyacheslav Zakharin [Sat, 22 Sep 2018 01:01:03 +0000 (01:01 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342792
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Jordan Rupprecht [Fri, 21 Sep 2018 23:48:12 +0000 (23:48 +0000)]
[llvm-size] Berkeley formatting: use tabs instead of spaces as field delimeters.
This matches GNU behavior for size and allows use of cut to parse the output of llvm-size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342791
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Craig Topper [Fri, 21 Sep 2018 23:14:05 +0000 (23:14 +0000)]
[X86] Teach fast isel to use MOV32ri64 for loading an unsigned 32 immediate into a 64-bit register.
Previously we used SUBREG_TO_REG+MOV32ri. But regular isel was changed recently to use the MOV32ri64 pseudo. Fast isel now does the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342788
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Warren Ristow [Fri, 21 Sep 2018 23:03:50 +0000 (23:03 +0000)]
[Loop Vectorizer] Abandon vectorization when no integer IV found
Support for vectorizing loops with secondary floating-point induction
variables was added in r276554. A primary integer IV is still required
for vectorization to be done. If an FP IV was found, but no integer IV
was found at all (primary or secondary), the attempt to vectorize still
went forward, causing a compiler-crash. This change abandons that
attempt when no integer IV is found. (Vectorizing FP-only cases like
this, rather than bailing out, is discussed as possible future work
in D52327.)
See PR38800 for more information.
Differential Revision: https://reviews.llvm.org/D52327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342786
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Aaron Ballman [Fri, 21 Sep 2018 23:01:32 +0000 (23:01 +0000)]
Move individual benchmark targets into the Utils folder in IDEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342785
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Zachary Turner [Fri, 21 Sep 2018 23:00:37 +0000 (23:00 +0000)]
Try moving this function to another file.
I can't reproduce this compilation failure so I can't really
test this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342784
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Lang Hames [Fri, 21 Sep 2018 22:59:48 +0000 (22:59 +0000)]
[ORC] In RTDyldObjectLinkingLayer, only call NotifyFreed if the object file
has been finalized.
This prevents crashes on unfinalized objects for clients using
JITEventListeners.
Patch by Geoff Levner. Thanks Geoff!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342783
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Aaron Ballman [Fri, 21 Sep 2018 22:55:57 +0000 (22:55 +0000)]
Add benchmark and benchmark_main to the Utils folder in IDEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342782
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Zachary Turner [Fri, 21 Sep 2018 22:44:31 +0000 (22:44 +0000)]
Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342781
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Zachary Turner [Fri, 21 Sep 2018 22:36:28 +0000 (22:36 +0000)]
[NativePDB] Add support for reading function signatures.
This adds support for parsing function signature records and returning
them through the native DIA interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342780
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Zachary Turner [Fri, 21 Sep 2018 22:36:04 +0000 (22:36 +0000)]
[PDB] Add native reading support for UDT / class types.
This allows the native reader to find records of class/struct/
union type and dump them. This behavior is tested by using the
diadump subcommand against golden output produced by actual DIA
SDK on the same PDB file, and again using pretty -native to
confirm that we actually dump the classes. We don't find class
members or anything like that yet, for now it's just the class
itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342779
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Fedor Sergeev [Fri, 21 Sep 2018 22:10:17 +0000 (22:10 +0000)]
[New PM][PassInstrumentation] Adding PassInstrumentation to the AnalysisManager runs
As a prerequisite to time-passes implementation which needs to time both passes
and analyses, adding instrumentation points to the Analysis Manager.
The are two functional differences between Pass and Analysis instrumentation:
- the latter does not increment pass execution counter
- it does not provide ability to skip execution of the corresponding analysis
Reviewers: chandlerc, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D51275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342778
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Adrian Prantl [Fri, 21 Sep 2018 21:59:34 +0000 (21:59 +0000)]
llvm-dwarfdump --statistics: Unique abstract origins across multiple CUs.
Instead of indexing local variables by DIE offset, use the variable
name + the path through the lexical block tree. This makes the lookup
key consistent across duplicate abstract origins in different CUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342776
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Sanjay Patel [Fri, 21 Sep 2018 21:25:16 +0000 (21:25 +0000)]
[x86] add more tests for poetntial andnp splitting with AVX1; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342775
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Simon Pilgrim [Fri, 21 Sep 2018 21:08:26 +0000 (21:08 +0000)]
[X86] Add AVX512 target to load scalar to vector tests
To investigate broadcast instruction codegen for D51553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342773
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Wouter van Oortmerssen [Fri, 21 Sep 2018 20:53:55 +0000 (20:53 +0000)]
[WebAssembly] Simplified selecting asmmatcher stack instructions.
Summary:
By using the existing isCodeGenOnly bit in the tablegen defs, as
suggested by tlively in https://reviews.llvm.org/D51662
Tested: llvm-lit -v `find test -name WebAssembly`
Reviewers: tlively
Subscribers: dschuff, sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342772
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Jorge Gorbe Moya [Fri, 21 Sep 2018 20:45:08 +0000 (20:45 +0000)]
Test commit. Removed a blank line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342771
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Thomas Lively [Fri, 21 Sep 2018 18:46:39 +0000 (18:46 +0000)]
[WebAssembly][NFC] Rename simd-conversions test to simd-bitcasts
Summary:
This name is more accurate and I want to reuse the simd-conversions
name for testing the actual conversion ops.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342761
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Caroline Tice [Fri, 21 Sep 2018 18:41:31 +0000 (18:41 +0000)]
Pass code-model through Module IR to LTO which will use it.
Currently the code-model does not get saved in the module IR,
so if a code model is specified when compiling with LTO,
it gets lost and is not propagated properly to LTO. This patch,
along with one for the front end, fixes that.
Differential Revision: https://reviews.llvm.org/D52322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342760
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JF Bastien [Fri, 21 Sep 2018 18:35:32 +0000 (18:35 +0000)]
[NFC] use bit_cast in PointerSumType
The code was already using union and memcpy to do this. Remove the memcpy. We can't just change the union because a reference to its member is returned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342759
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Sanjay Patel [Fri, 21 Sep 2018 18:24:53 +0000 (18:24 +0000)]
[x86] add (negative) andnp test for D52318; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342756
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Sanjay Patel [Fri, 21 Sep 2018 18:03:49 +0000 (18:03 +0000)]
[x86] add test with optsize attribute for scalar->vector transform; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342755
91177308-0d34-0410-b5e6-
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Wouter van Oortmerssen [Fri, 21 Sep 2018 17:47:58 +0000 (17:47 +0000)]
[WebAssembly] Made assembler only use stack instruction tablegen defs
Summary:
This ensures we have the non-register version of the instruction.
The stack version of call_indirect now wants a type index argument,
so that has been added in the existing tests.
Tested:
llvm-lit -v `find test -name WebAssembly`
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342753
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Krzysztof Parzyszek [Fri, 21 Sep 2018 17:40:35 +0000 (17:40 +0000)]
[Hexagon] Avoid functions with exception handling in HexagonConstExtenders
The constant-extender optimization does a form of code motion, which is
complicated in the presence of exception handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342751
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Daniel Sanders [Fri, 21 Sep 2018 16:32:49 +0000 (16:32 +0000)]
[tblgen] Fix undefined behaviour when assigning integers to large bits<n>'s
This code:
bits<96> X = 0;
was triggering undefined behaviour since it iterates over bits 0..95 and tests
them against the IntInit using 1LL << I.
This patch resolves the undefined behaviour by continuing to treat the IntInit
as a 64-bit value and simply causing all bit tests in excess of 64-bits to report
false. As a result,
bits<96> X = -1;
will be equivalent to:
bits<96> X;
let X{0-63} = -1;
let X{64-95} = 0;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342744
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Sameer Sahasrabuddhe [Fri, 21 Sep 2018 16:31:51 +0000 (16:31 +0000)]
revert changes from r342722
"[AMDGPU] lower-switch in preISel as a workaround for legacy DA"
This broke regression tests. The first breakage was noticed here:
http://lab.llvm.org:8011/builders/lld-x86_64-freebsd/builds/23549
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342743
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Matthias Braun [Fri, 21 Sep 2018 15:47:41 +0000 (15:47 +0000)]
AArch64FastISel: Abort if we failed to select operand of intrinsic
rdar://
44642447
Differential Revision: https://reviews.llvm.org/D52335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342742
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Sanjay Patel [Fri, 21 Sep 2018 14:43:49 +0000 (14:43 +0000)]
[InstCombine] add tests for extractelement; NFC
There are folds under visitExtractElementInst() that don't appear
to have any test coverage, so adding a few basic cases here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342740
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JF Bastien [Fri, 21 Sep 2018 14:31:25 +0000 (14:31 +0000)]
[ADT] restrict bit_cast to trivially-constructible To
Summary: As discussed in r341853 by blaikie, the reinterpret_cast was technically an aliasing violation. Restrict our bit_cast implementation to To which are trivially-constructible (and note the existing restriction to constexpr). Once we move to C++17 we can use a version of bit_cast without these restrictions, or if we care we can SFINAE a different implementation when To isn't trivially-constructible.
Originally landed in r342710 and reverted in r342711 because is_trivially_copyable is only in GCC 5.1 and later.
Reviewers: dblaikie, rsmith
Subscribers: dexonsmith, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D52332
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342739
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Clement Courbet [Fri, 21 Sep 2018 14:07:20 +0000 (14:07 +0000)]
[X86][Sched] Add zero idiom sched data to the SNB model.
Summary:
On SNB, renamer-based zeroing does not work for:
- 16 and 8-bit GPRs[1].
- MMX [2].
- ANDN variants [3]
[1] echo 'sub %ax, %ax' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
[2] echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
[3] echo 'andnps %xmm0, %xmm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
Reviewers: RKSimon, andreadb
Subscribers: gbedwell, craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D52358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342736
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Andrea Di Biagio [Fri, 21 Sep 2018 12:43:07 +0000 (12:43 +0000)]
[X86][BtVer2] Fix latency and resource cycles of AVX 256-bit zero-idioms.
This patch introduces a SchedWriteVariant to describe zero-idiom VXORP(S|D)Yrr
and VANDNP(S|D)Yrr.
This is a follow-up of r342555.
On Jaguar, a VXORPSYrr is 2 macro opcodes. Only one opcode is eliminated at
register-renaming stage. The other opcode has to be executed to set the upper
half of the destination YMM.
Same for VANDNP(S|D)Yrr.
Differential Revision: https://reviews.llvm.org/D52347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342728
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Jonas Devlieghere [Fri, 21 Sep 2018 12:28:44 +0000 (12:28 +0000)]
[test] Fix Assembler/debug-info.ll
Update Assembler/debug-info.ll to contain discriminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342727
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Andrea Di Biagio [Fri, 21 Sep 2018 12:22:14 +0000 (12:22 +0000)]
[X86] Add scheduling tests for AVX1 256-bit zero-idioms. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342726
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Jonas Devlieghere [Fri, 21 Sep 2018 12:03:14 +0000 (12:03 +0000)]
Ensure that variant part discriminator is read by MetadataLoader
https://reviews.llvm.org/D42082 introduced variant parts to debug info
in LLVM. Subsequent work on the Rust compiler has found a bug in that
patch; namely, there is a path in MetadataLoader that fails to restore
the discriminator.
This patch fixes the bug.
Patch by: Tom Tromey
Differential revision: https://reviews.llvm.org/D52340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342725
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Jonas Devlieghere [Fri, 21 Sep 2018 11:55:17 +0000 (11:55 +0000)]
[dsymutil] Suppress CoreFoundation leaks in tests.
This suppresses CoreFoundation originated leaks in the dsymutil tests.
I'm not sure if this is a false positive or not, but either way we don't
have control over it and shouldn't keep the bot red.
http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342724
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Benjamin Kramer [Fri, 21 Sep 2018 11:38:35 +0000 (11:38 +0000)]
[ADT] Hack around GCC 5.4 miscompiling Optional of enum.
I'm still not 100% sure that this is not UB lingering (Optional has UB
and should use std::launder, but we don't have std::launder)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342723
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Sameer Sahasrabuddhe [Fri, 21 Sep 2018 11:26:55 +0000 (11:26 +0000)]
[AMDGPU] lower-switch in preISel as a workaround for legacy DA
Summary:
The default target of the switch instruction may sometimes be an
"unreachable" block, when it is guaranteed that one of the cases is
always taken. The dominator tree concludes that such a switch
instruction does not have an immediate post dominator. This confuses
divergence analysis, which is unable to propagate sync dependence to
the targets of the switch instruction.
As a workaround, the AMDGPU target now invokes lower-switch as a
preISel pass. LowerSwitch is designed to handle the unreachable
default target correctly, allowing the divergence analysis to locate
the correct immediate dominator of the now-lowered switch.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits, simoll
Differential Revision: https://reviews.llvm.org/D52221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342722
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Alexander Timofeev [Fri, 21 Sep 2018 10:31:22 +0000 (10:31 +0000)]
[AMDGPU] Divergence driven instruction selection. Part 1.
Summary: This change is the first part of the AMDGPU target description
change. The aim of it is the effective splitting the vector and scalar
flows at the selection stage. Selection uses predicate functions based
on the framework implemented earlier - https://reviews.llvm.org/D35267
Differential revision: https://reviews.llvm.org/D52019
Reviewers: rampitec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342719
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Jonas Devlieghere [Fri, 21 Sep 2018 07:50:21 +0000 (07:50 +0000)]
[dwarfdump] Verify DW_AT_type is set and points to a compatible DIE.
This extends the verifier to catch three new errors:
* Missing DW_AT_type attributes for DW_TAG_formal_parameter,
DW_TAG_variable and DW_TAG_array_type.
* Valid references for DW_AT_type pointing to a non-type tag.
Differential revision: https://reviews.llvm.org/D52223
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342713
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Jonas Devlieghere [Fri, 21 Sep 2018 07:49:29 +0000 (07:49 +0000)]
[dwarfdump] Verify compatibility of attribute TAGs.
Verify that DW_AT_specification and DW_AT_abstract_origin reference a
DIE with a compatible tag.
Differential revision: https://reviews.llvm.org/D38719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342712
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JF Bastien [Fri, 21 Sep 2018 05:34:12 +0000 (05:34 +0000)]
Revert "[ADT] restrict bit_cast to trivially-constructible To"
Of course some bots don't have std::is_trivially_constructible...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342711
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JF Bastien [Fri, 21 Sep 2018 05:18:49 +0000 (05:18 +0000)]
[ADT] restrict bit_cast to trivially-constructible To
Summary: As discussed in r341853 by blaikie, the reinterpret_cast was technically an aliasing violation. Restrict our bit_cast implementation to To which are trivially-constructible (and note the existing restriction to constexpr). Once we move to C++17 we can use a version of bit_cast without these restrictions, or if we care we can SFINAE a different implementation when To isn't trivially-constructible.
Reviewers: dblaikie, rsmith
Subscribers: dexonsmith, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D52332
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342710
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JF Bastien [Fri, 21 Sep 2018 05:17:42 +0000 (05:17 +0000)]
Merge clang's isRepeatedBytePattern with LLVM's isBytewiseValue
Summary:
his code was in CGDecl.cpp and really belongs in LLVM's isBytewiseValue. Teach isBytewiseValue the tricks clang's isRepeatedBytePattern had, including merging undef properly, and recursing on more types.
clang part of this patch: D51752
Subscribers: dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D51751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342709
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Dan Gohman [Fri, 21 Sep 2018 03:24:42 +0000 (03:24 +0000)]
[WebAssembly] Revert r342701, "Add WebAssembly to LLVM_ALL_TARGTS."
There is a memory leak which is detected in some of the sanitizer builds.
MCSymbolWasm contains SmallVectors for holding signature information,
however MCContext doesn't run destructors for MCSymbols, so in cases
where the SmallVectors heap-allocate, the memory is leaked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342707
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Dean Michael Berris [Fri, 21 Sep 2018 01:54:08 +0000 (01:54 +0000)]
[MCA] Remove dependency on CodeGen.
Summary:
There isn't any actual dependency - there's one #include from CodeGen
but nothing from the header is actually used.
With this change we can use the MCA library from CodeGen without
circular dependencies (e.g. for scheduling).
Reviewers: andreadb
Reviewed By: andreadb
Authored By: orodley
Subscribers: mgorny, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D52288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342706
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Kristina Brooks [Fri, 21 Sep 2018 01:53:51 +0000 (01:53 +0000)]
[Docs] [Support] Correct a missed reference and use up to date .inc examples.
In my original diff I missed #include "llvm/System/Thing.h" and forgot to update a
reference to .inc files a few lines down. This patch corrects these things as
they were missed in revision 342500.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342705
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Justin Bogner [Fri, 21 Sep 2018 00:51:04 +0000 (00:51 +0000)]
[MachineCopyPropagation] Refactor copy tracking into a class. NFC
This is a bit easier to follow than handling the copy and src maps
directly in the pass, and will make upcoming changes to how this is
done easier to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342703
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Jordan Rupprecht [Fri, 21 Sep 2018 00:47:31 +0000 (00:47 +0000)]
[llvm-objcopy/llvm-strip]: handle --version
Summary:
Implement --version for objcopy and strip.
I think there are LLVM utilities that automatically handle this, but that doesn't seem to work with custom parsing since this binary handles both objcopy and strip, so it uses custom parsing.
This fixes PR38298
Reviewers: jhenderson, alexshap, jakehehrlich
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342702
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Dan Gohman [Fri, 21 Sep 2018 00:39:57 +0000 (00:39 +0000)]
[WebAssembly] Add WebAssembly to LLVM_ALL_TARGTS.
This makes WebAssembly build by default, rather than requiring
LLVM_EXPERIMENTAL_TARGETS_TO_BUILD!
Differential Revision: https://reviews.llvm.org/D43211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342701
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Justin Bogner [Fri, 21 Sep 2018 00:08:33 +0000 (00:08 +0000)]
[MachineCopyPropagation] Minor clang-formatting. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342700
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David Blaikie [Thu, 20 Sep 2018 23:11:27 +0000 (23:11 +0000)]
Fix DenseSet::ConstIterator typedefs
Fix DenseSet::ConstIterator pointer/reference typedefs to be const
Patch by Brad Moody!
Differential Revision: https://reviews.llvm.org/D52260
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342697
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Aditya Nandakumar [Thu, 20 Sep 2018 23:01:56 +0000 (23:01 +0000)]
Add the ability to register callbacks for removal and insertion of MachineInstrs
https://reviews.llvm.org/D52127
This patch adds the ability to watch for insertions/deletions of
MachineInstructions similar to MachineRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342696
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David Blaikie [Thu, 20 Sep 2018 22:48:09 +0000 (22:48 +0000)]
Remove an unused function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342694
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Yonghong Song [Thu, 20 Sep 2018 22:24:27 +0000 (22:24 +0000)]
bpf: check illegal usage of XADD insn return value
Currently, BPF has XADD (locked add) insn support and the
asm looks like:
lock *(u32 *)(r1 + 0) += r2
lock *(u64 *)(r1 + 0) += r2
The instruction itself does not have a return value.
At the source code level, users often use
__sync_fetch_and_add()
which eventually translates to XADD. The return value of
__sync_fetch_and_add() is supposed to be the old value
in the xadd memory location. Since BPF::XADD insn does not
support such a return value, this patch added a PreEmit
phase to check such a usage. If such an illegal usage
pattern is detected, a fatal error will be reported like
line 4: Invalid usage of the XADD return value
if compiled with -g, or
Invalid usage of the XADD return value
if compiled without -g.
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342692
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Thomas Lively [Thu, 20 Sep 2018 22:08:27 +0000 (22:08 +0000)]
[WebAssembly][NFC] Add missing tests for indirect calls
Summary: Depends on D52105.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342691
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Thomas Lively [Thu, 20 Sep 2018 22:04:44 +0000 (22:04 +0000)]
[WebAssembly] Add V128 value type to binary format
Summary: Adds the necessary support to lib/ObjectYAML and fixes SIMD
calls to allow the tests to work. Also removes some dead code that
would otherwise have to have been updated.
Reviewers: aheejin, dschuff, sbc100
Subscribers: jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342689
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Jessica Paquette [Thu, 20 Sep 2018 21:53:25 +0000 (21:53 +0000)]
[MachineOutliner][NFC] Don't add MBBs with a size < 2 to the search space
The suffix tree won't ever consider sequences with a length less than 2.
Therefore, we really ought to not even consider them in the first place.
Also add a FIXME explaining that this should be defined in terms of the size
in B of an outlined call versus the size in B of the MBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342688
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Xin Tong [Thu, 20 Sep 2018 21:16:16 +0000 (21:16 +0000)]
[GlobalDCE] AvailableExternal linkage is checked in isDiscardableIfUnused [NFC].
Summary:
AvailableExternal was not handled in isDiscardableIfUnused when isDiscardableIfUnused
was added in r158476. Till it was handled in r247044. This is a NFC.
Reviewers: pcc, tejohnson
Reviewed By: tejohnson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342684
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Sanjay Patel [Thu, 20 Sep 2018 21:10:14 +0000 (21:10 +0000)]
[InstCombine] rename test file, simplify tests, regenerate full checks; NFC
Fast-math is irrelevant for these transforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342683
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Walter Lee [Thu, 20 Sep 2018 20:05:57 +0000 (20:05 +0000)]
[RegAllocGreedy] Fix crash in tryLocalSplit
tryLocalSplit only handles a single use block, but an interval may
have multiple use blocks. So don't crash in that case. This fixes
PR38795.
Differential revision: https://reviews.llvm.org/D52277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342682
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