OSDN Git Service
Amaury Sechet [Tue, 28 Feb 2017 00:15:13 +0000 (00:15 +0000)]
Add test case for computing known bits of substraction operations. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296417
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Michael Kuperstein [Tue, 28 Feb 2017 00:11:34 +0000 (00:11 +0000)]
[CGP] Split some critical edges coming out of indirect branches
Splitting critical edges when one of the source edges is an indirectbr
is hard in general (because it requires changing the memory the indirectbr
reads). But if a block only has a single indirectbr predecessor (which is
the common case), we can simulate splitting that edge by splitting
the destination block, and retargeting the *direct* branches.
This is motivated by the use of computed gotos in python 2.7: PyEval_EvalFrame()
ends up using an indirect branch with ~100 successors, and passing a constant to
each of those. Since MachineSink can't break indirect critical edges on demand
(and doing this in MIR doesn't look feasible), this causes us to emit about ~100
defs of registers containing constants, which we in the predecessor block, where
only one of those constants is used in each successor. So, at each computed goto,
we needlessly spill about a 100 constants to stack. The end result is that a
clang-compiled python interpreter can be about ~2.5x slower on a simple python
reduction loop than a gcc-compiled interpreter.
Differential Revision: https://reviews.llvm.org/D29916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296416
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Zachary Turner [Tue, 28 Feb 2017 00:04:07 +0000 (00:04 +0000)]
[PDB] Make streams carry their own endianness.
Before the endianness was specified on each call to read
or write of the StreamReader / StreamWriter, but in practice
it's extremely rare for streams to have data encoded in
multiple different endiannesses, so we should optimize for the
99% use case.
This makes the code cleaner and more general, but otherwise
has NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296415
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Eugene Zelenko [Mon, 27 Feb 2017 23:43:14 +0000 (23:43 +0000)]
[DebugInfo] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296413
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Michael Kuperstein [Mon, 27 Feb 2017 23:18:11 +0000 (23:18 +0000)]
[SLP] Load sorting should not try to sort things that aren't loads.
We may get a VL where the first element is a load, but the others
aren't. Trying to sort such VLs can only lead to sorrow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296411
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Dan Gohman [Mon, 27 Feb 2017 23:10:18 +0000 (23:10 +0000)]
[MC] Implement the COFF directives in MCNullStreamer.
This fixes -filetype=null errors introduced in r296403.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296410
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Matt Arsenault [Mon, 27 Feb 2017 23:08:49 +0000 (23:08 +0000)]
AMDGPU: Basic folds for fmed3 intrinsic
Constant fold, canonicalize constants to RHS,
reduce to minnum/maxnum when inputs are nan/undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296409
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Zachary Turner [Mon, 27 Feb 2017 22:57:32 +0000 (22:57 +0000)]
Remove some code accidentally left in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296407
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Petr Hosek [Mon, 27 Feb 2017 22:49:37 +0000 (22:49 +0000)]
[AddressSanitizer] Put shadow at 0 for Fuchsia
The Fuchsia ASan runtime reserves the low part of the address space.
Patch by Roland McGrath
Differential Revision: https://reviews.llvm.org/D30426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296405
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Eugene Zelenko [Mon, 27 Feb 2017 22:45:06 +0000 (22:45 +0000)]
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296404
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Dan Gohman [Mon, 27 Feb 2017 22:44:37 +0000 (22:44 +0000)]
[MC] Factor out non-COFF handling of COFF-specific directives.
Instead of requiring every non-COFF MCObjectStreamer to implement the
COFF hooks just to do an llvm_unreachable to say that they're not
supported, do the llvm_unreachable in the default implementation, as
suggested by rnk in https://reviews.llvm.org/D26722.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296403
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Dan Gohman [Mon, 27 Feb 2017 22:41:39 +0000 (22:41 +0000)]
[WebAssembly] Add some comments and tidy up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296402
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Matt Arsenault [Mon, 27 Feb 2017 22:40:39 +0000 (22:40 +0000)]
AMDGPU: Use v_med3_{f16|i16|u16}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296401
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Dan Gohman [Mon, 27 Feb 2017 22:38:58 +0000 (22:38 +0000)]
[WebAssembly] Split CFG-sorting into its own pass. NFC.
CFG sorting was already an independent algorithm from block/loop insertion;
this change makes it more convenient to debug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296399
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Hans Wennborg [Mon, 27 Feb 2017 22:33:02 +0000 (22:33 +0000)]
Revert r296366 "[InlineFunction] add nonnull assumptions based on argument attributes"
It causes miscompiles e.g. during self-host of Clang (PR32082).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296398
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Zachary Turner [Mon, 27 Feb 2017 22:17:50 +0000 (22:17 +0000)]
Add missing namespace qualifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296397
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Matt Arsenault [Mon, 27 Feb 2017 22:15:25 +0000 (22:15 +0000)]
AMDGPU: Support v2i16/v2f16 packed operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296396
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Arnold Schwaighofer [Mon, 27 Feb 2017 22:12:06 +0000 (22:12 +0000)]
ISel: We need to notify FastIS of the IMPLICIT_DEF we created in createSwiftErrorEntriesInEntryBlock
Otherwise, it will insert instructions before it.
rdar://
30536186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296395
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Zachary Turner [Mon, 27 Feb 2017 22:11:43 +0000 (22:11 +0000)]
[PDB] Partial resubmit of r296215, which improved PDB Stream Library.
This was reverted because it was breaking some builds, and
because of incorrect error code usage. Since the CL was
large and contained many different things, I'm resubmitting
it in pieces.
This portion is NFC, and consists of:
1) Renaming classes to follow a consistent naming convention.
2) Fixing the const-ness of the interface methods.
3) Adding detailed doxygen comments.
4) Fixing a few instances of passing `const BinaryStream& X`. These
are now passed as `BinaryStreamRef X`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296394
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Matt Arsenault [Mon, 27 Feb 2017 21:59:07 +0000 (21:59 +0000)]
Revert "DAG: Check if extract_vector_elt is legal or custom"
This reverts r295782. This could potentially result in some
legalization loops and I avoided the need for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296393
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Xin Tong [Mon, 27 Feb 2017 21:51:48 +0000 (21:51 +0000)]
Empty line. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296392
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Rong Xu [Mon, 27 Feb 2017 21:42:39 +0000 (21:42 +0000)]
[PGO] Fix a bug in reading text format value profile.
Summary: Should use the Valuekind read from the profile.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits, xur
Differential Revision: https://reviews.llvm.org/D30420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296391
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Sanjay Patel [Mon, 27 Feb 2017 21:30:54 +0000 (21:30 +0000)]
[ARM] don't transform an add(ext Cond), C to select unless there's a setcc of the condition
The transform in question claims to be doing:
// fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
...starting in PerformADDCombineWithOperands(), but it wasn't actually checking for a setcc node
for the sext/zext patterns.
This is exactly the opposite of a transform I'd like to add to DAGCombiner's foldSelectOfConstants(),
so I was seeing infinite loops with my draft of a patch applied.
The changes in select_const.ll look positive (less instructions). The change in arm-and-tst-peephole.ll
is unrelated. We're changing the input IR in that test to preserve the intent of the test, but that's
not affected by this code change.
Differential Revision:
https://reviews.llvm.org/D30355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296389
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Lang Hames [Mon, 27 Feb 2017 21:09:47 +0000 (21:09 +0000)]
[Support][Error] Add a 'cantFail' utility function for known-safe calls to
fallible functions.
Some fallible functions (those returning Error or Expected<T>) may only fail
for a subset of their inputs. For example, a "safe" square root function will
succeed for all finite positive inputs:
Expected<double> safeSqrt(double d) {
if (d < 0 && !isnan(d) && !isinf(d))
return make_error<...>("Cannot sqrt -ve values, nans or infs");
return sqrt(d);
}
At a safe callsite for such a function, checking the error return value is
redundant:
if (auto ValOrErr = safeSqrt(42.0)) {
// use *ValOrErr.
} else
llvm_unreachable("safeSqrt should always succeed for +ve values");
The cantFail function wraps this check and extracts the contained value,
simplifying control flow:
double Result = cantFail(safeSqrt(42.0));
This function should be used with care: it is a programmatic error to wrap a
call with cantFail if it can in fact fail. For debug builds this will
result in llvm_unreachable being called. For release builds the behavior is
undefined.
Use of this function is likely to be rare in library code, but more common
for tool and unit-test code where inputs and mock functions may be known to be
safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296384
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Matt Arsenault [Mon, 27 Feb 2017 21:04:41 +0000 (21:04 +0000)]
AMDGPU: Add some of the new gfx9 VOP3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296382
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Simon Pilgrim [Mon, 27 Feb 2017 21:01:57 +0000 (21:01 +0000)]
[X86][SSE] Attempt to extract vector elements through target shuffles
DAGCombiner already supports peeking thorough shuffles to improve vector element extraction, but legalization often leaves us in situations where we need to extract vector elements after shuffles have already been lowered.
This patch adds support for VECTOR_EXTRACT_ELEMENT/PEXTRW/PEXTRB instructions to attempt to handle target shuffles as well. I've covered some basic scenarios including handling shuffle mask scaling and the implicit zero-extension of PEXTRW/PEXTRB, there is more that could be done here (that I've mentioned in TODOs) but I haven't found many cases where its worth it.
Differential Revision: https://reviews.llvm.org/D30176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296381
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Matt Arsenault [Mon, 27 Feb 2017 20:52:10 +0000 (20:52 +0000)]
AMDGPU: Support inlineasm for packed instructions
Add packed types as legal so they may be used with inlineasm.
Keep all operations expanded for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296379
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Alexey Bataev [Mon, 27 Feb 2017 20:22:44 +0000 (20:22 +0000)]
[SLP] Use different flags in tests for reduction ops and extra args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296376
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Matt Arsenault [Mon, 27 Feb 2017 20:21:31 +0000 (20:21 +0000)]
AMDGPU: Don't fold immediate if clamp/omod are set
Doesn't fix any practical problems because clamp/omod
are currently folded after peephole optimizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296375
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Matt Arsenault [Mon, 27 Feb 2017 19:35:42 +0000 (19:35 +0000)]
AMDGPU: Fold omod into instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296372
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Taewook Oh [Mon, 27 Feb 2017 19:30:01 +0000 (19:30 +0000)]
[TailDuplicator] Maintain DebugLoc for branch instructions
Summary: Existing implementation of duplicateSimpleBB function drops DebugLoc metadata of branch instructions during the transformation. This patch addresses this issue by making newly created branch instructions to keep the metadata of replaced branch instructions.
Reviewers: qcolombet, craig.topper, aprantl, MatzeB, sanjoy, dblaikie
Reviewed By: dblaikie
Subscribers: dblaikie, llvm-commits
Differential Revision: https://reviews.llvm.org/D30026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296371
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Matt Arsenault [Mon, 27 Feb 2017 19:24:47 +0000 (19:24 +0000)]
AMDGPU: Add f16 to shader calling conventions
Mostly useful for writing tests for f16 features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296370
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Alexey Bataev [Mon, 27 Feb 2017 19:16:09 +0000 (19:16 +0000)]
[SLP] Modify test to check IR flags propagation for extra args.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296369
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Matt Arsenault [Mon, 27 Feb 2017 18:49:11 +0000 (18:49 +0000)]
AMDGPU: Add VOP3P instruction format
Add a few non-VOP3P but instructions related to packed.
Includes hack with dummy operands for the benefit of the assembler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296368
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Amaury Sechet [Mon, 27 Feb 2017 18:32:54 +0000 (18:32 +0000)]
Refactor xaluo.ll and xmulo.ll tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296367
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Sanjay Patel [Mon, 27 Feb 2017 18:13:48 +0000 (18:13 +0000)]
[InlineFunction] add nonnull assumptions based on argument attributes
This was suggested in D27855: have the inliner add assumptions, so we don't
lose nonnull info provided by argument attributes.
This still doesn't solve PR28430 (dyn_cast), but this gets us closer.
https://reviews.llvm.org/D29999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296366
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Krzysztof Parzyszek [Mon, 27 Feb 2017 18:03:35 +0000 (18:03 +0000)]
[Hexagon] Defs and clobbers can overlap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296365
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Xin Tong [Mon, 27 Feb 2017 18:00:13 +0000 (18:00 +0000)]
Fix a bug when unswitching on partial LIV for SwitchInst
Summary: Fix a bug when unswitching on partial LIV for SwitchInst.
Reviewers: hfinkel, efriedma, sanjoy
Reviewed By: sanjoy
Subscribers: david2050, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D29107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296363
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Rong Xu [Mon, 27 Feb 2017 17:59:01 +0000 (17:59 +0000)]
Fix comments. NFC.
Change "Thin-LTO" to "ThinLTO" in the comments for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296362
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Steven Wu [Mon, 27 Feb 2017 16:56:37 +0000 (16:56 +0000)]
Fix LLVM module build
Add WasmRelocs/WebAssembly.def to textual include header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296356
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Craig Topper [Mon, 27 Feb 2017 16:15:32 +0000 (16:15 +0000)]
[X86] Use APInt instead of SmallBitVector tracking undef elements from getTargetConstantBitsFromNode and getConstVector.
Summary:
SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc.
APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296355
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Craig Topper [Mon, 27 Feb 2017 16:15:30 +0000 (16:15 +0000)]
[X86] Use APInt instead of SmallBitVector for tracking Zeroable elements in shuffle lowering
Summary:
SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc.
APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296354
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Craig Topper [Mon, 27 Feb 2017 16:15:27 +0000 (16:15 +0000)]
[X86] Fix SmallVector sizes in constant pool shuffle decoding to avoid heap allocation
Some of the vectors are under sized to avoid heap allocation. In one case the vector was oversized.
Differential Revision: https://reviews.llvm.org/D30387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296353
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Craig Topper [Mon, 27 Feb 2017 16:15:25 +0000 (16:15 +0000)]
[X86] Use APInt instead of SmallBitVector for tracking undef elements in constant pool shuffle decoding
Summary:
SmallBitVector uses a malloc for more than 58 bits on a 64-bit target and more than 27 bits on a 32-bit target. Some of the vector types we deal with here use more than those number of elements and therefore cause a malloc.
APInt on the other hand supports up to 64 bits without a malloc. That's the maximum number of bits we need here so we can avoid a malloc for all cases by using APInt. This will incur a minor increase in stack usage due to APInt storing the bit count separately from the data bits unlike SmallBitVector, but that should be ok.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296352
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Amaury Sechet [Mon, 27 Feb 2017 16:09:44 +0000 (16:09 +0000)]
Remove an empty line in icmp-illegal.ll . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296350
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Alexey Bataev [Mon, 27 Feb 2017 16:07:10 +0000 (16:07 +0000)]
[SLP] A test for a fix of PR32038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296349
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Artur Pilipenko [Mon, 27 Feb 2017 15:44:49 +0000 (15:44 +0000)]
Loop predication expand both sides of the widened condition
This is a fix for a loop predication bug which resulted in malformed IR generation.
Loop invariant side of the widened condition is not guaranteed to be available in the preheader as is, so we need to expand it as well. See added unsigned_loop_0_to_n_hoist_length test for example.
Reviewed By: sanjoy, mkazantsev
Differential Revision: https://reviews.llvm.org/D30099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296345
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Sjoerd Meijer [Mon, 27 Feb 2017 14:45:34 +0000 (14:45 +0000)]
AArch64InstPrinter: rewrite of printSysAlias
This is a cleanup/rewrite of the printSysAlias function. This was not using the
tablegen instruction descriptions, but was "manually" decoding the
instructions. This has been replaced with calls to lookup_XYZ_ByEncoding
tablegen calls.
This revealed several problems. First, instruction IVAU had the wrong encoding.
This was cancelled out by the parser that incorrectly matched the wrong
encoding. Second, instruction CVAP was missing from the SystemOperands tablegen
descriptions, so this has been added. And third, the required target features
were not captured in the tablegen descriptions, so support for this has also
been added.
Differential Revision: https://reviews.llvm.org/D30329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296343
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John Brawn [Mon, 27 Feb 2017 14:40:51 +0000 (14:40 +0000)]
[ARM] LSL #0 is an alias of MOV
Currently we handle this correctly in arm, but in thumb we don't which leads to
an unpredictable instruction being emitted for LSL #0 in an IT block and SP not
being permitted in some cases when it should be.
For the thumb2 LSL we can handle this by making LSL #0 an alias of MOV in the
.td file, but for thumb1 we need to handle it in checkTargetMatchPredicate to
get the IT handling right. We also need to adjust the handling of
MOV rd, rn, LSL #0 to avoid generating the 16-bit encoding in an IT block. We
should also adjust it to allow SP in the same way that it is allowed in
MOV rd, rn, but I haven't done that here because it looks like it would take
quite a lot of work to get right.
Additionally correct the selection of the 16-bit shift instructions in
processInstruction, where it was checking if the two registers were equal when
it should have been checking if they were low. It appears that previously this
code was never executed and the 16-bit encoding was selected by default, but
the other changes I've done here have somehow made it start being used.
Differential Revision: https://reviews.llvm.org/D30294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296342
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Artur Pilipenko [Mon, 27 Feb 2017 13:04:23 +0000 (13:04 +0000)]
[DAGCombine] Fix for a load combine bug with non-zero offset patterns on BE targets
This pattern is essentially a i16 load from p+1 address:
%p1.i16 = bitcast i8* %p to i16*
%p2.i8 = getelementptr i8, i8* %p, i64 2
%v1 = load i16, i16* %p1.i16
%v2.i8 = load i8, i8* %p2.i8
%v2 = zext i8 %v2.i8 to i16
%v1.shl = shl i16 %v1, 8
%res = or i16 %v1.shl, %v2
Current implementation would identify %v1 load as the first byte load and would mistakenly emit a i16 load from %p1.i16 address. This patch adds a check that the first byte is loaded from a non-zero offset of the first load address. This way this address can be used as the base address for the combined value. Otherwise just give up combining.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296336
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Artur Pilipenko [Mon, 27 Feb 2017 11:42:54 +0000 (11:42 +0000)]
[DAGCombine] NFC. MatchLoadCombine extract MemoryByteOffset lambda helper
This refactoring will simplify the upcoming change to fix the bug in folding patterns with non-zero offsets on BE targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296332
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Artur Pilipenko [Mon, 27 Feb 2017 11:40:14 +0000 (11:40 +0000)]
[DAGCombine] NFC. MatchLoadCombine remember the first byte provider, not the load node
This refactoring will simplify the upcoming change to fix a bug in folding patterns with non-zero offsets on BE targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296331
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Sjoerd Meijer [Mon, 27 Feb 2017 10:51:11 +0000 (10:51 +0000)]
AArch64AsmParser: don't try to parse “[1]” for non-vector register operands
There are no instructions that have "[1]" as part of the assembly string;
FMOVXDhighr is out of date. This removes dead code.
Differential Revision: https://reviews.llvm.org/D30165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296327
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Konstantin Zhuravlyov [Mon, 27 Feb 2017 07:55:17 +0000 (07:55 +0000)]
[AMDGPU] Runtime metadata fixes:
- Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it:
.amdgpu_runtime_metadata
{ amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: ...
- Make IsaInfo optional, and always emit it.
Differential Revision: https://reviews.llvm.org/D30349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296324
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Brian Cain [Mon, 27 Feb 2017 06:22:17 +0000 (06:22 +0000)]
llvm-mc-fuzzer: add support for assembly
This creates an llvm-mc-disassemble-fuzzer from the existing llvm-mc-fuzzer
and finishing the assemble support in llvm-mc-assemble-fuzzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296323
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Craig Topper [Mon, 27 Feb 2017 06:05:33 +0000 (06:05 +0000)]
[APInt] Use UINT64_MAX instead of ~integerPart(0). NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296322
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Craig Topper [Mon, 27 Feb 2017 06:05:30 +0000 (06:05 +0000)]
[X86] Check for less than 0 rather than explicit compare with -1. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296321
91177308-0d34-0410-b5e6-
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Amaury Sechet [Mon, 27 Feb 2017 01:15:57 +0000 (01:15 +0000)]
Do full codegen for various tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296305
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 26 Feb 2017 21:15:18 +0000 (21:15 +0000)]
[APInt] Use UINT64_MAX instead of ~uint64_t(0ULL). NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296301
91177308-0d34-0410-b5e6-
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Craig Topper [Sun, 26 Feb 2017 19:28:48 +0000 (19:28 +0000)]
[APInt] Use UINT64_MAX instead of ~0ULL. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296300
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Craig Topper [Sun, 26 Feb 2017 19:28:45 +0000 (19:28 +0000)]
[APInt] Remove unnecessary early out from getLowBitsSet. The same case is handled equally well by the next check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296299
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Xin Tong [Sun, 26 Feb 2017 19:08:44 +0000 (19:08 +0000)]
Update comments. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296298
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Daniel Jasper [Sun, 26 Feb 2017 11:09:12 +0000 (11:09 +0000)]
Revert "[CGP] Split some critical edges coming out of indirect branches"
This reverts commit r296149 as it leads to crashes when compiling for
PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296295
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Davide Italiano [Sun, 26 Feb 2017 07:08:20 +0000 (07:08 +0000)]
[LoopDeletion] Modernize and simplify a bit. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296294
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Craig Topper [Sun, 26 Feb 2017 06:45:59 +0000 (06:45 +0000)]
[X86] Fix execution domain for cmpss/sd instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296293
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Craig Topper [Sun, 26 Feb 2017 06:45:56 +0000 (06:45 +0000)]
[AVX-512] Fix execution domain for scalar commutable min/max instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296292
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Craig Topper [Sun, 26 Feb 2017 06:45:54 +0000 (06:45 +0000)]
[AVX-512] Fix execution domain for vmovhpd/lpd/hps/lps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296291
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Craig Topper [Sun, 26 Feb 2017 06:45:51 +0000 (06:45 +0000)]
[AVX-512] Fix the execution domain for AVX-512 integer broadcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296290
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Craig Topper [Sun, 26 Feb 2017 06:45:48 +0000 (06:45 +0000)]
[AVX-512] Disable the redundant patterns in the VPBROADCASTBr_Alt and VPBROADCASTWr_Alt instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296289
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Craig Topper [Sun, 26 Feb 2017 06:45:45 +0000 (06:45 +0000)]
[AVX-512] Fix execution domain for VPMADD52 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296288
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Craig Topper [Sun, 26 Feb 2017 06:45:43 +0000 (06:45 +0000)]
[AVX-512] Use update_llc_test_checks.py to regenerate a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296287
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Craig Topper [Sun, 26 Feb 2017 06:45:40 +0000 (06:45 +0000)]
[AVX-512] Fix the execution domain for VSCALEF instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296286
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Craig Topper [Sun, 26 Feb 2017 06:45:37 +0000 (06:45 +0000)]
[AVX-512] Fix execution domain of scalar VRANGE/REDUCE/GETMANT with sae.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296285
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Craig Topper [Sun, 26 Feb 2017 06:45:35 +0000 (06:45 +0000)]
[X86] Fix the execution domain for scalar SQRT intrinsic instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296284
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Craig Topper [Sun, 26 Feb 2017 06:45:32 +0000 (06:45 +0000)]
[X86] Add an additional CHECK prefix to a test. Some of the cases used it, but it wasn't on the FileCheck command lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296283
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Xin Tong [Sun, 26 Feb 2017 02:11:24 +0000 (02:11 +0000)]
[SCCP] Remove manual folding of terminator instructions.
Summary:
BranchInst, SwitchInst (with non-default case) with Undef as input is not
possible at this point. As we always default-fold terminator to one target in
ResolvedUndefsIn and set the input accordingly.
So we should only have constantint/blockaddress here.
If ConstantFoldTerminator fails, that could mean 2 things.
1. ConstantFoldTerminator is doing something unexpected, i.e. not folding on constantint
or blockaddress and not making blocks that should be dead dead.
2. This is not a terminator on constantint or blockaddress. Its on a constant or
overdefined, then this block should not be dead.
In both cases, we should assert.
Reviewers: davide, efriedma, sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296281
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David L. Jones [Sun, 26 Feb 2017 01:32:35 +0000 (01:32 +0000)]
[X86] Clean up test/CodeGen/X86/2006-03-02-InstrSchedBug.ll
Summary:
Migrated from grep to FileCheck.
Re-indented code, removed boilerplate comments.
Added 'entry' label at beginning of basic block.
Patch by Jorge Gorbe!
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296280
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Nirav Dave [Sun, 26 Feb 2017 01:27:32 +0000 (01:27 +0000)]
Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."
This reverts commit r296252 until 256-bit operations are more efficiently generated in X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296279
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Eric Christopher [Sun, 26 Feb 2017 00:11:58 +0000 (00:11 +0000)]
vec perm can go down either pipeline on P8.
No observable changes, spotted while looking at the scheduling description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296277
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Sanjoy Das [Sat, 25 Feb 2017 22:25:48 +0000 (22:25 +0000)]
Fix signed-unsigned comparison warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296274
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Sanjoy Das [Sat, 25 Feb 2017 20:30:45 +0000 (20:30 +0000)]
[ValueTracking] Don't do an unchecked shift in ComputeNumSignBits
Summary:
Previously we used to return a bogus result, 0, for IR like `ashr %val,
-1`.
I've also added an assert checking that `ComputeNumSignBits` at least
returns 1. That assert found an already checked in test case where we
were returning a bad result for `ashr %val, -1`.
Fixes PR32045.
Reviewers: spatel, majnemer
Reviewed By: spatel, majnemer
Subscribers: efriedma, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D30311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296273
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Simon Pilgrim [Sat, 25 Feb 2017 20:01:58 +0000 (20:01 +0000)]
[APInt] Add APInt::extractBits() method to extract APInt subrange (reapplied)
The current pattern for extract bits in range is typically:
Mask.lshr(BitOffset).trunc(SubSizeInBits);
Which can be particularly slow for large APInts (MaskSizeInBits > 64) as they require the allocation of memory for the temporary variable.
This is another of the compile time issues identified in PR32037 (see also D30265).
This patch adds the APInt::extractBits() helper method which avoids the temporary memory allocation.
Differential Revision: https://reviews.llvm.org/D30336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296272
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Craig Topper [Sat, 25 Feb 2017 19:36:28 +0000 (19:36 +0000)]
[AVX-512] Fix the execution domain for scalar FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296271
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Craig Topper [Sat, 25 Feb 2017 19:18:11 +0000 (19:18 +0000)]
[AVX-512] Fix the execution domain on some instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296270
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Craig Topper [Sat, 25 Feb 2017 19:18:08 +0000 (19:18 +0000)]
[AVX-512] Add an additional test case to show the execution domain for vrqsrtsd is wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296269
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Craig Topper [Sat, 25 Feb 2017 19:18:04 +0000 (19:18 +0000)]
[AVX-512] Use update_llc_test_checks.py to regenerate the avx512er intrinsic test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296268
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Nirav Dave [Sat, 25 Feb 2017 19:11:53 +0000 (19:11 +0000)]
reenable accidentally disabled test NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296266
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Craig Topper [Sat, 25 Feb 2017 18:43:42 +0000 (18:43 +0000)]
[AVX-512] Remove unnecessary masked versions of VCVTSS2SD and VCVTSD2SS using the scalar register class. We only have patterns for the masked intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296264
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Craig Topper [Sat, 25 Feb 2017 18:12:25 +0000 (18:12 +0000)]
[ExecutionDepsFix] Don't make copies of LiveReg objects when collecting operands for soft instructions
Summary:
While collecting operands we make copies of the LiveReg objects which are stored in the LiveRegs array. If the instruction uses the same register multiple times we end up with multiple copies. Later we iterate through the collected list of LiveReg objects and merge DomainValues. In the process of doing this the merge function can change the contents of the original LiveReg object in the LiveRegs array, but not the copies that have been made. So when we get to the second usage of the register we end up seeing a stale copy of the LiveReg object.
To fix this I've stopped copying and now just store a pointer to the original LiveReg object. Another option might be to avoid adding the same register to the Regs array twice, but this approach seemed simpler.
The included test case exposes this bug due to an AVX-512 masked OR instruction using the same register for the passthru operand and one of the inputs to the OR operation.
Fixes PR30284.
Reviewers: RKSimon, stoklund, MatzeB, spatel, myatsina
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296260
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Artyom Skrobov [Sat, 25 Feb 2017 17:18:09 +0000 (17:18 +0000)]
No need to copy the variable [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296259
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NAKAMURA Takumi [Sat, 25 Feb 2017 17:04:23 +0000 (17:04 +0000)]
Revert r296215, "[PDB] General improvements to Stream library." and followings.
r296215, "[PDB] General improvements to Stream library."
r296217, "Disable BinaryStreamTest.StreamReaderObject temporarily."
r296220, "Re-enable BinaryStreamTest.StreamReaderObject."
r296244, "[PDB] Disable some tests that are breaking bots."
r296249, "Add static_cast to silence -Wc++11-narrowing."
std::errc::no_buffer_space should be used for OS-oriented errors for socket transmission.
(Seek discussions around llvm/xray.)
I could substitute s/no_buffer_space/others/g, but I revert whole them ATM.
Could we define and use LLVM errors there?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296258
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Amaury Sechet [Sat, 25 Feb 2017 16:46:47 +0000 (16:46 +0000)]
Update various test's codegen. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296257
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Amaury Sechet [Sat, 25 Feb 2017 15:58:34 +0000 (15:58 +0000)]
Add test for known bits in uaddo and saddo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296255
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Artyom Skrobov [Sat, 25 Feb 2017 15:17:16 +0000 (15:17 +0000)]
The automatic CHECK: to CHECK-LABEL: conversion, back in 2013,
had missed most labels in this test because they didn't end
with a colon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296254
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Victor Leschuk [Sat, 25 Feb 2017 13:15:57 +0000 (13:15 +0000)]
[DebugInfo] Skip implicit_const attributes when dumping .debug_info. NFC.
When dumping .debug_info section we loop through all attributes mentioned in
.debug_abbrev section and dump values using DWARFFormValue::extractValue().
We need to skip implicit_const attributes here as their values are not
really located in .debug_info but directly in .debug_abbrev. This patch fixes
triggered assert() in DWARFFormValue::extractValue() caused by trying to
access implicit_const values from .debug_info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296253
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Nirav Dave [Sat, 25 Feb 2017 11:43:58 +0000 (11:43 +0000)]
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296252
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Piotr Padlewski [Sat, 25 Feb 2017 10:33:37 +0000 (10:33 +0000)]
[Doc] Modernize programmers manual
Summary:
Fixed bunch of for loops to range based for loop
and bunch of rendundat types with auto.
Reviewers: echristo, silvas, chandlerc
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D30338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296251
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Xin Tong [Sat, 25 Feb 2017 08:10:28 +0000 (08:10 +0000)]
Empty line. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296250
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Daniel Jasper [Sat, 25 Feb 2017 07:53:36 +0000 (07:53 +0000)]
Add static_cast to silence -Wc++11-narrowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296249
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Zachary Turner [Sat, 25 Feb 2017 05:57:57 +0000 (05:57 +0000)]
[PDB] Disable some tests that are breaking bots.
This has to do with big endian, but I can't fix it until
Monday. The code itself is fine, just the tests are wrong.
Disabling 3 tests for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296244
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