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George Burgess IV [Thu, 25 Aug 2016 02:15:54 +0000 (02:15 +0000)]
Make buildbots happy.
"warning: extra ‘;’ [-Wpedantic]"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279703
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Kyle Butt [Thu, 25 Aug 2016 01:37:07 +0000 (01:37 +0000)]
TailDuplication: Don't pass MMI separately from MF. NFC
MMI must match the function passed, and MF has a handle on MMI. Use that instead
of accepting it as separate argument. No Functional Change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279701
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Kyle Butt [Thu, 25 Aug 2016 01:37:03 +0000 (01:37 +0000)]
TailDuplication: Save MF and reduce number of parameters. NFC
Save the function in the class, and then don't pass it around. This reduces the
number of parameters and makes calls to member functions simpler.
No Functional Change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279700
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George Burgess IV [Thu, 25 Aug 2016 01:29:55 +0000 (01:29 +0000)]
Update a comment.
r279696, which changed `LLVM_CONSTEXPR AliasAttr` to `const AliasAttr`,
made this comment make less sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279699
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Matthias Braun [Thu, 25 Aug 2016 01:27:13 +0000 (01:27 +0000)]
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of
running after register and simply describes that no vregs are used in
a machine function. With that we can simply compute the property and do
not need to dump/parse it in .mir files.
Differential Revision: http://reviews.llvm.org/D23850
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279698
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Kostya Serebryany [Thu, 25 Aug 2016 01:25:03 +0000 (01:25 +0000)]
[libFuzzer] simplify the code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279697
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George Burgess IV [Thu, 25 Aug 2016 01:05:08 +0000 (01:05 +0000)]
Make some LLVM_CONSTEXPR variables const. NFC.
This patch changes LLVM_CONSTEXPR variable declarations to const
variable declarations, since LLVM_CONSTEXPR expands to nothing if the
current compiler doesn't support constexpr. In all of the changed
cases, it looks like the code intended the variable to be const instead
of sometimes-constexpr sometimes-not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279696
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Eugene Zelenko [Thu, 25 Aug 2016 00:45:04 +0000 (00:45 +0000)]
Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes.
Differential revision: https://reviews.llvm.org/D23861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279695
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Xinliang David Li [Thu, 25 Aug 2016 00:26:32 +0000 (00:26 +0000)]
[Profile] Propagate branch metadata properly in instcombine
Differential Revision: http://reviews.llvm.org/D23590
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279693
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Kyle Butt [Thu, 25 Aug 2016 00:06:52 +0000 (00:06 +0000)]
Test: Add REQUIRES: asserts to test that now requires stats.
Test was modified in r279670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279690
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Kostya Serebryany [Wed, 24 Aug 2016 23:10:17 +0000 (23:10 +0000)]
[libFuzzer] make a test more deterministic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279686
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Sanjay Patel [Wed, 24 Aug 2016 23:03:36 +0000 (23:03 +0000)]
[InstCombine] move foldICmpDivConstConst() contents to foldICmpDivConstant(); NFCI
There was no logic in foldICmpDivConstant, so no need for a separate function.
The code is directly copy/pasted, so further cleanups to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279685
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Evgeny Stupachenko [Wed, 24 Aug 2016 23:01:33 +0000 (23:01 +0000)]
The patch improves ValueTracking on left shift with nsw flag.
Summary:
The patch fixes PR28946.
Reviewers: majnemer, sanjoy
Differential Revision: http://reviews.llvm.org/D23296
From: Li Huang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279684
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Heejin Ahn [Wed, 24 Aug 2016 22:53:00 +0000 (22:53 +0000)]
[WebAssembly] Change a comment line
Test for commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279683
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Matthias Braun [Wed, 24 Aug 2016 22:41:46 +0000 (22:41 +0000)]
MIRYamlMapping cleanup
Missed two lines got lost when cherry picking old commits to master.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279682
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Krzysztof Parzyszek [Wed, 24 Aug 2016 22:36:35 +0000 (22:36 +0000)]
[Hexagon] Check for block end when skipping debug instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279681
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Matthias Braun [Wed, 24 Aug 2016 22:34:06 +0000 (22:34 +0000)]
MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279680
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Matthias Braun [Wed, 24 Aug 2016 22:32:11 +0000 (22:32 +0000)]
Missed a test in my last commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279679
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Krzysztof Parzyszek [Wed, 24 Aug 2016 22:27:36 +0000 (22:27 +0000)]
[Hexagon] Change insertion of expand-condsets pass to avoid memory leaks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279678
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Sanjay Patel [Wed, 24 Aug 2016 22:22:06 +0000 (22:22 +0000)]
[InstCombine] use m_APInt to allow icmp eq/ne (shr X, C2), C folds for splat constant vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279677
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Matthias Braun [Wed, 24 Aug 2016 22:17:45 +0000 (22:17 +0000)]
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it
tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there
is not need to change it or save/parse it in a .mir file.
Make the field const and move the initialization LiveIntervalAnalysis to the
MachineRegisterInfo constructor. Also cleanup some code and fix some
instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead
of TargetSubtargetInfo::enableSubRegLiveness().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279676
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Kyle Butt [Wed, 24 Aug 2016 21:34:27 +0000 (21:34 +0000)]
CodeGen: If Convert blocks that would form a diamond when tail-merged.
The following function currently relies on tail-merging for if
conversion to succeed. The common tail of cond_true and cond_false is
extracted, and this then forms a diamond pattern that can be
successfully if converted.
If this block does not get extracted, either because tail-merging is
disabled or the threshold is higher, we should still recognize this
pattern and if-convert it.
Fixed a regression in the original commit. Need to un-reverse branches after
reversing them, or other conversions go awry.
define i32 @t2(i32 %a, i32 %b) nounwind {
entry:
%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp1434, label %bb17, label %bb.outer
bb.outer: ; preds = %cond_false, %entry
%b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ]
%a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ]
br label %bb
bb: ; preds = %cond_true, %bb.outer
%indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ]
%tmp. = sub i32 0, %b_addr.021.0.ph
%tmp.40 = mul i32 %indvar, %tmp.
%a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph
%tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph
br i1 %tmp3, label %cond_true, label %cond_false
cond_true: ; preds = %bb
%tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph
%tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph
%indvar.next = add i32 %indvar, 1
br i1 %tmp1437, label %bb17, label %bb
cond_false: ; preds = %bb
%tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0
%tmp14 = icmp eq i32 %a_addr.026.0, %tmp10
br i1 %tmp14, label %bb17, label %bb.outer
bb17: ; preds = %cond_false, %cond_true, %entry
%a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ]
ret i32 %a_addr.026.1
}
Without tail-merging or diamond-tail if conversion:
LBB1_1: @ %bb
@ =>This Inner Loop Header: Depth=1
cmp r0, r1
ble LBB1_3
@ BB#2: @ %cond_true
@ in Loop: Header=BB1_1 Depth=1
subs r0, r0, r1
cmp r1, r0
it ne
cmpne r0, r1
bgt LBB1_4
LBB1_3: @ %cond_false
@ in Loop: Header=BB1_1 Depth=1
subs r1, r1, r0
cmp r1, r0
bne LBB1_1
LBB1_4: @ %bb17
bx lr
With diamond-tail if conversion, but without tail-merging:
@ BB#0: @ %entry
cmp r0, r1
it eq
bxeq lr
LBB1_1: @ %bb
@ =>This Inner Loop Header: Depth=1
cmp r0, r1
ite le
suble r1, r1, r0
subgt r0, r0, r1
cmp r1, r0
bne LBB1_1
@ BB#2: @ %bb17
bx lr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279671
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Kyle Butt [Wed, 24 Aug 2016 21:34:24 +0000 (21:34 +0000)]
IfConversion: Rescan diamonds.
The cost of predicating a diamond is only the instructions that are not shared
between the two branches. Additionally If a predicate clobbering instruction
occurs in the shared portion of the branches (e.g. a cond move), it may still
be possible to if convert the sub-cfg. This change handles these two facts by
rescanning the non-shared portion of a diamond sub-cfg to recalculate both the
predication cost and whether both blocks are pred-clobbering.
Fixed 2 bugs before recommitting. Branch instructions must be compared and found
identical before diamond conversion. Also, predicate-clobbering instructions in
the shared prefix disqualifies a potential diamond conversion. Includes tests
for both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279670
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Tim Northover [Wed, 24 Aug 2016 21:21:29 +0000 (21:21 +0000)]
ARM: don't diagnose cbz/cbnz to Thumb functions.
A branch-distance to a Thumb function shouldn't be forced to be odd for
CBZ/CBNZ instructions because (assuming it's within range), it's going to be a
valid, even offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279665
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Changpeng Fang [Wed, 24 Aug 2016 20:35:23 +0000 (20:35 +0000)]
AMDGCN/SI: Implement readlane/readfirstlane intrinsics
Summary:
This patch implements readlane/readfirstlane intrinsics.
TODO: need to define a new register class to consider the case
that the source could be a vector register or M0.
Reviewed by:
arsenm and tstellarAMD
Differential Revision:
http://reviews.llvm.org/D22489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279660
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Rafael Espindola [Wed, 24 Aug 2016 19:02:29 +0000 (19:02 +0000)]
Use isTargetMachO instead of isTargetDarwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279655
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Simon Pilgrim [Wed, 24 Aug 2016 18:40:53 +0000 (18:40 +0000)]
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support
These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279652
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David Blaikie [Wed, 24 Aug 2016 18:29:49 +0000 (18:29 +0000)]
DebugInfo: Add flag to CU to disable emission of inline debug info into the skeleton CU
In cases where .dwo/.dwp files are guaranteed to be available, skipping
the extra online (in the .o file) inline info can save a substantial
amount of space - see the original r221306 for more details there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279650
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Matthew Simpson [Wed, 24 Aug 2016 18:23:17 +0000 (18:23 +0000)]
[LV] Unify vector and scalar maps
This patch unifies the data structures we use for mapping instructions from the
original loop to their corresponding instructions in the new loop. Previously,
we maintained two distinct maps for this purpose: WidenMap and ScalarIVMap.
WidenMap maintained the vector values each instruction from the old loop was
represented with, and ScalarIVMap maintained the scalar values each scalarized
induction variable was represented with. With this patch, all values created
for the new loop are maintained in VectorLoopValueMap.
The change allows for several simplifications. Previously, when an instruction
was scalarized, we had to insert the scalar values into vectors in order to
maintain the mapping in WidenMap. Then, if a user of the scalarized value was
also scalar, we had to extract the scalar values from the temporary vector we
created. We now aovid these unnecessary scalar-to-vector-to-scalar conversions.
If a scalarized value is used by a scalar instruction, the scalar value is used
directly. However, if the scalarized value is needed by a vector instruction,
we generate the needed insertelement instructions on-demand.
A common idiom in several locations in the code (including the scalarization
code), is to first get the vector values an instruction from the original loop
maps to, and then extract a particular scalar value. This patch adds
getScalarValue for this purpose along side getVectorValue as an interface into
VectorLoopValueMap. These functions work together to return the requested
values if they're available or to produce them if they're not.
The mapping has also be made less permissive. Entries can be added to
VectorLoopValue map with the new initVector and initScalar functions.
getVectorValue has been modified to return a constant reference to the mapped
entries.
There's no real functional change with this patch; however, in some cases we
will generate slightly different code. For example, instead of an insertelement
sequence following the definition of an instruction, it will now precede the
first use of that instruction. This can be seen in the test case changes.
Differential Revision: https://reviews.llvm.org/D23169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279649
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Evandro Menezes [Wed, 24 Aug 2016 18:17:30 +0000 (18:17 +0000)]
[AArch64] Adjust the feature set for Exynos M1.
Enable zero cycle zeroing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279648
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Sanjoy Das [Wed, 24 Aug 2016 18:10:21 +0000 (18:10 +0000)]
[SCCP] Don't delete side-effecting instructions
I'm not sure if the `!isa<CallInst>(Inst) &&
!isa<TerminatorInst>(Inst))` bit is correct either, but this fixes the
case we know is broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279647
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Simon Pilgrim [Wed, 24 Aug 2016 18:07:53 +0000 (18:07 +0000)]
[X86][SSE] Add support for combining VZEXT_MOVL target shuffles
Includes adding more general support for the pattern: VZEXT_MOVL(VZEXT_LOAD(ptr)) -> VZEXT_LOAD(ptr)
This has unearthed a couple of latent poor codegen issues (MINSS/MAXSS scalar load folding and MOVDDUP/BROADCAST load folding patterns), which will be fixed shortly.
Its also reduced a couple of tests so that they no longer reach the instruction threshold necessary to be combined to PSHUFB (see PR26183).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279646
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Krzysztof Parzyszek [Wed, 24 Aug 2016 17:17:39 +0000 (17:17 +0000)]
[Hexagon] Enable subregister liveness tracking
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279642
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Krzysztof Parzyszek [Wed, 24 Aug 2016 16:36:37 +0000 (16:36 +0000)]
[Hexagon] Remove the utilization of IMPLICIT_DEFs from expand-condsets
This is no longer necessary, because since r279625 the subregister
liveness properly accounts for read-undefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279637
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Nico Weber [Wed, 24 Aug 2016 16:34:54 +0000 (16:34 +0000)]
fix typo 'varaible' in assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279636
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Tim Northover [Wed, 24 Aug 2016 15:37:51 +0000 (15:37 +0000)]
GlobalISel: fix cmp test to be in SSA form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279633
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Teresa Johnson [Wed, 24 Aug 2016 15:11:47 +0000 (15:11 +0000)]
[ThinLTO/gold] Add caching support to gold-plugin
Summary:
With support now in the new LTO API for caching (r279576), add
optional ThinLTO caching in the gold-plugin.
Reviewers: mehdi_amini
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D23836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279631
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Simon Pilgrim [Wed, 24 Aug 2016 15:07:11 +0000 (15:07 +0000)]
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279630
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Wei Ding [Wed, 24 Aug 2016 14:59:47 +0000 (14:59 +0000)]
AMDGPU : Add V_SAD_U32 instruction pattern.
Differential Revision: http://reviews.llvm.org/D23069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279629
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Ying Yi [Wed, 24 Aug 2016 14:27:23 +0000 (14:27 +0000)]
[llvm-cov] Add the project summary to each source file coverage report.
This patch includes the following changes:
- Included header "Code coverage report" and include the date that the report was created.
- Included title (as specified in a command line option, (i.e llvm-cov -project-title="Simple Test")
- In the summary, list the elf files that the source code file has contributed to.
- Used column heading for "Line No.", "Count No.", Source".
Differential Revision: https://reviews.llvm.org/D23345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279628
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Sanjay Patel [Wed, 24 Aug 2016 13:55:55 +0000 (13:55 +0000)]
[InstCombine] add assert and explanatory comment for fold removed in r279568; NFC
I deleted a fold from InstCombine at:
https://reviews.llvm.org/rL279568
because it (like any InstCombine to a constant?) should always happen in InstSimplify,
however, it's not obvious what the assumptions are in the remaining code.
Add a comment and assert to make it clearer.
Differential Revision: https://reviews.llvm.org/D23819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279626
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Krzysztof Parzyszek [Wed, 24 Aug 2016 13:37:55 +0000 (13:37 +0000)]
Create subranges for new intervals resulting from live interval splitting
The register allocator can split a live interval of a register into a set
of smaller intervals. After the allocation of registers is complete, the
rewriter will modify the IR to replace virtual registers with the corres-
ponding physical registers. At this stage, if a register corresponding
to a subregister of a virtual register is used, the rewriter will check
if that subregister is undefined, and if so, it will add the <undef> flag
to the machine operand. The function verifying liveness of the subregis-
ter would assume that it is undefined, unless any of the subranges of the
live interval proves otherwise.
The problem is that the live intervals created during splitting do not
have any subranges, even if the original parent interval did. This could
result in the <undef> flag placed on a register that is actually defined.
Differential Revision: http://reviews.llvm.org/D21189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279625
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Simon Dardis [Wed, 24 Aug 2016 13:00:47 +0000 (13:00 +0000)]
[mips] Preparatory work for a generic scheduler
Extend instruction definitions from nearly all ISAs to include
appropriate instruction itineraries. Change MIPS16s gp prologue
generation to use real instructions instead of using a pseudo
instruction.
Reviewers: dsanders, vkalintiris
Differential Review: https://reviews.llvm.org/D23548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279623
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Simon Pilgrim [Wed, 24 Aug 2016 12:42:31 +0000 (12:42 +0000)]
[X86][AVX2] Ensure on 32-bit targets that we broadcast f64 types not i64 (PR29101)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279622
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Simon Pilgrim [Wed, 24 Aug 2016 11:56:15 +0000 (11:56 +0000)]
[X86][F16C] Regenerated f16c tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279621
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Gil Rapaport [Wed, 24 Aug 2016 11:37:57 +0000 (11:37 +0000)]
[Loop Vectorizer] Support predication of div/rem
div/rem instructions in basic blocks that require predication currently prevent
vectorization. This patch extends the existing mechanism for predicating stores
to handle other instructions and leverages it to predicate divs and rems.
Differential Revision: https://reviews.llvm.org/D22918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279620
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Simon Pilgrim [Wed, 24 Aug 2016 10:46:40 +0000 (10:46 +0000)]
[X86][SSE] Add support for 32-bit element vectors to X86ISD::VZEXT_LOAD
Consecutive load matching (EltsFromConsecutiveLoads) currently uses VZEXT_LOAD (load scalar into lowest element and zero uppers) for vXi64 / vXf64 vectors only.
For vXi32 / vXf32 vectors it instead creates a scalar load, SCALAR_TO_VECTOR and finally VZEXT_MOVL (zero upper vector elements), relying on tablegen patterns to match this into an equivalent of VZEXT_LOAD.
This patch adds the VZEXT_LOAD patterns for vXi32 / vXf32 vectors directly and updates EltsFromConsecutiveLoads to use this.
This has proven necessary to allow us to easily make VZEXT_MOVL a full member of the target shuffle set - without this change the call to combineShuffle (which is the main caller of EltsFromConsecutiveLoads) tended to recursively recreate VZEXT_MOVL nodes......
Differential Revision: https://reviews.llvm.org/D23673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279619
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Chandler Carruth [Wed, 24 Aug 2016 09:37:14 +0000 (09:37 +0000)]
[PM] Introduce basic update capabilities to the new PM's CGSCC pass
manager, including both plumbing and logic to handle function pass
updates.
There are three fundamentally tied changes here:
1) Plumbing *some* mechanism for updating the CGSCC pass manager as the
CG changes while passes are running.
2) Changing the CGSCC pass manager infrastructure to have support for
the underlying graph to mutate mid-pass run.
3) Actually updating the CG after function passes run.
I can separate them if necessary, but I think its really useful to have
them together as the needs of #3 drove #2, and that in turn drove #1.
The plumbing technique is to extend the "run" method signature with
extra arguments. We provide the call graph that intrinsically is
available as it is the basis of the pass manager's IR units, and an
output parameter that records the results of updating the call graph
during an SCC passes's run. Note that "...UpdateResult" isn't a *great*
name here... suggestions very welcome.
I tried a pretty frustrating number of different data structures and such
for the innards of the update result. Every other one failed for one
reason or another. Sometimes I just couldn't keep the layers of
complexity right in my head. The thing that really worked was to just
directly provide access to the underlying structures used to walk the
call graph so that their updates could be informed by the *particular*
nature of the change to the graph.
The technique for how to make the pass management infrastructure cope
with mutating graphs was also something that took a really, really large
number of iterations to get to a place where I was happy. Here are some
of the considerations that drove the design:
- We operate at three levels within the infrastructure: RefSCC, SCC, and
Node. In each case, we are working bottom up and so we want to
continue to iterate on the "lowest" node as the graph changes. Look at
how we iterate over nodes in an SCC running function passes as those
function passes mutate the CG. We continue to iterate on the "lowest"
SCC, which is the one that continues to contain the function just
processed.
- The call graph structure re-uses SCCs (and RefSCCs) during mutation
events for the *highest* entry in the resulting new subgraph, not the
lowest. This means that it is necessary to continually update the
current SCC or RefSCC as it shifts. This is really surprising and
subtle, and took a long time for me to work out. I actually tried
changing the call graph to provide the opposite behavior, and it
breaks *EVERYTHING*. The graph update algorithms are really deeply
tied to this particualr pattern.
- When SCCs or RefSCCs are split apart and refined and we continually
re-pin our processing to the bottom one in the subgraph, we need to
enqueue the newly formed SCCs and RefSCCs for subsequent processing.
Queuing them presents a few challenges:
1) SCCs and RefSCCs use wildly different iteration strategies at
a high level. We end up needing to converge them on worklist
approaches that can be extended in order to be able to handle the
mutations.
2) The order of the enqueuing need to remain bottom-up post-order so
that we don't get surprising order of visitation for things like
the inliner.
3) We need the worklists to have set semantics so we don't duplicate
things endlessly. We don't need a *persistent* set though because
we always keep processing the bottom node!!!! This is super, super
surprising to me and took a long time to convince myself this is
correct, but I'm pretty sure it is... Once we sink down to the
bottom node, we can't re-split out the same node in any way, and
the postorder of the current queue is fixed and unchanging.
4) We need to make sure that the "current" SCC or RefSCC actually gets
enqueued here such that we re-visit it because we continue
processing a *new*, *bottom* SCC/RefSCC.
- We also need the ability to *skip* SCCs and RefSCCs that get merged
into a larger component. We even need the ability to skip *nodes* from
an SCC that are no longer part of that SCC.
This led to the design you see in the patch which uses SetVector-based
worklists. The RefSCC worklist is always empty until an update occurs
and is just used to handle those RefSCCs created by updates as the
others don't even exist yet and are formed on-demand during the
bottom-up walk. The SCC worklist is pre-populated from the RefSCC, and
we push new SCCs onto it and blacklist existing SCCs on it to get the
desired processing.
We then *directly* update these when updating the call graph as I was
never able to find a satisfactory abstraction around the update
strategy.
Finally, we need to compute the updates for function passes. This is
mostly used as an initial customer of all the update mechanisms to drive
their design to at least cover some real set of use cases. There are
a bunch of interesting things that came out of doing this:
- It is really nice to do this a function at a time because that
function is likely hot in the cache. This means we want even the
function pass adaptor to support online updates to the call graph!
- To update the call graph after arbitrary function pass mutations is
quite hard. We have to build a fairly comprehensive set of
data structures and then process them. Fortunately, some of this code
is related to the code for building the cal graph in the first place.
Unfortunately, very little of it makes any sense to share because the
nature of what we're doing is so very different. I've factored out the
one part that made sense at least.
- We need to transfer these updates into the various structures for the
CGSCC pass manager. Once those were more sanely worked out, this
became relatively easier. But some of those needs necessitated changes
to the LazyCallGraph interface to make it significantly easier to
extract the changed SCCs from an update operation.
- We also need to update the CGSCC analysis manager as the shape of the
graph changes. When an SCC is merged away we need to clear analyses
associated with it from the analysis manager which we didn't have
support for in the analysis manager infrsatructure. New SCCs are easy!
But then we have the case that the original SCC has its shape changed
but remains in the call graph. There we need to *invalidate* the
analyses associated with it.
- We also need to invalidate analyses after we *finish* processing an
SCC. But the analyses we need to invalidate here are *only those for
the newly updated SCC*!!! Because we only continue processing the
bottom SCC, if we split SCCs apart the original one gets invalidated
once when its shape changes and is not processed farther so its
analyses will be correct. It is the bottom SCC which continues being
processed and needs to have the "normal" invalidation done based on
the preserved analyses set.
All of this is mostly background and context for the changes here.
Many thanks to all the reviewers who helped here. Especially Sanjoy who
caught several interesting bugs in the graph algorithms, David, Sean,
and others who all helped with feedback.
Differential Revision: http://reviews.llvm.org/D21464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279618
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Mehdi Amini [Wed, 24 Aug 2016 05:50:07 +0000 (05:50 +0000)]
Tentatively fix gold-plugin test: ThinLTO objects start at offset 0 now.
Annoyingly, incremental builds don't detect these kind of issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279612
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Gor Nishanov [Wed, 24 Aug 2016 05:20:30 +0000 (05:20 +0000)]
[Coroutines] Fix unused var warning in release build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279610
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Gor Nishanov [Wed, 24 Aug 2016 04:44:35 +0000 (04:44 +0000)]
[Coroutines] Part 8: Coroutine Frame Building algorithm
Summary:
This patch adds coroutine frame building algorithm. Now, simple coroutines such as ex0.ll and ex1.ll (first examples from docs\Coroutines.rst can be compiled).
Documentation and overview is here: http://llvm.org/docs/Coroutines.html.
Upstreaming sequence (rough plan)
1.Add documentation. (https://reviews.llvm.org/D22603)
2.Add coroutine intrinsics. (https://reviews.llvm.org/D22659)
...
7. Split coroutine into subfunctions. (https://reviews.llvm.org/D23461)
8. Coroutine Frame Building algorithm <= we are here
9. Add f.cleanup subfunction.
10+. The rest of the logic
Reviewers: majnemer
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D23586
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279609
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Chandler Carruth [Wed, 24 Aug 2016 03:42:51 +0000 (03:42 +0000)]
Preserve a pointer to the newly allocated signal stack as well. That too
is flagged by LSan at least among leak detectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279605
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Matthias Braun [Wed, 24 Aug 2016 02:32:29 +0000 (02:32 +0000)]
TargetSchedule: Do not consider subregister definitions as reads.
We should not consider subregister definitions as reads for schedule
model purposes (they are just modeled as reads of the overal vreg for
liveness calculation purposes, the CPU instructions are not actually
reading).
Unfortunately I cannot submit a test for this as it requires a target
which uses ReadAdvance annotation in the scheduling model and has
subregister liveness enabled at the same time, which is only the case on
an out of tree target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279604
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Matthias Braun [Wed, 24 Aug 2016 01:52:46 +0000 (01:52 +0000)]
CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
Re-apply this patch, hopefully I will get away without any warnings
in the constructor now.
This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.
This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.
Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.
Differential Revision: http://reviews.llvm.org/D23736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279602
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Kostya Serebryany [Wed, 24 Aug 2016 01:38:42 +0000 (01:38 +0000)]
[libFuzzer] use __attribute__((target("popcnt"))) only on x86_64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279601
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Matthias Braun [Wed, 24 Aug 2016 01:32:41 +0000 (01:32 +0000)]
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.
Differential Revision: http://reviews.llvm.org/D22722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279600
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Richard Smith [Wed, 24 Aug 2016 00:54:49 +0000 (00:54 +0000)]
Increase the size of the sigaltstack used by LLVM signal handlers. 8KB is not
sufficient in some cases; increase to 64KB, which should be enough for anyone :)
Patch by github.com/bryant!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279599
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Matthias Braun [Wed, 24 Aug 2016 00:42:05 +0000 (00:42 +0000)]
MachineModuleInfo: Avoid dummy constructor, use INITIALIZE_TM_PASS
Change this pass constructor to just accept a const TargetMachine * and
use INITIALIZE_TM_PASS, that way we can get rid of the dummy
constructor. The pass will still fail when calling the default
constructor leading to TM == nullptr, this is no different than before
but is more in line what other codegen passes are doing and avoids the
dummy constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279598
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David Callahan [Wed, 24 Aug 2016 00:10:06 +0000 (00:10 +0000)]
[ADCE] Add control dependence computation
Summary:
This is part of a serious of patches to evolve ADCE.cpp to support
removing of unnecessary control flow.
This patch adds the ability to compute control dependences using
the iterated dominance frontier. We extend the liveness propagation
to alternate between data and control dependences until convergences.
Modify the pass manager intergation to compute the post-dominator tree
needed for iterator dominance frontier.
We still force all terminators live for now until we add code to
handlinge removing control flow in a later patch.
No changes to effective behavior with this patch
Previous patches:
D23225 [ADCE] Modify data structures to support removing control flow
D23065 [ADCE] Refactor anticipating new functionality (NFC)
D23102 [ADCE] Refactoring for new functionality (NFC)
Reviewers: nadav, majnemer, mehdi_amini
Subscribers: twoh, freik, llvm-commits
Differential Revision: https://reviews.llvm.org/D23559
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279594
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Philip Reames [Tue, 23 Aug 2016 23:58:08 +0000 (23:58 +0000)]
[stackmaps] Remove an unneeded member variable [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279590
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Kostya Serebryany [Tue, 23 Aug 2016 23:43:08 +0000 (23:43 +0000)]
[libFuzzer] fix link in docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279589
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Kostya Serebryany [Tue, 23 Aug 2016 23:37:37 +0000 (23:37 +0000)]
[libFuzzer] collect 64 states for value profile, not 65
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279588
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Kostya Serebryany [Tue, 23 Aug 2016 23:36:21 +0000 (23:36 +0000)]
[libFuzzer] docs on value profile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279587
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Philip Reames [Tue, 23 Aug 2016 23:33:29 +0000 (23:33 +0000)]
[stackmaps] More extraction of common code [NFCI]
General cleanup before starting to work on the part I want to actually change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279586
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Michael Zolotukhin [Tue, 23 Aug 2016 23:13:15 +0000 (23:13 +0000)]
[LoopUnroll] By default disable unrolling when optimizing for size.
Summary:
In clang commit r268509 we started to invoke loop-unroll pass from the
driver even under -Os. However, we happen to not initialize optsize
thresholds properly, which si fixed with this change.
r268509 led to some big compile time regressions, because we started to
unroll some loops that we didn't unroll before. With this change I hope
to recover most of the regressions. We still are slightly slower than
before, because we do some checks here and there in loop-unrolling
before we bail out, but at least the slowdown is not that huge now.
Reviewers: hfinkel, chandlerc
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D23388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279585
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Richard Smith [Tue, 23 Aug 2016 22:21:58 +0000 (22:21 +0000)]
Don't use "return {...}" to initialize a std::tuple. This has only been valid
since 2015 (n4387), though it's allowed by a library DR so new implementations
accept it in their C++11 modes...
This should unbreak the build with libstdc++ 4.9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279583
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Richard Smith [Tue, 23 Aug 2016 22:14:15 +0000 (22:14 +0000)]
#ifdef out validation code when asserts are disabled to remove unused variable
warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279582
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Richard Smith [Tue, 23 Aug 2016 22:10:46 +0000 (22:10 +0000)]
Remove unused data member to unbreak -Werror builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279581
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Richard Smith [Tue, 23 Aug 2016 22:08:27 +0000 (22:08 +0000)]
Revert r279564. It introduces undefined behavior (binding a reference to a
dereferenced null pointer) in MachineModuleInfo::MachineModuleInfo that causes
-Werror builds (including several buildbots) to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279580
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Tim Northover [Tue, 23 Aug 2016 22:07:31 +0000 (22:07 +0000)]
GlobalISel: add some G_TRUNCs to make icmp test valid MIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279579
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Sanjay Patel [Tue, 23 Aug 2016 22:05:55 +0000 (22:05 +0000)]
[InstCombine] use local variables for repeated values; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279578
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Petr Hosek [Tue, 23 Aug 2016 21:34:53 +0000 (21:34 +0000)]
[MC] Support .dc directives in assembler parser
While these directives are mostly aliases for the existing integer
and float value directives, some of them like .dc.a have no direct
equivalents and are sometimes being used for convenience.
Differential Revision: https://reviews.llvm.org/D23810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279577
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Mehdi Amini [Tue, 23 Aug 2016 21:30:12 +0000 (21:30 +0000)]
[ThinLTO] Add caching to the new LTO API
Add the ability to plug a cache on the LTO API.
I tried to write such that a linker implementation can
control the cache backend. This is intrusive and I'm
not totally happy with it, but I can't figure out a
better design right now.
Differential Revision: https://reviews.llvm.org/D23599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279576
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Sanjay Patel [Tue, 23 Aug 2016 21:25:13 +0000 (21:25 +0000)]
[InstCombine] move foldICmpShrConstConst() contents to foldICmpShrConst(); NFCI
There will only be 3 lines of code in foldICmpShrConst() when the cleanup is done,
so it doesn't make much sense to have a separate function for a single fold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279575
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Philip Reames [Tue, 23 Aug 2016 21:21:43 +0000 (21:21 +0000)]
[stackmaps] Extract out magic constants [NFCI]
This is a first step towards clarifying the exact MI semantics of stackmap's "live values".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279574
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Matthias Braun [Tue, 23 Aug 2016 21:19:49 +0000 (21:19 +0000)]
MachineFunction: Introduce NoPHIs property
I want to compute the SSA property of .mir files automatically in
upcoming patches. The problem with this is that some inputs will be
reported as static single assignment with some passes claiming not to
support SSA form. In reality though those passes do not support PHI
instructions => Track the presence of PHI instructions separate from the
SSA property.
Differential Revision: https://reviews.llvm.org/D22719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279573
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Tim Northover [Tue, 23 Aug 2016 21:11:36 +0000 (21:11 +0000)]
GlobalISel: add forgotten test-case for G_ICMP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279569
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Sanjay Patel [Tue, 23 Aug 2016 21:01:35 +0000 (21:01 +0000)]
[InstCombine] remove icmp shr folds that are already handled by InstSimplify
AFAICT, these already worked in all cases for scalar types, and I enhanced
the code to work for vector types in:
https://reviews.llvm.org/rL279543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279568
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Tim Northover [Tue, 23 Aug 2016 21:01:33 +0000 (21:01 +0000)]
GlobalISel: make truncate/extend casts uniform
They really should have both types represented, but early variants were created
before MachineInstrs could have multiple types so they're rather ambiguous.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279567
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Tim Northover [Tue, 23 Aug 2016 21:01:26 +0000 (21:01 +0000)]
GlobalISel: legalize integer comparisons on AArch64.
Next step is doing both legalizations at the same time! Marvel at GlobalISel's
cunning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279566
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Tim Northover [Tue, 23 Aug 2016 21:01:20 +0000 (21:01 +0000)]
GlobalISel: legalize conditional branches on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279565
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Matthias Braun [Tue, 23 Aug 2016 20:58:29 +0000 (20:58 +0000)]
CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
Re-apply this commit with the deletion of a MachineFunction delegated to
a separate pass to avoid use after free when doing this directly in
AsmPrinter.
This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.
This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.
Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.
Differential Revision: http://reviews.llvm.org/D23736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279564
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David Majnemer [Tue, 23 Aug 2016 20:52:00 +0000 (20:52 +0000)]
[ValueTracking] Use a function_ref to avoid multiple instantiations
No functional change intended, this should just be a code size
improvement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279563
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Matthew Simpson [Tue, 23 Aug 2016 20:48:50 +0000 (20:48 +0000)]
[SLP] Avoid signed integer overflow
The test case included with r279125 exposed an existing signed integer
overflow. Since getTreeCost can return INT_MAX, we can't sum this cost together
with other costs, such as getReductionCost.
This patch removes the possibility of assigning a cost of INT_MAX. Since we
were previously using INT_MAX as an indicator for "should not vectorize", we
now explicitly check this condition with "isTreeTinyAndNotFullyVectorizable"
before computing a cost.
This patch adds a run-line to the test case used for r279125 that ensures we
don't vectorize. Previously, this line would vectorize the test case by chance
due to undefined behavior in the cost calculation.
Differential Revision: https://reviews.llvm.org/D23723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279562
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Zachary Turner [Tue, 23 Aug 2016 20:08:02 +0000 (20:08 +0000)]
Remove unused translation unit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279561
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Zachary Turner [Tue, 23 Aug 2016 20:07:32 +0000 (20:07 +0000)]
Update coding standards for include style.
Reviewed By: lattner
Differential Revision: https://reviews.llvm.org/D23591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279560
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Mehdi Amini [Tue, 23 Aug 2016 19:32:41 +0000 (19:32 +0000)]
[LTO] Fix test following r279550
The output name changed, but it was passing locally
using the old output still present in the build dir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279556
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Tim Northover [Tue, 23 Aug 2016 19:30:42 +0000 (19:30 +0000)]
GlobalISel: extend legalizer interface to handle multiple types.
Instructions like G_ICMP have multiple types that may need to be legalized (the
boolean output and nearly arbitrary inputs in this case). So the legalizer must
be capable of deciding what to do for each of them separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279554
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Tim Northover [Tue, 23 Aug 2016 19:30:38 +0000 (19:30 +0000)]
GlobalISel: mark pointer casts legal on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279553
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Mehdi Amini [Tue, 23 Aug 2016 18:39:15 +0000 (18:39 +0000)]
[ThinLTO] Add a llvm-lto2 test to check that ODR type uniquing is enabled (NFC)
This adds a test for r279532, thanks David Li for noticing :)
Recommit r279545 after committing first a dependent patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279551
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Mehdi Amini [Tue, 23 Aug 2016 18:39:12 +0000 (18:39 +0000)]
Stop always creating and running an LTO compilation if there is not a single LTO object
Summary:
I assume there was a use case, so maybe this strawman patch will help
clarifying if it is legit.
In any case the current situation is not legit: a ThinLTO compilation
should not trigger an unexpected full LTO compilation.
Right now, adding a --save-temps option triggers this and makes the
number of output differs.
Reviewers: tejohnson
Subscribers: pcc, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D23600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279550
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Mehdi Amini [Tue, 23 Aug 2016 18:25:59 +0000 (18:25 +0000)]
Revert "[ThinLTO] Add a llvm-lto2 test to check that ODR type uniquing is enabled (NFC)"
This reverts commit r279545, test is failing, my Output dir was dirty and making the test pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279549
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Tim Northover [Tue, 23 Aug 2016 18:20:09 +0000 (18:20 +0000)]
GlobalISel: legalize 1-bit load/store and mark 8/16 bit variants legal on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279548
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Mehdi Amini [Tue, 23 Aug 2016 18:12:55 +0000 (18:12 +0000)]
[ThinLTO] Add a llvm-lto2 test to check that ODR type uniquing is enabled (NFC)
This adds a test for r279532, thanks David Li for noticing :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279545
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Peter Zotov [Tue, 23 Aug 2016 18:07:16 +0000 (18:07 +0000)]
[CMake] [OCaml] Add -DLLVM_ENABLE_OCAMLDOC switch
Patch by Michael Gorny.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279544
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Sanjay Patel [Tue, 23 Aug 2016 18:00:51 +0000 (18:00 +0000)]
[InstSimplify] allow icmp with constant folds for splat vectors, part 2
Completes the m_APInt changes for simplifyICmpWithConstant().
Other commits in this series:
https://reviews.llvm.org/rL279492
https://reviews.llvm.org/rL279530
https://reviews.llvm.org/rL279534
https://reviews.llvm.org/rL279538
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279543
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Xinliang David Li [Tue, 23 Aug 2016 18:00:41 +0000 (18:00 +0000)]
Possible fix of test failures on win bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279542
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Sanjay Patel [Tue, 23 Aug 2016 17:30:56 +0000 (17:30 +0000)]
[InstSimplify] allow icmp with constant folds for splat vectors, part 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279538
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Justin Lebar [Tue, 23 Aug 2016 17:18:11 +0000 (17:18 +0000)]
[SelectionDAG] Use a union of bitfield structs for SDNode::SubclassData.
Summary:
This greatly simplifies our handling of SDNode::SubclassData.
NFC, hopefully. :)
See discussion in D23035 for discussion about the design API of these
bitfields.
Reviewers: chandlerc
Subscribers: llvm-commits, rnk
Differential Revision: https://reviews.llvm.org/D23036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279537
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Justin Lebar [Tue, 23 Aug 2016 17:18:07 +0000 (17:18 +0000)]
[CodeGen] Convert a loop to a for-each loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279536
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