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Fangrui Song [Thu, 11 Jul 2019 10:17:59 +0000 (10:17 +0000)]
[llvm-objcopy] Don't change permissions of non-regular output files
There is currently an EPERM error when a regular user executes `llvm-objcopy a.o /dev/null`.
Worse, root can even change the mode bits of /dev/null.
Fix it by checking if the output file is special.
A new overload of llvm::sys::fs::setPermissions with FD as the parameter
is added. Users should provide `perm & ~umask` as the parameter if they
intend to respect umask.
The existing overload of llvm::sys::fs::setPermissions may be deleted if
we can find an implementation of fchmod() on Windows. fchmod() is
usually better than chmod() because it saves syscalls and can avoid race
condition.
Reviewed By: jakehehrlich, jhenderson
Differential Revision: https://reviews.llvm.org/D64236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365753
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Fangrui Song [Thu, 11 Jul 2019 10:10:09 +0000 (10:10 +0000)]
[X86] -fno-plt: use GOT __tls_get_addr only if GOTPCRELX is enabled
Summary:
As of binutils 2.32, ld has a bogus TLS relaxation error when the GD/LD
code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is
attempted to be relaxed to IE/LE (binutils PR24784). gold and lld are good.
In gcc/config/i386/i386.md, there is a configure-time check of as/ld
support and the GOT relaxation will not be used if as/ld doesn't support
it:
if (flag_plt || !HAVE_AS_IX86_TLS_GET_ADDR_GOT)
return "call\t%P2";
return "call\t{*%p2@GOT(%1)|[DWORD PTR %p2@GOT[%1]]}";
In clang, -DENABLE_X86_RELAX_RELOCATIONS=OFF is the default. The ld.bfd
bogus error can be reproduced with:
thread_local int a;
int main() { return a; }
clang -fno-plt -fpic a.cc -fuse-ld=bfd
GOTPCRELX gained relative good support in 2016, which is considered
relatively new. It is even difficult to conditionally default to
-DENABLE_X86_RELAX_RELOCATIONS=ON due to cross compilation reasons. So
work around the ld.bfd bug by only using GOT when GOTPCRELX is enabled.
Reviewers: dalias, hjl.tools, nikic, rnk
Reviewed By: nikic
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365752
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Florian Hahn [Thu, 11 Jul 2019 09:57:00 +0000 (09:57 +0000)]
[BitcodeReader] Validate OpNum, before accessing Record array.
Currently invalid bitcode files can cause a crash, when OpNum exceeds
the number of elements in Record, like in the attached bitcode file.
The test case was generated by clusterfuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15698
Reviewers: t.p.northover, thegameg, jfb
Reviewed By: jfb
Differential Revision: https://reviews.llvm.org/D64507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365750
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Sam Parker [Thu, 11 Jul 2019 09:56:15 +0000 (09:56 +0000)]
[ARM][LowOverheadLoops] Correct offset checking
This patch addresses a couple of problems:
1) The maximum supported offset of LE is -4094.
2) The offset of WLS also needs to be checked, this uses a
maximum positive offset of 4094.
The use of BasicBlockUtils has been changed because the block offsets
weren't being initialised, but the isBBInRange checks both positive
and negative offsets.
ARMISelLowering has been tweaked because the test case presented
another pattern that we weren't supporting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365749
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Simon Tatham [Thu, 11 Jul 2019 09:52:15 +0000 (09:52 +0000)]
[ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.
The VQDMLAH.U8, VQDMLAH.U16 and VQDMLAH.U32 instructions don't
actually exist: the Armv8.1-M architecture spec only lists signed
forms of that instruction. The unsigned ones were added in error: they
existed in an early draft of the spec, but they were removed before
the public version, and we missed that particular spec change.
Also affects the variant forms VQDMLASH, VQRDMLAH and VQRDMLASH.
Reviewers: miyuki
Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365747
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Kai Luo [Thu, 11 Jul 2019 09:43:03 +0000 (09:43 +0000)]
[NFC][PowerPC] Added test to track current behaviour of TailDup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365746
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Petar Avramovic [Thu, 11 Jul 2019 09:28:34 +0000 (09:28 +0000)]
[MIPS GlobalISel] Skip copies in addUseDef and addDefUses
Skip copies between virtual registers during search for UseDefs
and DefUses.
Since each operand has one def search for UseDefs is straightforward.
But since operand can have many uses, we have to check all uses of
each copy we traverse during search for DefUses.
Differential Revision: https://reviews.llvm.org/D64486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365744
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Petar Avramovic [Thu, 11 Jul 2019 09:22:49 +0000 (09:22 +0000)]
[MIPS GlobalISel] RegBankSelect for chains of ambiguous instructions
When one of the uses/defs of ambiguous instruction is also ambiguous
visit it recursively and search its uses/defs for instruction with
only one mapping available.
When all instruction in a chain are ambiguous arbitrary mapping can
be selected. For s64 operands in ambiguous chain fprb is selected since
it results in less instructions then having to narrow scalar s64 to s32.
For s32 both gprb and fprb result in same number of instructions and
gprb is selected like a general purpose option.
At the moment we always avoid cross register bank copies.
TODO: Implement a model for costs calculations of different mappings
on same instruction and cross bank copies. Allow cross bank copies
when appropriate according to cost model.
Differential Revision: https://reviews.llvm.org/D64485
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365743
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Haojian Wu [Thu, 11 Jul 2019 08:54:28 +0000 (08:54 +0000)]
Revert Recommit "[CommandLine] Remove OptionCategory and SubCommand caches from the Option class."
This reverts r365675 (git commit
43d75f977853c3ec891a440c362b2df183a211b5)
The patch causes a crash in SupportTests (CommandLineTest.AliasesWithArguments).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365742
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Jay Foad [Thu, 11 Jul 2019 08:49:52 +0000 (08:49 +0000)]
Remove some redundant code from r290372 and improve a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365741
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Sam Parker [Thu, 11 Jul 2019 07:47:50 +0000 (07:47 +0000)]
[ARM][ParallelDSP] Change the search for smlads
Two functional changes have been made here:
- Now search up from any add instruction to find the chains of
operations that we may turn into a smlad. This allows the
generation of a smlad which doesn't accumulate into a phi.
- The search function has been corrected to stop it falsely searching
up through an invalid path.
The bulk of the changes have been making the Reduction struct a class
and making it more C++y with getters and setters.
Differential Revision: https://reviews.llvm.org/D61780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365740
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Mikael Holmen [Thu, 11 Jul 2019 07:07:23 +0000 (07:07 +0000)]
[test] Silence gcc 7.4 warning [NFC]
Without this gcc 7.4.0 complains with
../unittests/Analysis/ValueTrackingTest.cpp:937:66: error: ISO C++11 requires at least one argument for the "..." in a variadic macro [-Werror]
::testing::ValuesIn(IsBytewiseValueTests));
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365738
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Heejin Ahn [Thu, 11 Jul 2019 05:55:47 +0000 (05:55 +0000)]
[WebAssembly] Print error message for llvm.clear_cache intrinsic
Summary:
Wasm does not currently support `llvm.clear_cache` intrinsic, and this
prints a proper error message instead of segfault.
Reviewers: dschuff, sbc100, sunfish
Subscribers: jgravelle-google, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365731
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Huihui Zhang [Thu, 11 Jul 2019 04:56:37 +0000 (04:56 +0000)]
[InstCombine][NFCI] Add test coverage to onehot_merge.ll
Prep work for upcoming patch D64275.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365729
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Chen Zheng [Thu, 11 Jul 2019 02:18:22 +0000 (02:18 +0000)]
[SCEV] teach SCEV symbolical execution about overflow intrinsics folding.
Differential Revision: https://reviews.llvm.org/D64422
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365726
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Johannes Doerfert [Thu, 11 Jul 2019 01:14:48 +0000 (01:14 +0000)]
Replace three "strip & accumulate" implementations with a single one
This patch replaces the three almost identical "strip & accumulate"
implementations for constant pointer offsets with a single one,
combining the respective functionalities. The old interfaces are kept
for now.
Differential Revision: https://reviews.llvm.org/D64468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365723
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Johannes Doerfert [Thu, 11 Jul 2019 01:14:30 +0000 (01:14 +0000)]
[NFC] Adjust "invalid.ll.bc" tests to check for AttrKind #255 not #63
We are about to add enum attributes with AttrKind numbers >= 63. This
means we cannot use AttrKind #63 to test for an invalid attribute number
in the RAW format anymore. This patch changes the number of an invalid
attribute to #255. There is no change to the character of the tests.
Differential Revision: https://reviews.llvm.org/D64531
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365722
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Craig Topper [Thu, 11 Jul 2019 01:01:39 +0000 (01:01 +0000)]
[X86] Don't convert 8 or 16 bit ADDs to LEAs on Atom in FixupLEAPass.
We use the functions that convert to three address to do the
conversion, but changing an 8 or 16 bit will cause it to create
a virtual register. This can't be done after register allocation
where this pass runs.
I've switched the pass completely to a white list of instructions
that can be converted to LEA instead of a blacklist that was
incorrect. This will avoid surprises if we enhance the three
address conversion function to include additional instructions
in the future.
Fixes PR42565.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365720
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Stanislav Mekhanoshin [Thu, 11 Jul 2019 00:10:17 +0000 (00:10 +0000)]
[AMDGPU] gfx908 atomic fadd and atomic pk_fadd
Differential Revision: https://reviews.llvm.org/D64435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365717
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Stanislav Mekhanoshin [Thu, 11 Jul 2019 00:00:27 +0000 (00:00 +0000)]
[AMDGPU] gfx908 dot instruction support
Differential Revision: https://reviews.llvm.org/D64431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365715
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Jordan Rupprecht [Wed, 10 Jul 2019 23:32:44 +0000 (23:32 +0000)]
Revert [llvm-objcopy] Allow strip symtab from executables and DSOs
This reverts r365193 (git commit
194f16b3548bcb23a7f0fd638778ed72edd18d37)
This patch doesn't work with binaries built w/ `--emit-relocs`, e.g.
```
$ echo 'int main() { return 0; }' | clang -Wl,--emit-relocs -x c - -o foo && llvm-objcopy --strip-unneeded foo
llvm-objcopy: error: 'foo': not stripping symbol '__gmon_start__' because it is named in a relocation
```
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365712
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Sanjay Patel [Wed, 10 Jul 2019 23:23:54 +0000 (23:23 +0000)]
[SDAG] commute setcc operands to match a subtract
If we have:
R = sub X, Y
P = cmp Y, X
...then flipping the operands in the compare instruction can allow using a subtract that sets compare flags.
Motivated by diffs in D58875 - not sure if this changes anything there,
but this seems like a good thing independent of that.
There's a more involved version of this transform already in IR (in instcombine
although that seems misplaced to me) - see "swapMayExposeCSEOpportunities()".
Differential Revision: https://reviews.llvm.org/D63958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365711
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Vitaly Buka [Wed, 10 Jul 2019 22:56:15 +0000 (22:56 +0000)]
Add IsBytewiseValue unit test
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365710
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Vitaly Buka [Wed, 10 Jul 2019 22:53:52 +0000 (22:53 +0000)]
NFC: Pass DataLayout into isBytewiseValue
Summary:
We will need to handle IntToPtr which I will submit in a separate patch as it's
not going to be NFC.
Reviewers: eugenis, pcc
Reviewed By: eugenis
Subscribers: hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D63940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365709
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Craig Topper [Wed, 10 Jul 2019 22:44:32 +0000 (22:44 +0000)]
[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions.
Fixes similar issues to r352306.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365705
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Craig Topper [Wed, 10 Jul 2019 22:44:24 +0000 (22:44 +0000)]
[X86] Add a few more TBM and BLSI test cases that show the same issue that r352306 fixed for BLSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365704
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Craig Topper [Wed, 10 Jul 2019 22:14:39 +0000 (22:14 +0000)]
[X86] Add BLSR and BLSMSK to isUseDefConvertible.
Unfortunately subo formation in CGP prevents obvious ways of
testing this.
But we already have BLSI in here and the flag behavior is
well understood.
Might become more useful if we improve PR42571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365702
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David Tenty [Wed, 10 Jul 2019 22:13:55 +0000 (22:13 +0000)]
[NFC]Fix IR/MC depency issue for function descriptor SDAG implementation
Summary: llvm/IR/GlobalValue.h can't be included in MC, that creates a circular dependency between MC and IR libraries. This circular dependency is causing an issue for build system that enforce layering.
Author: Xiangling_L
Reviewers: sfertile, jasonliu, hubert.reinterpretcast, gribozavr
Reviewed By: gribozavr
Subscribers: wuzish, nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365701
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Craig Topper [Wed, 10 Jul 2019 21:01:34 +0000 (21:01 +0000)]
[X86] Remove unused variable. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365697
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Roman Lebedev [Wed, 10 Jul 2019 19:58:13 +0000 (19:58 +0000)]
[NFC][InstCombine] Comb through just-added "omit mask before left-shift" tests once more
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365694
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Nico Weber [Wed, 10 Jul 2019 19:31:25 +0000 (19:31 +0000)]
Add support for building with Python 3
LLDB supports Python 3 now.
Differential Revision: https://reviews.llvm.org/D64443
Patch from Christian Biesinger <cbiesinger@google.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365692
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Amara Emerson [Wed, 10 Jul 2019 19:21:43 +0000 (19:21 +0000)]
[AArch64][GlobalISel] Optimize compare and branch cases with G_INTTOPTR and unknown values.
Since we have distinct types for pointers and scalars, G_INTTOPTRs can sometimes
obstruct attempts to find constant source values. These usually come about when
try to do some kind of null pointer check. Teaching getConstantVRegValWithLookThrough
about this operation allows the CBZ/CBNZ optimization to catch more cases.
This change also improves the case where we can't find a constant source at all.
Previously we would emit a cmp, cset and tbnz for that. Now we try to just emit
a cmp and conditional branch, saving an instruction.
The cumulative code size improvement of this change plus D64354 is 5.5% geomean
on arm64 CTMark -O0.
Differential Revision: https://reviews.llvm.org/D64377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365690
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Nico Weber [Wed, 10 Jul 2019 19:20:17 +0000 (19:20 +0000)]
gn build: Merge r365687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365689
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Nikola Prica [Wed, 10 Jul 2019 18:58:05 +0000 (18:58 +0000)]
Revert "[ELF] Loose a condition for relocation with a symbol"
This reverts commit
8507eca1647118e73435b0ce1de8a1952a021d01.
Reveting due to some suspicious failurse in santizer-x86_64-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365685
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Jessica Paquette [Wed, 10 Jul 2019 18:46:56 +0000 (18:46 +0000)]
[GlobalISel][AArch64] Use getOpcodeDef instead of findMIFromReg
Some minor cleanup.
This function in Utils does the same thing as `findMIFromReg`. It also looks
through copies, which `findMIFromReg` didn't.
Delete `findMIFromReg` and use `getOpcodeDef` instead. This only happens in
`tryOptVectorDup` right now.
Update opt-shuffle-splat to show that we can look through the copies now, too.
Differential Revision: https://reviews.llvm.org/D64520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365684
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Jessica Paquette [Wed, 10 Jul 2019 18:44:57 +0000 (18:44 +0000)]
[GlobalISel][AArch64][NFC] Use getDefIgnoringCopies from Utils where we can
There are a few places where we walk over copies throughout
AArch64InstructionSelector.cpp. In Utils, there's a function that does exactly
this which we can use instead.
Note that the utility function works with the case where we run into a COPY
from a physical register. We've run into bugs with this a couple times, so using
it should defend us from similar future bugs.
Also update opt-fold-compare.mir to show that we still handle physical registers
properly.
Differential Revision: https://reviews.llvm.org/D64513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365683
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David Greene [Wed, 10 Jul 2019 18:25:58 +0000 (18:25 +0000)]
Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"
This broke some PPC prefetching tests.
This reverts commit
9fdfb045ae8bb643ab0d0455dcf9ecaea3b1eb3c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365680
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Michael Berg [Wed, 10 Jul 2019 18:23:26 +0000 (18:23 +0000)]
Move three folds for FADD, FSUB and FMUL in the DAG combiner away from Unsafe to more aligned checks that reflect context
Summary: Unsafe does not map well alone for each of these three cases as it is missing NoNan context when accessed directly with clang. I have migrated the fold guards to reflect the expectations of handing nan and zero contexts directly (NoNan, NSZ) and some tests with it. Unsafe does include NSZ, however there is already precedent for using the target option directly to reflect that context.
Reviewers: spatel, wristow, hfinkel, craig.topper, arsenm
Reviewed By: arsenm
Subscribers: michele.scandale, wdng, javed.absar
Differential Revision: https://reviews.llvm.org/D64450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365679
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David Greene [Wed, 10 Jul 2019 18:07:01 +0000 (18:07 +0000)]
[System Model] [TTI] Update cache and prefetch TTI interfaces
Rework the TTI cache and software prefetching APIs to prepare for the
introduction of a general system model. Changes include:
- Marking existing interfaces const and/or override as appropriate
- Adding comments
- Adding BasicTTIImpl interfaces that delegate to a subtarget
implementation
- Adding a default "no information" subtarget implementation
Only a handful of targets use these interfaces currently: AArch64,
Hexagon, PPC and SystemZ. AArch64 already has a custom subtarget
implementation, so its custom TTI implementation is migrated to use
the new facilities in BasicTTIImpl to invoke its custom subtarget
implementation. The custom TTI implementations continue to exist for
the other targets with this change. They are not moved over to
subtarget-based implementations.
The end goal is to have the default subtarget implementation defer to
the system model defined by the target. With this change, the default
subtarget implementation essentially returns "no information" for
these interfaces. None of the existing users of TTI will hit that
implementation because they define their own custom TTI
implementations and won't use the BasicTTIImpl implementations.
Once system models are in place for the targets that use these
interfaces, their custom TTI implementations can be removed.
Differential Revision: https://reviews.llvm.org/D63614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365676
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Don Hinton [Wed, 10 Jul 2019 17:57:05 +0000 (17:57 +0000)]
Recommit "[CommandLine] Remove OptionCategory and SubCommand caches from the Option class."
Previously reverted in 364141 due to buildbot breakage, and fixed here
by making GeneralCategory global a ManagedStatic.
Summary:
This change processes `OptionCategory`s and `SubCommand`s as they
are seen instead of caching them in the Option class and processing
them later. Doing so simplifies the work needed to be done by the Global
parser and significantly reduces the size of the Option class to a mere 64
bytes.
Removing the `OptionCategory` cache saved 24 bytes, and removing
the `SubCommand` cache saved an additional 48 bytes, for a total of a
72 byte reduction.
Reviewed By: serge-sans-paille
Tags: #llvm, #clang
Differential Revision: https://reviews.llvm.org/D62105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365675
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Simon Pilgrim [Wed, 10 Jul 2019 17:49:27 +0000 (17:49 +0000)]
[X86] EltsFromConsecutiveLoads - clean up element size calcs. NFCI.
Determine the element/load size calculations earlier and assert that they are whole bytes in size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365674
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Alina Sbirlea [Wed, 10 Jul 2019 17:36:56 +0000 (17:36 +0000)]
[LoopRotate + MemorySSA] Keep an <instruction-cloned instruction> map.
Summary:
The map kept in loop rotate is used for instruction remapping, in order
to simplify the clones of instructions. Thus, if an instruction can be
simplified, its simplified value is placed in the map, even when the
clone is added to the IR. MemorySSA in contrast needs to know about that
clone, so it can add an access for it.
To resolve this: keep a different map for MemorySSA.
Reviewers: george.burgess.iv
Subscribers: jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365672
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Lang Hames [Wed, 10 Jul 2019 17:24:24 +0000 (17:24 +0000)]
[ORC] Add custom IR compiler configuration to LLJITBuilder to enable obj caches.
LLJITBuilder now has a setCompileFunctionCreator method which can be used to
construct a CompileFunction for the LLJIT instance being created. The motivating
use-case for this is supporting ObjectCaches, which can now be set up at
compile-function construction time. To demonstrate this an example project,
LLJITWithObjectCache, is included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365671
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Simon Pilgrim [Wed, 10 Jul 2019 17:22:31 +0000 (17:22 +0000)]
[X86] Regenerate tests. NFCI.
Hasn't been regenerated since the update script could merge 32/64-bit checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365670
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Craig Topper [Wed, 10 Jul 2019 17:11:18 +0000 (17:11 +0000)]
[X86] Add tests for an alternative sequence for _mm_storel_pi/_mm_storeh_pi intrinsics. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365667
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Nick Desaulniers [Wed, 10 Jul 2019 17:08:25 +0000 (17:08 +0000)]
[TargetLowering] support BlockAddress as "i" inline asm constraint
Summary:
This allows passing address of labels to inline assembly "i" input
constraints.
Fixes pr/42502.
Reviewers: ostannard
Reviewed By: ostannard
Subscribers: void, echristo, nathanchance, ostannard, javed.absar, hiraditya, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365664
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Roman Lebedev [Wed, 10 Jul 2019 16:54:13 +0000 (16:54 +0000)]
[NFC][InstCombine] Fixup some tests in just-added "omit mask before left-shift" tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365663
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Peter Collingbourne [Wed, 10 Jul 2019 16:36:46 +0000 (16:36 +0000)]
MC: AArch64: Add support for pg_hi21_nc relocation specifier.
Differential Revision: https://reviews.llvm.org/D64455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365661
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Vedant Kumar [Wed, 10 Jul 2019 16:32:20 +0000 (16:32 +0000)]
[CodeExtractor] Fix sinking of allocas with multiple bitcast uses (PR42451)
An alloca which can be sunk into the extraction region may have more
than one bitcast use. Move these uses along with the alloca to prevent
use-before-def.
Testing: check-llvm, stage2 build of clang
Fixes llvm.org/PR42451.
Differential Revision: https://reviews.llvm.org/D64463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365660
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Vedant Kumar [Wed, 10 Jul 2019 16:32:16 +0000 (16:32 +0000)]
[CodeExtractor] Simplify findAllocas, NFC
Split getLifetimeMarkers out into its own method and have it return a
struct.
Differential Revision: https://reviews.llvm.org/D64467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365659
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Matt Arsenault [Wed, 10 Jul 2019 16:31:19 +0000 (16:31 +0000)]
GlobalISel: Legalization for G_FMINNUM/G_FMAXNUM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365658
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Matt Arsenault [Wed, 10 Jul 2019 16:31:15 +0000 (16:31 +0000)]
GlobalISel: Define the full family of FP min/max instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365657
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Simon Pilgrim [Wed, 10 Jul 2019 16:22:31 +0000 (16:22 +0000)]
[X86] EltsFromConsecutiveLoads - remove duplicate check for element size. NFCI.
We've already checked that each element is the correct contributory size for VT when we inspect the elements for Undef/Zero/Load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365656
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Simon Pilgrim [Wed, 10 Jul 2019 16:14:26 +0000 (16:14 +0000)]
[X86] EltsFromConsecutiveLoads - ensure element reg/store sizes are the same size. NFCI.
This renames the type so it doesn't sound like its based off the load size - as we're moving towards supporting combining loads of different sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365655
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Matt Arsenault [Wed, 10 Jul 2019 16:09:26 +0000 (16:09 +0000)]
AMDGPU: Serialize mode from MachineFunctionInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365653
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Roman Lebedev [Wed, 10 Jul 2019 16:07:35 +0000 (16:07 +0000)]
[PatternMatch] Generalize m_SpecificInt_ULT() to take ICmpInst::Predicate
As discussed in the original review, this may be useful,
so let's just do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365652
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Francis Visoiu Mistrih [Wed, 10 Jul 2019 15:46:36 +0000 (15:46 +0000)]
[Remarks] Add cl::Hidden to -remarks-yaml-string-table
It was showing up in a lot of unrelated tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365647
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Tom Stellard [Wed, 10 Jul 2019 15:39:37 +0000 (15:39 +0000)]
docs/GithubMove.rst: Remove obsolete information
Summary:
Remove references to the multirepo and update the document to
reflect the current state of the github repository.
Reviewers: mehdi_amini, jyknight
Subscribers: jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365645
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Thomas Preud'homme [Wed, 10 Jul 2019 15:31:19 +0000 (15:31 +0000)]
[FileCheck] Use bool operator to test Expected
Use bool() consistently to get boolean value of Error, Optional and
Expected types in EXPECT calls. While static_cast is used in all cases
but one, bool provides more clarity and makes more sense as a new
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365644
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Roman Lebedev [Wed, 10 Jul 2019 15:08:06 +0000 (15:08 +0000)]
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365641
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Jay Foad [Wed, 10 Jul 2019 14:53:47 +0000 (14:53 +0000)]
[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
Summary:
D59191 added support for these modifiers in the assembler and
disassembler. This patch just teaches instruction selection that it can
use them.
Reviewers: arsenm, tstellar
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365640
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David Bolvansky [Wed, 10 Jul 2019 14:43:27 +0000 (14:43 +0000)]
[InstCombine] pow(C,x) -> exp2(log2(C)*x)
Summary:
Transform
pow(C,x)
To
exp2(log2(C)*x)
if C > 0, C != inf, C != NaN (and C is not power of 2, since we have some fold for such case already).
log(C) is folded by the compiler and exp2 is much faster to compute than pow.
Reviewers: spatel, efriedma, evandro
Reviewed By: evandro
Subscribers: lebedev.ri, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64099
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365637
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Sanjay Patel [Wed, 10 Jul 2019 14:41:47 +0000 (14:41 +0000)]
[InferFunctionAttrs] add/adjust tests for dereferenceable; NFC
Based on review comments for D64258.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365636
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Nico Weber [Wed, 10 Jul 2019 14:05:13 +0000 (14:05 +0000)]
gn build: Merge r365585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365633
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James Henderson [Wed, 10 Jul 2019 13:40:45 +0000 (13:40 +0000)]
[docs][llvm-symbolizer] Fix grammar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365630
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Simon Pilgrim [Wed, 10 Jul 2019 13:28:13 +0000 (13:28 +0000)]
[X86] EltsFromConsecutiveLoads - cleanup Zero/Undef/Load element collection. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365628
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Petar Avramovic [Wed, 10 Jul 2019 13:18:13 +0000 (13:18 +0000)]
[MIPS GlobalISel] Select float and double phi
Select float and double phi for MIPS32.
Differential Revision: https://reviews.llvm.org/D64420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365627
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Petar Avramovic [Wed, 10 Jul 2019 12:55:21 +0000 (12:55 +0000)]
[MIPS GlobalISel] Select float and double load and store
Select float and double load and store for MIPS32.
Differential Revision: https://reviews.llvm.org/D64419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365626
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Thomas Preud'homme [Wed, 10 Jul 2019 12:49:28 +0000 (12:49 +0000)]
[FileCheck] Simplify numeric variable interface
Summary:
This patch simplifies 2 aspects in the FileCheckNumericVariable code.
First, setValue() method is turned into a void function since being
called only on undefined variable is an invariant and is now asserted
rather than returned. This remove the assert from the callers.
Second, clearValue() method is also turned into a void function since
the only caller does not check its return value since it may be trying
to clear the value of variable that is already cleared without this
being noteworthy.
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64231
llvm-svn: 365249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365625
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Thomas Preud'homme [Wed, 10 Jul 2019 12:49:17 +0000 (12:49 +0000)]
[FileCheck] Fix @LINE value after match failure
Summary:
The value of the FileCheckNumericVariable class instance representing
the @LINE numeric variable is set and cleared respectively before and
after substitutions are made, if any. However, when a substitution
fails, the value is not cleared. This causes the next substitution of
@LINE later on to give the wrong value since setValue is a nop if the
value is already set. This is what caused failures after commit r365249.
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365624
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Sam Parker [Wed, 10 Jul 2019 12:29:43 +0000 (12:29 +0000)]
[NFC][ARM] Convert lambdas to static helpers
Break up and convert some of the lambdas in ARMLowOverheadLoops into
static functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365623
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Simon Pilgrim [Wed, 10 Jul 2019 12:22:59 +0000 (12:22 +0000)]
[X86] EltsFromConsecutiveLoads - LDBase is non-null. NFCI.
Don't bother checking for LDBase != null - it should be (and we assert that it is).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365622
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Simon Pilgrim [Wed, 10 Jul 2019 12:21:35 +0000 (12:21 +0000)]
[DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.
Keep the uint64_t type from getZExtValue() to stop truncation/extension overflow warnings in MSVC in subvector index math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365621
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Simon Pilgrim [Wed, 10 Jul 2019 11:26:57 +0000 (11:26 +0000)]
[X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.
Cache the LoadSDNode nodes so we can easily map to/from the element index instead of packing them together - this will be useful for future patches for PR16739 etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365620
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Nikola Prica [Wed, 10 Jul 2019 11:17:48 +0000 (11:17 +0000)]
[ELF] Loose a condition for relocation with a symbol
Deleted code was introduced as a work around for a bug in the gold linker
(http://sourceware.org/PR16794). Test case that was given as a reason for
this part of code, the one on previous link, now works for the gold.
This condition is too strict and when a code is compiled with debug info
it forces generation of numerous relocations with symbol for architectures
that do not have relocation addend.
Reviewers: arsenm, espindola
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D64327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365618
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Simon Pilgrim [Wed, 10 Jul 2019 10:46:36 +0000 (10:46 +0000)]
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support
This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it.
Another step towards partial vector loads......
Differential Revision: https://reviews.llvm.org/D64205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365614
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Simon Pilgrim [Wed, 10 Jul 2019 10:45:09 +0000 (10:45 +0000)]
Fix const/non-const lambda return type warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365613
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Simon Pilgrim [Wed, 10 Jul 2019 10:34:44 +0000 (10:34 +0000)]
Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365612
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Serguei Katkov [Wed, 10 Jul 2019 10:25:22 +0000 (10:25 +0000)]
[SimpleLoopUnswitch] Don't consider unswitching `switch` insructions with one unique successor
Only instructions with two or more unique successors should be considered for unswitching.
Patch Author: Daniil Suchkov.
Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365611
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Mikhail Maltsev [Wed, 10 Jul 2019 08:59:17 +0000 (08:59 +0000)]
[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.
Patch by Momchil Velikov.
Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen
Reviewed By: dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365604
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James Henderson [Wed, 10 Jul 2019 08:56:13 +0000 (08:56 +0000)]
[docs][llvm-dwarfdump] Normalise some wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365603
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George Rimar [Wed, 10 Jul 2019 08:40:11 +0000 (08:40 +0000)]
[test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries.
This converts 5 precompiled binaries to YAMLs,
removes 4 from inputs and performs a cleanup.
Differential revision: https://reviews.llvm.org/D64246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365601
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Serguei Katkov [Wed, 10 Jul 2019 08:25:48 +0000 (08:25 +0000)]
[SimpleLoopUnswitch] Add a test case exposing a bug
This test exposes a bug in SimpleLoopUnswitch that leads to a crash on
assert(SuccessorsCount > 1 && "Cannot unswitch a condition without multiple distinct successors!");
when SimpleLoopUnswitch considers unswitching of a loop by a switch with one successor.
Fix will be submitted soon.
Patch Author: Daniil Suchkov.
Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365600
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Mikael Holmen [Wed, 10 Jul 2019 06:18:03 +0000 (06:18 +0000)]
Silence gcc warning by adding parentheses to condition [NFC]
Without this gcc 7.4.0 complains with
../include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:457:54: error: suggest parentheses around '&&' within '||' [-Werror=parentheses]
isArtifactCast(TmpDef->getOpcode()) &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
"Expecting copy or artifact cast here");
~
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365597
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Kristina Brooks [Wed, 10 Jul 2019 03:52:31 +0000 (03:52 +0000)]
Fix modular build issues caused by BitCodes.h
Consolidate llvm::BWH_* statics into an enum to fix
module build issues. This fixes the LLVM_Bitcode module,
getting rid of -Wmodules-ambiguous-internal-linkage.
Differential Revision: https://reviews.llvm.org/D64469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365594
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Craig Topper [Wed, 10 Jul 2019 00:40:01 +0000 (00:40 +0000)]
[X86] Limit getTargetConstantFromNode to only work on NormalLoads not extending loads.
This seems to fix a failure reported by Jordan Rupprecht, but we
don't have a reduced test case yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365589
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Reid Kleckner [Wed, 10 Jul 2019 00:34:13 +0000 (00:34 +0000)]
[Support] Move llvm::MemoryBuffer to sys::fs::file_t
Summary:
On Windows, Posix integer file descriptors are a compatibility layer
over native file handles provided by the C runtime. There is a hard
limit on the maximum number of file descriptors that a process can open,
and the limit is 8192. LLD typically doesn't run into this limit because
it opens input files, maps them into memory, and then immediately closes
the file descriptor. This prevents it from running out of FDs.
For various reasons, I'd like to open handles to every input file and
keep them open during linking. That requires migrating MemoryBuffer over
to taking open native file handles instead of integer FDs.
Reviewers: aganea, Bigcheese
Reviewed By: aganea
Subscribers: smeenai, silvas, mehdi_amini, hiraditya, steven_wu, dexonsmith, dang, llvm-commits, zturner
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365588
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Tom Stellard [Wed, 10 Jul 2019 00:22:41 +0000 (00:22 +0000)]
AMDGPU/GlobalISel: Add support for wide loads >= 256-bits
Summary:
This adds support for the most commonly used wide load types:
<8xi32>, <16xi32>, <4xi64>, and <8xi64>
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57399
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365586
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Matt Arsenault [Tue, 9 Jul 2019 23:34:29 +0000 (23:34 +0000)]
GlobalISel: Implement lower for G_FCOPYSIGN
In SelectionDAG AMDGPU treated these as legal, but this was mostly
because the bitcasts required for FP types were painful. Theoretically
the bitpattern should eventually match to bfi, so don't bother trying
to get the patterns to import.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365583
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Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:20:01 +0000 (23:20 +0000)]
[Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.h
This fixes a modules issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365580
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Francis Visoiu Mistrih [Tue, 9 Jul 2019 23:16:59 +0000 (23:16 +0000)]
[docs][Remarks] Add documentation for remarks in LLVM
This adds documentation that describes remarks in LLVM.
It aims at explaining what remarks are, how to enable them, and what
users can do with the different modes.
It lists all the available flags in LLVM (excluding clang), and
describes the expected YAML structure as well as the tools that support
the YAML format today.
Differential Revision: https://reviews.llvm.org/D64355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365578
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Craig Topper [Tue, 9 Jul 2019 23:05:54 +0000 (23:05 +0000)]
[X86] Don't form extloads in combineExtInVec unless the load extension is legal.
This should prevent doing this on pre-sse4.1 targets or for 256
bit vectors without avx2.
I don't know of a failure from this. Op legalization will probably
take care of, but seemed better to be safe.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365577
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Matt Arsenault [Tue, 9 Jul 2019 22:48:04 +0000 (22:48 +0000)]
AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365575
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Stanislav Mekhanoshin [Tue, 9 Jul 2019 22:42:24 +0000 (22:42 +0000)]
[AMDGPU] gfx908 v_pk_fmac_f16 support
Differential Revision: https://reviews.llvm.org/D64433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365573
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:51 +0000 (22:37 +0000)]
gn build: Merge r365536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365572
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:41 +0000 (22:37 +0000)]
gn build: Merge r365532.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365571
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:25 +0000 (22:37 +0000)]
gn build: Merge r365541.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365570
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Peter Collingbourne [Tue, 9 Jul 2019 22:37:09 +0000 (22:37 +0000)]
gn build: Merge r365531.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365569
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Pavel Labath [Tue, 9 Jul 2019 22:36:43 +0000 (22:36 +0000)]
Add lldb type unit support to the release notes
Reviewers: JDevlieghere, teemperor
Subscribers: llvm-commits, lldb-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365568
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Matt Arsenault [Tue, 9 Jul 2019 22:19:13 +0000 (22:19 +0000)]
GlobalISel: Combine unmerge of merge with intermediate cast
This eliminates some illegal intermediate vectors when operations are
scalarized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365566
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