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Dmytro Laktyushkin [Fri, 19 Jul 2019 15:43:39 +0000 (11:43 -0400)]
drm/amd/display: update optc odm interface for more than 2 opps
Current optc odm interface only accepts 2 opps, we need to
expand this to allow 4 to 1 odm combine.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya Bakoulin [Wed, 17 Jul 2019 22:33:48 +0000 (18:33 -0400)]
drm/amd/display: Update DML parameters
[Why]
Need to add DML struct members that were omitted in previous
DML implemenations.
[How]
- Add missing enum values
- Add missing struct members
- Set new input values in the fetch functions
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julian Parkin [Mon, 15 Jul 2019 16:16:01 +0000 (12:16 -0400)]
drm/amd/display: Remove duplicate interface for programming FB
[Why]
There are currently two interfaces for exactly the same thing:
hupb_update_dchub in hupb and update_dchub in hubbub. The hubbub
version is currently unused past dcn10, largely because the call
from the dcn10 hardware sequencer does not call through the
interface, so the hupb interface was used instead. This is
confusing because of the duplicate code, the unused functions,
and the fact that more that one block currently owns this set
of registers.
[How]
Remove the hubp interface entirely, as well as the register
declarations that are not longer needed because of this. Change
the call site to always call the hubbub version through the
interface. Fix the update_dchub function in dcn20_hubbub.c to
program the correct registers for dcn20.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Mon, 22 Jul 2019 13:45:20 +0000 (09:45 -0400)]
drm/amd/display: fix pipe selection logic in validate
[why]
Resource mapping done in dcn20_validate_bandwidth has a flaw: When a full
update is performed, the HWSS will only update the MPCC tree for the stream
that is updated as opposed to all streams. This means that when mapping pipes
in validation, care must be taken to not change any existing mapping, otherwise it
leads to partial hw programming
[how]
it's not strictly necessary to track which stream/mpcc tree is being updated, but
rather it's sufficient to compare current and new state and just keep pipes that were
previously already mapped unchanged.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 19 Jul 2019 21:41:56 +0000 (17:41 -0400)]
drm/amd/display: 3.2.44
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Wed, 17 Jul 2019 23:02:14 +0000 (19:02 -0400)]
drm/amd/display: Set DSC before DIG front-end is connected to its back-end
[why]
At the time DIG FE is connected to its BE, the clocks in OTG are enabled and
PHY will also be set up. When DSC has to be used to fit the stream into the
available bandwidth, without DSC being set DIG could get exposed to the
higer bandwidth it (or link) could handle. This causes the HW to "reject"
video enable setup (the register shows that video enable was attempted, but
the status bit shows it as disabled).
[how]
- Separate DSC setup into DSC register config and DSC PPS SDP setup
- Move most of the DSC setup (register config) to before
dcn10_link_encoder_connect_dig_be_to_fe() is called
- Set up DSC PPS SDP after DIG FE is connected to its BE. This is because
setting DSC PPS SDP before that has no effect.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 18 Jul 2019 23:13:26 +0000 (19:13 -0400)]
drm/amd/display: Change DSC policy from slices per column to minimum slice height
[why] Minimum slice height is recommended by VESA DSC Spreadsheet user guide
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Thu, 18 Jul 2019 18:07:03 +0000 (13:07 -0500)]
drm/amd/display: Add HLG support in color module
[Why & How]
Support hlg OETF and EOTF based on BT.2100-2
Follow up is required.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Thu, 18 Jul 2019 14:02:40 +0000 (10:02 -0400)]
drm/amd/display: clean up DML for DCN2x
[why]
Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since
DMLv2 has gone through proper validation. v2 can now be used as the default and 1
level of fallback can be removed
[how]
remove previous workaround implemenation
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Wed, 17 Jul 2019 20:08:19 +0000 (16:08 -0400)]
drm/amd/display: enabling seamless boot sequence for dcn2
[Why]
Seamless boot (building SW state inheriting BIOS-initialized timing) was
enabled on DCN2, including fixes
[How]
Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/
Pixel clock.
This is part 2 of 2 for seamless boot NV10
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Sun, 28 Jul 2019 15:09:11 +0000 (11:09 -0400)]
drm/amd/display: fix dcn-specific clk_mgr init_clocks
[Why]
underflow seen on certain monitor setups caused by making dcnxx_init_hw
generic
[How]
by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr
init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr
memset in an else statement so both memsets don't get set
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Tue, 9 Jul 2019 19:15:17 +0000 (15:15 -0400)]
drm/amd/display: Make init_hw and init_pipes generic for seamless boot
[Why]
For seamless boot the init_hw sequence must be split into
actual hardware vs pipes, in order to defer pipe initialization to set mode
and skip of pipe-destructive sequences
[How]
made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit
deleted dcn20 specific versions. This is part 1 of a 2 partimplementation
of seamless boot
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 15 Jul 2019 14:34:30 +0000 (10:34 -0400)]
drm/amd/display: 3.2.43
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Tue, 16 Jul 2019 17:02:41 +0000 (13:02 -0400)]
drm/amd/display: wait for pending complete when enabling a plane
[why]
When planes are enabled, they must be enabled using VSYNC update (not immediate).
However, before the VUPDATE occurs, DM may call with an "immediate" flip which is address
only. This operation would normally be okay, but if the locking for immediate flip happens
to occur before the VUPDATE associated with the initial plane enablement, it will cause HW
to hang.
[how]
HWSS should enforce plane enable in HW to be synchronous with the call that enables the plane.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Su Sung Chung [Mon, 8 Jul 2019 15:31:39 +0000 (11:31 -0400)]
drm/amd/display: refactor gpio to allocate hw_container in constructor
[why]
if dynamic allocation fails during gpio_open, it will cause crash due to
page fault.
[how]
handle allocation when gpio object gets created and prevent from calling
gpio_open if allocation failed
Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jaehyun Chung [Mon, 15 Jul 2019 21:35:56 +0000 (17:35 -0400)]
drm/amd/display: Add work-around option to skip DCN20 clock updates
[Why] Auto Overclock Memory fails for some systems that don't support
p-state.
[How] Implement the workaround, and it's corresponding enable flag.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Mon, 15 Jul 2019 14:41:47 +0000 (10:41 -0400)]
drm/amd/display: fixup DPP programming sequence
[why]
DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not.
This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need
an increased divider will temporarily have actual DPP clock drop below minimum while DTO
double buffering takes effect. This results in temporary underflow.
[how]
To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the
ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase.
When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because
we do not use dividers larger than 1.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 12 Jul 2019 19:06:06 +0000 (15:06 -0400)]
drm/amd/display: make firmware info only load once during dc_bios create
Currently every time DC wants to access firmware info we make a call
into VBIOS. This makes no sense as there is nothing that can change
runtime inside fw info and can cause issues when calling unstable
bios during bringup.
This change eliminate this behavior by only calling bios once for fw
info and keeping it stored as part of dc_bios.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Mon, 24 Jun 2019 14:34:13 +0000 (10:34 -0400)]
drm/amd/display: Synchronous DisplayPort Link Training
[WHY]
We require a method to perform synchronous link training.
[HOW]
Sync LT is broken into 3 basic steps.
"Begin" starts the state machine, and resets "preferred" link settings.
"Attempt" will attempt to train the link with a given set of training
parameters.
"End" stops the state machine, and will optionally disable the link phy.
Between "Begin" and "End" DPCD:600h must not be set to "2"
(D3:Powered Down).
Between "Begin" and "End", there may be multiple "Attempts" with different
training parameters.
Signed-off-by: David Galiffi <david.galiffi@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julian Parkin [Fri, 12 Jul 2019 21:30:06 +0000 (17:30 -0400)]
drm/amd/display: Improve sharing of HUBBUB register lists
Add DCN20 common register list that contains registers shared
between DCN20 generations.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Wed, 10 Jul 2019 19:20:08 +0000 (14:20 -0500)]
drm/amd/display: Add 22, 24, and 26 degamma
[Why & How]
Support degamma ROM and RAM based on hardware capabilities.
Some refactoring into color module
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Gary Kattan <Gary.Kattan@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bayan Zabihiyan [Wed, 10 Jul 2019 20:00:53 +0000 (16:00 -0400)]
drm/amd/display: Fix frames_to_insert math
[Why]
The math on deciding on how many
"frames to insert" sometimes sent us over the max refresh rate.
Also integer overflow can occur if we have high refresh rates.
[How]
Instead of clipping the frame duration such that it doesn’t go below the min,
just remove a frame from the number of frames to insert. +
Use unsigned long long for intermediate calculations to prevent
integer overflow.
Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Fri, 12 Jul 2019 14:52:54 +0000 (10:52 -0400)]
drm/amd/display: fix issue where 252-255 values are clipped
[Why]
When endpoint is at the boundary of a region, such as at 2^0=1
we find that the last segment has a sharp slope and some points
are clipped at the top.
[How]
If end point is 1, which is exactly at the 2^0 region boundary, we
need to program an additional region beyond this point.
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Wed, 10 Jul 2019 22:35:18 +0000 (18:35 -0400)]
drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset
[why]
hdmi data scramble and tmds rate is not reset during pipe reset.
[how]
reset hdmi tmds rate and data scramble on pipe reset
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Wed, 10 Jul 2019 22:31:38 +0000 (18:31 -0400)]
drm/amd/display: reset drr programming on pipe reset
[why]
drr is still enabled after driver is unloaded causing black screen
[how]
disable drr during pipe reset.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Tue, 25 Jun 2019 23:08:50 +0000 (19:08 -0400)]
drm/amd/display: Add DFS reference clock field
Add to clk_mgr_internal struct, for future use.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Sat, 22 Jun 2019 22:52:41 +0000 (18:52 -0400)]
drm/amd/display: Add PIXEL_RATE control regs for more instances
For use by future ASICs
Signed-off-by: Sung Lee <sung.lee@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 9 Aug 2019 15:27:21 +0000 (17:27 +0200)]
drm/scheduler: use job count instead of peek
The spsc_queue_peek function is accessing queue->head which belongs to
the consumer thread and shouldn't be accessed by the producer
This is fixing a rare race condition when destroying entities.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Monk.liu@amd.com
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stephen Rothwell [Tue, 13 Aug 2019 08:10:38 +0000 (18:10 +1000)]
drm/amdgpu: MODULE_FIRMWARE requires linux/module.h
Fixes:
6a7a0bdbfa0c ("drm/amdgpu: add psp_v12_0 for renoir (v2)")
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Tue, 13 Aug 2019 10:33:40 +0000 (11:33 +0100)]
drm/amdgpu/powerplay: fix spelling mistake "unsuported" -> "unsupported"
There is a spelling mistake in a pr_err error message. Fix it. Also
add a space after a comma to clean up a checkpatch warning.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 13 Aug 2019 07:46:03 +0000 (15:46 +0800)]
drm/amdgpu: implement querying ras error count for mmhub
get mmhub ea ras error count by accessing EDC_CNT register
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 13 Aug 2019 08:52:04 +0000 (16:52 +0800)]
drm/amdgpu: use exiting amdgpu_ctx_total_num_entities function
simplify driver code.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 13 Aug 2019 08:48:28 +0000 (16:48 +0800)]
drm/amdgpu: fix typo error amdgput -> amdgpu
fix typo error:
change function name from "amdgput_ctx_total_num_entities" to
"amdgpu_ctx_total_num_entities".
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 13 Aug 2019 02:25:25 +0000 (10:25 +0800)]
drm/amd/powerplay: fix message of SetHardMinByFreq failed when feature is disabled
the direct send message to smc to set hard clokc will failed
when smc clock dpm feature is disabled.
so use function of smu_set_hard_freq_range to replace it.
the function will check feature enablement.
eg: when uclk (mclk) dpm feature is disabled on navi10
[ 300.675901] amdgpu: [powerplay] failed send message: SetHardMinByFreq(28)
param: 0x00020064 response 0xfffffffb
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Mon, 12 Aug 2019 02:23:04 +0000 (10:23 +0800)]
drm/amd/powerplay: add arcturus_is_dpm_running function for arcturus
add arcturus_is_dpm_running function
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Mon, 12 Aug 2019 02:06:34 +0000 (10:06 +0800)]
drm/amd/powerplay: remove redundancy debug log about smu unsupported features
remove redundancy debug log about smu unsupported features
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christoph Hellwig [Thu, 15 Aug 2019 07:27:03 +0000 (09:27 +0200)]
drm/amdgpu: simplify and cleanup setting the dma mask
Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks. Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christoph Hellwig [Thu, 15 Aug 2019 07:27:02 +0000 (09:27 +0200)]
drm/radeon: simplify and cleanup setting the dma mask
Use dma_set_mask_and_coherent to set both masks in one go, and remove
the no longer required fallback, as the kernel now always accepts
larger than required DMA masks. Fail the driver probe if we can't
set the DMA mask, as that means the system can only support a larger
mask.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christoph Hellwig [Thu, 15 Aug 2019 07:27:01 +0000 (09:27 +0200)]
drm/amdgpu: handle PCIe root ports with addressing limitations
amdgpu uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision. Unfortunately
PCIe root ports that have limited addressing exist as well. Use the
dma_addressing_limited instead to also take those into account.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christoph Hellwig [Thu, 15 Aug 2019 07:27:00 +0000 (09:27 +0200)]
drm/radeon: handle PCIe root ports with addressing limitations
radeon uses a need_dma32 flag to indicate to the drm core that some
allocations need to be done using GFP_DMA32, but it only checks the
device addressing capabilities to make that decision. Unfortunately
PCIe root ports that have limited addressing exist as well. Use the
dma_addressing_limited instead to also take those into account.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reported-by: Atish Patra <Atish.Patra@wdc.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 9 Aug 2019 15:38:32 +0000 (10:38 -0500)]
drm/amdgpu: flag renoir as experimental for now
The current code won't likely work on production hw when
it ships so leave it as experimental until it's ready.
Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 21 Jul 2019 14:27:50 +0000 (22:27 +0800)]
drm/amdgpu: skip mec2 jump table loading for renoir
Renoir need not load mec2 jump table with psp.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sun, 21 Jul 2019 12:58:31 +0000 (20:58 +0800)]
drm/amdgpu: use direct loading on renoir vcn for the moment
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use
direct loading for the moment till the issue is addressed.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Fri, 9 Aug 2019 15:46:36 +0000 (10:46 -0500)]
drm/amdgpu: set fw default loading by psp for renoir
By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 16 Jul 2019 09:36:43 +0000 (17:36 +0800)]
drm/amdgpu: update lbpw for renoir
enable gfx_v9_0_init_lbpw for renoir
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Tue, 16 Jul 2019 09:09:47 +0000 (17:09 +0800)]
drm/amdgpu: enable power gating for renoir
enable gfx power gating for renoir
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Mon, 12 Aug 2019 16:32:56 +0000 (11:32 -0500)]
drm/amdgpu: enable clock gating for renoir
enable gfx&common clock gating for renoir
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Jul 2019 13:21:57 +0000 (09:21 -0400)]
drm/amdgpu: add VCN2.0 to Renoir IP blocks
Thus enable VCN2.0 for Renoir
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Jul 2019 14:14:17 +0000 (10:14 -0400)]
drm/amdgpu: enable Doorbell support for Renoir (v2)
Add VCN range aperture to NBIO 7.0
v2: rebase (Alex)
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 15 Jul 2019 13:01:51 +0000 (09:01 -0400)]
drm/amdgpu: enable Renoir VCN firmware loading
By adding new Renoir VCN firmware
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 19:03:25 +0000 (14:03 -0500)]
drm/amdgpu: add sdma golden settings for renoir
This patch adds sdma golden settings for renoir asic.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Sat, 22 Jun 2019 18:51:57 +0000 (02:51 +0800)]
drm/amdgpu: add gfx golden settings for renoir (v2)
This patch adds gfx golden settings for renoir real asic.
v2: update settings (Alex)
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Fri, 9 Aug 2019 15:32:15 +0000 (10:32 -0500)]
drm/amdgpu: add psp_v12_0 for renoir (v2)
1. Add psp ip block
2. Use direct loading type by default and it can also config psp
loading type.
3. Bypass sos fw loading and xgmi&ras interface
v2: drop TA loading
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 24 Jul 2019 18:56:27 +0000 (13:56 -0500)]
drm/amdgpu: set rlc funcs for renoir
add gfx_v9_0_rlc_funcs for renoir
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Mon, 8 Apr 2019 05:14:28 +0000 (13:14 +0800)]
drm/amdgpu: add asic funcs for renoir
add asic funcs for renoir, init soc15_asic_funcs
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 24 Jul 2019 18:55:38 +0000 (13:55 -0500)]
drm/amdgpu: enable dce virtual ip module for Renoir
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Liu [Wed, 24 Jul 2019 18:53:17 +0000 (13:53 -0500)]
drm/amdgpu: fix no interrupt issue for renoir emu
In renoir's ih model, there's a change in mmIH_CHICKEN
register, that limits IH to use physical address directly.
Those chicken bits need to be programmed first.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 30 Oct 2018 03:43:02 +0000 (11:43 +0800)]
drm/amdgpu: add renoir pci id
Add Renoir PCI id support.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:50:22 +0000 (13:50 -0500)]
drm/amdgpu: set ip blocks for renoir
Enable ip blocks for renoir.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 8 Aug 2019 19:58:51 +0000 (14:58 -0500)]
drm/amdgpu: add sdma support for renoir
Add renoir checks to appropriate places.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:47:52 +0000 (13:47 -0500)]
drm/amdgpu: add gfx support for renoir
Add Renoir checks to gfx9 code.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:43:16 +0000 (13:43 -0500)]
drm/amdgpu: set fw load type for renoir
This patch sets fw load type as direct for renoir for the moment.
Will switch to psp when psp is ready.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:42:16 +0000 (13:42 -0500)]
drm/amdgpu: add gmc v9 supports for renoir
Add gfx memory controller support for renoir.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:39:36 +0000 (13:39 -0500)]
drm/amdgpu: add soc15 common ip block support for renoir
This patch adds common ip support for renoir.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:38:15 +0000 (13:38 -0500)]
drm/amdgpu: add renoir support for gpu_info and ip block setting
This patch adds renoir support for gpu_info firmware and ip block setting.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 24 Jul 2019 18:36:09 +0000 (13:36 -0500)]
drm/amdgpu: add renoir asic_type enum
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[].
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 25 Oct 2018 11:49:10 +0000 (19:49 +0800)]
drm/amdgpu: add renoir header files (v2)
This patch add all renoir header files.
v2: clean up headers (Alex)
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Mon, 5 Aug 2019 10:29:40 +0000 (11:29 +0100)]
drm/amd/powerplay: remove redundant duplicated return check
The check on ret is duplicated in two places, it is redundant code.
Remove it.
Addresses-Coverity: ("Logically dead code")
Fixes:
b94afb61cdae ("drm/amd/powerplay: honor hw limit on fetching metrics data for navi10")
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christophe JAILLET [Fri, 9 Aug 2019 20:12:19 +0000 (22:12 +0200)]
drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask
This should be 'dce_audio_mask', not 'dce_aduio_mask'.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 8 Aug 2019 05:29:23 +0000 (00:29 -0500)]
drm/amd/display: use kvmalloc for dc_state (v2)
It's large and doesn't need contiguous memory. Fixes
allocation failures in some cases.
v2: kvfree the memory.
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pierre-Eric Pelloux-Prayer [Tue, 6 Aug 2019 16:27:26 +0000 (18:27 +0200)]
drm/amdgpu: fix gfx9 soft recovery
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail.
v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 9 Aug 2019 07:44:22 +0000 (15:44 +0800)]
drm/amdgpu/powerplay: update Arcturus smu version in new place
Follow patch below:
drm/amd/powerplay: re-define smu interface version for smu v11
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 9 Aug 2019 10:58:42 +0000 (18:58 +0800)]
drm/amdgpu: enable mmhub clock gating for Arcturus
Init MC_MGCG/LS flag. Also apply to athub CG.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 9 Aug 2019 10:57:15 +0000 (18:57 +0800)]
drm/amdgpu: add mmhub clock gating for Arcturus
Add 2 mmhub instances CG
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 9 Aug 2019 07:13:38 +0000 (15:13 +0800)]
drm/amdgpu: increase CGCG gfx idle threshold for Arcturus
Follow the hw spec, and no need to consider gfxoff on Arcturus
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 9 Aug 2019 07:24:56 +0000 (15:24 +0800)]
drm/amdgpu: add GFX_CP_LS flag to Arcturus
Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
drm/amdgpu: enable gfx clock gating for Arcturus
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 9 Aug 2019 09:39:06 +0000 (17:39 +0800)]
drm/amdgpu: remove ras block's feature status info in sysfs
feature mask info is enough for rocm tool,
"cat /sys/class/drm/card0/device/ras/features" will get the
info like this:
feature mask: 0x3ffb
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Tue, 23 Jul 2019 04:16:25 +0000 (12:16 +0800)]
drm/amd/powerplay: change smu_read_sensor sequence in smu
change the smu_read_sensor sequence to:
asic specific sensor read -> smu v11 specific sensor read -> smu v11 common sensor read
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Thu, 8 Aug 2019 06:54:12 +0000 (14:54 +0800)]
drm/amdgpu: split athub clock gating from mmhub
Untie the bind of get/set athub CG state from mmhub, for cosmetic fix and Asic
not using mmhub 1.0. Besides, also fix wrong athub CG state in amdgpu_pm_info.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 07:48:44 +0000 (15:48 +0800)]
drm/amdgpu: enable sdma clock gating for Arcturus
Init sdma MGCG/LS flag
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 07:47:34 +0000 (15:47 +0800)]
drm/amdgpu: add sdma clock gating for Arcturus
Add ARCTURUS case in sdma set clockgating function
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 07:45:25 +0000 (15:45 +0800)]
drm/amdgpu: support sdma clock gating for more instances
Shorten the code with RREG32_SDMA/WREG32_SDMA macro in CG part.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 07:17:38 +0000 (15:17 +0800)]
drm/amdgpu: enable hdp clock gating for Arcturus
Init hdp MGCG/LS flag as Vega20
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 07:16:19 +0000 (15:16 +0800)]
drm/amdgpu: add hdp clock gating for Arcturus
Add hdp CGLS for Arcturus in set common clockgating function
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 06:52:38 +0000 (14:52 +0800)]
drm/amdgpu: enable gfx clock gating for Arcturus
Init gfx MGCG/LS and CGCG/LS flag.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 7 Aug 2019 06:59:07 +0000 (14:59 +0800)]
drm/amdgpu: add gfx clock gating for Arcturus
Add ARCTURUS case in gfx set clockgating function. No 3d clock on Arcturus.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 7 Aug 2019 04:21:22 +0000 (12:21 +0800)]
drm/amdgpu: create mmhub ras framework
enable mmhub ras feature and create sysfs/debugfs node for mmhub
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 6 Aug 2019 12:22:49 +0000 (20:22 +0800)]
drm/amdgpu: support mmhub ras in amdgpu ras
call mmhub ras query/inject in amdgpu ras
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 6 Aug 2019 12:15:55 +0000 (20:15 +0800)]
drm/amdgpu: add amdgpu_mmhub_funcs definition
add amdgpu_mmhub_funcs definition and initialize it,
prepare for mmhub ras enablement
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 7 Aug 2019 06:27:42 +0000 (14:27 +0800)]
drm/amdgpu: add sub block parameter in ras inject command
ras sub block index could be passed from shell command
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Thu, 8 Aug 2019 06:54:41 +0000 (14:54 +0800)]
drm/amdgpu: add check to avoid array bound issue
Sub_block_index can be passed from user level, so
add one check before accessing the array first to
prevent array index out of bound problem.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Thu, 8 Aug 2019 05:20:40 +0000 (13:20 +0800)]
drm/amd/powerplay: update smu11_driver_if_navi10.h
update the smu11_driver_if_navi10.h since navi14 smu fw
update to 53.12
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Thu, 8 Aug 2019 03:57:28 +0000 (11:57 +0800)]
drm/amd/powerplay: re-define smu interface version for smu v11
[why]
navi14 share same defination of smu interface version with navi10,
anyone of them update the version may break the other one's
version checking.
[how]
create different version defination, so that they can
update their version separately.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 7 Aug 2019 19:37:26 +0000 (14:37 -0500)]
drm/amdgpu: add navi14 PCI ID
Add the navi14 PCI device id.
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Wed, 24 Jul 2019 15:56:28 +0000 (17:56 +0200)]
drm/amdgpu: Update pitch on page flips without DC as well
DC already handles this correctly since amdgpu minor version 31. Bump
the minor version again so that xf86-video-amdgpu can take advantage of
this working without DC as well now.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Wed, 7 Aug 2019 14:25:48 +0000 (10:25 -0400)]
drm/amd/display: Remove drm_dsc_dc.c
This file was accidentally added to the driver during
Navi promotion
Nothing includes it. No makefile attempts to compile it, and
it would fail compilation if they tried
Remove it
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>w
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 1 Aug 2019 07:22:59 +0000 (15:22 +0800)]
drm/amdgpu: enable vcn clock gating for navi12
enables vcn medium grained clock gating
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 1 Aug 2019 07:19:10 +0000 (15:19 +0800)]
drm/amdgpu: enable athub clock gating for navi12
enables athub medium grained clock gating and memory light sleep
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 6 Aug 2019 05:42:03 +0000 (13:42 +0800)]
drm/amdgpu/athub2: set clock gating for navi12
add navi12 define
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 1 Aug 2019 07:01:23 +0000 (15:01 +0800)]
drm/amdgpu: enable ih clock gating for navi12
enables ih clock gating
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>