OSDN Git Service
Dmitry Venikov [Thu, 10 Jan 2019 15:33:35 +0000 (15:33 +0000)]
[llvm-symbolizer] Add -p as alias to -pretty-print
Summary: Provides -p as a short alias for -pretty-print. Motivation: https://bugs.llvm.org/show_bug.cgi?id=40076
Reviewers: samsonov, khemant, ruiu, rnk, fjricci, jhenderson
Reviewed By: jhenderson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350832
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Thu, 10 Jan 2019 15:33:17 +0000 (15:33 +0000)]
[RISCV][MC] Add support for evaluating constant symbols as immediates
This further improves compatibility with GNU as, allowing input such as the
following to be assembled:
.equ CONST, 0x123456
li a0, CONST
addi a0, a0, %lo(CONST)
.equ CONST, 1
slli a0, a0, CONST
Note that we don't have perfect compatibility with gas, as it will avoid
emitting a relocation in this case:
addi a0, a0, %lo(CONST2)
.equ CONST2, 0x123456
Thanks to Shiva Chen for suggesting a better way to approach this during review.
Differential Revision: https://reviews.llvm.org/D52298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350831
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 10 Jan 2019 15:27:23 +0000 (15:27 +0000)]
[x86] fix remaining miscompile bug in horizontal binop matching (PR40243)
When we use the partial-matching function on a 128-bit chunk, we must
account for the possibility that we've matched undef halves of the
original source vectors, so the outputs may need to be reset.
This should allow closing PR40243:
https://bugs.llvm.org/show_bug.cgi?id=40243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350830
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Thu, 10 Jan 2019 15:16:32 +0000 (15:16 +0000)]
gn build: Merge r350819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350829
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Thu, 10 Jan 2019 15:04:52 +0000 (15:04 +0000)]
[x86] fix horizontal binop matching for 256-bit vectors (PR40243)
This is a partial fix for:
https://bugs.llvm.org/show_bug.cgi?id=40243
...as seen in the integer test, we still need to correct the result when using the
existing (old) horizontal op matching function because it does not model the way
x86 256-bit horizontal ops return results (each 128-bit half is its own horizontal-op).
A potential follow-up change for that is discussed in the bug report - see also D56490.
This generally duplicates a lot of the existing matching code, but we can't just remove
that without introducing regressions, so the existing code is renamed and used less often.
Follow-ups may try to reduce that overlap.
Differential Revision: https://reviews.llvm.org/D56450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350826
91177308-0d34-0410-b5e6-
96231b3b80d8
Bryan Chan [Thu, 10 Jan 2019 15:02:37 +0000 (15:02 +0000)]
[AArch64] Fix operation actions for FP16 vector intrinsics
Summary:
This patch changes the legalization action for some half-precision floating-
point vector intrinsics (FSIN, FLOG, etc.) from Promote to Expand. These ops
are not supported in hardware for half-precision vectors, but promotion is
not always possible (for v8f16 operands). Changing the action to Expand fixes
an assertion failure in the legalizer when the frontend produces such ops.
In addition, a quick microbenchmark shows that, in the v4f16 case,
expanding introduces fewer spills and is therefore slightly faster than
promoting.
Reviewers: t.p.northover, SjoerdMeijer
Reviewed By: SjoerdMeijer
Subscribers: javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D56296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350825
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Thu, 10 Jan 2019 14:55:26 +0000 (14:55 +0000)]
[llvm-objdump] - Implement -z/--disassemble-zeroes.
This is https://bugs.llvm.org/show_bug.cgi?id=37151,
GNU objdump spec says that "Normally the disassembly output will skip blocks of zeroes.",
but currently, llvm-objdump prints them.
The patch implements the -z/--disassemble-zeroes option and switches the default to always
skip blocks of zeroes.
Differential revision: https://reviews.llvm.org/D56083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350823
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Thu, 10 Jan 2019 14:26:15 +0000 (14:26 +0000)]
[X86] Add SSE41 vector abs tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350822
91177308-0d34-0410-b5e6-
96231b3b80d8
James Henderson [Thu, 10 Jan 2019 14:10:02 +0000 (14:10 +0000)]
[llvm-symbolizer] Add support for specifying addresses on command-line
See https://bugs.llvm.org/show_bug.cgi?id=40070.
GNU addr2line accepts input addresses both on the command-line and via
stdin. llvm-symbolizer previously only supported the latter. This
change adds support for the former. As with addr2line, the new
behaviour is to only look for addresses on stdin if no positional
arguments were provided to llvm-symbolizer.
Reviewed by: ruiu
Differential Revision: https://reviews.llvm.org/D56272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350821
91177308-0d34-0410-b5e6-
96231b3b80d8
Andrea Di Biagio [Thu, 10 Jan 2019 13:59:13 +0000 (13:59 +0000)]
[MCA] Fix wrong definition of ResourceUnitMask in DefaultResourceStrategy.
Field ResourceUnitMask was incorrectly defined as a 'const unsigned' mask. It
should have been a 64 bit quantity instead. That means, ResourceUnitMask was
always implicitly truncated to a 32 bit quantity.
This issue has been found by inspection. Surprisingly, that bug was latent, and
it never negatively affected any existing upstream targets.
This patch fixes the wrong definition of ResourceUnitMask, and adds a bunch of
extra debug prints to help debugging potential issues related to invalid
processor resource masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350820
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Thu, 10 Jan 2019 10:47:23 +0000 (10:47 +0000)]
[ARM] Fix for verifier buildbot
Copy the MachineOperand first and then change the flags instead of
making a copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350811
91177308-0d34-0410-b5e6-
96231b3b80d8
Fedor Sergeev [Thu, 10 Jan 2019 10:01:53 +0000 (10:01 +0000)]
[LoopUnroll] add parsing for unroll parameters in -passes pipeline
Allow to specify loop-unrolling with optional parameters explicitly
spelled out in -passes pipeline specification.
Introducing somewhat generic way of specifying parameters parsing via
FUNCTION_PASS_PARAMETRIZED pass registration.
Syntax of parametrized unroll pass name is as follows:
'unroll<' parameter-list '>'
Where parameter-list is ';'-separate list of parameter names and optlevel
optlevel: 'O[0-3]'
parameter: { 'partial' | 'peeling' | 'runtime' | 'upperbound' }
negated: 'no-' parameter
Example:
-passes=loop(unroll<O3;runtime;no-upperbound>)
this invokes LoopUnrollPass configured with OptLevel=3,
Runtime, no UpperBound, everything else by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350808
91177308-0d34-0410-b5e6-
96231b3b80d8
Bjorn Pettersson [Thu, 10 Jan 2019 09:58:23 +0000 (09:58 +0000)]
Fix RUN line in test/Transforms/LoopDeletion/crashbc.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350807
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Parker [Thu, 10 Jan 2019 08:36:33 +0000 (08:36 +0000)]
[ARM] Size reduce teq to eors
Add t2TEQrr to the map of instructions with can be reduced down into
a T1 instruction. This is a special case because TEQ just sets the
CPSR and doesn't write to a GPR, which is not the case for EOR. So,
we need to ensure that the EOR can write to the first operand.
Differential Revision: https://reviews.llvm.org/D56255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350801
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 10 Jan 2019 07:43:54 +0000 (07:43 +0000)]
[X86] Disable DomainReassignment pass when AVX512BW is disabled to avoid injecting VK32/VK64 references into the MachineIR
Summary:
This pass replaces GR8/GR16/GR32/GR64 with their equivalent sized mask register classes. But VK32/VK64 aren't legal without AVX512BW. Apparently this mostly appears to work if the register coalescer is able to remove the VK32/VK64 register class reference. Or if we don't ever spill it. But there's no guarantee of that.
Another Intel employee managed to trigger a crash due to this with ISPC. Unfortunately, I've lost the test case he sent me at the time. I'm trying to get him to reproduce it for me. I'd like to get this in before 8.0 branches since its a little scary.
The regressions here are unfortunate, but I think we can make some improvements to DAG combine, load folding, etc. to fix them. Just not sure if we can get that done for 8.0.
Fixes PR39741
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350800
91177308-0d34-0410-b5e6-
96231b3b80d8
Zi Xuan Wu [Thu, 10 Jan 2019 06:20:14 +0000 (06:20 +0000)]
Recommit "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"
This re-commit r350685.
Differential Revision: https://reviews.llvm.org/D55686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350799
91177308-0d34-0410-b5e6-
96231b3b80d8
Mandeep Singh Grang [Thu, 10 Jan 2019 04:59:44 +0000 (04:59 +0000)]
[AArch64] Emit the correct MCExpr relocations specifiers like VK_ABS_G0, etc
Summary:
D55896 and D56029 add support to emit fixups for :abs_g0: , :abs_g1_s: , etc.
This patch adds the necessary enums and MCExpr needed for lowering these.
Reviewers: rnk, mstorsjo, efriedma
Reviewed By: efriedma
Subscribers: javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D56037
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350798
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Thu, 10 Jan 2019 04:09:25 +0000 (04:09 +0000)]
Revert "[WebAssembly] Add simd128-unimplemented subtarget feature"
This reverts rL350791.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350795
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Thu, 10 Jan 2019 03:25:20 +0000 (03:25 +0000)]
[AMDGPU] Separate feature dot-insts
Differential Revision: https://reviews.llvm.org/D56524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350793
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Thu, 10 Jan 2019 02:55:52 +0000 (02:55 +0000)]
[WebAssembly] Add simd128-unimplemented subtarget feature
This is a second attempt at r350778, which was reverted in
r350789. The only change is that the unimplemented-simd128 feature has
been renamed simd128-unimplemented, since naming it
unimplemented-simd128 somehow made the simd128 feature flag enable the
unimplemented-simd128 feature on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350791
91177308-0d34-0410-b5e6-
96231b3b80d8
Jorge Gorbe Moya [Thu, 10 Jan 2019 01:51:54 +0000 (01:51 +0000)]
Revert "Fix go bindings for r350647: missed a function rename"
This reverts commit
a74266858a8164cfb23d4e138cd4c7c37be0b5d1. SVN revision r350657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350790
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Thu, 10 Jan 2019 01:37:44 +0000 (01:37 +0000)]
Revert "[WebAssembly] Add unimplemented-simd128 subtarget feature"
This reverts L350778.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350789
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Thu, 10 Jan 2019 00:16:54 +0000 (00:16 +0000)]
[MemorySSA] Remove optimized value when reseting optimized.
Summary:
If we don't reset the optimized value O for access A, even though A is no longer optimized to O, A will still show up in that O's users list.
This fails verification when hoisting a Def outside a loop, even though the updates are correct.
The reason is that the phi in the loop header still find as user the hoisted def, because the Def has a pointer to the Phi in its optimized operand.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D56467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350783
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 10 Jan 2019 00:14:27 +0000 (00:14 +0000)]
[X86] After turning VSELECT into SHRUNKBLEND, make we push the VSELECT into the worklist so it can be deleted.
Found while trying to figure out why my second version of D56421 worked better than the first version. We weren't deleting the vselect in a timely fashion and that caused SimplfyDemandedBit to see an additional user.
The new version doesn't have this problem so this fix isn't needed there, but seemed like the right thing to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350781
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 9 Jan 2019 23:59:37 +0000 (23:59 +0000)]
[WebAssembly] Add unimplemented-simd128 subtarget feature
Summary:
This replaces the old ad-hoc -wasm-enable-unimplemented-simd
flag. Also makes the new unimplemented-simd128 feature imply the
simd128 feature.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits, alexcrichton
Differential Revision: https://reviews.llvm.org/D56501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350778
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Wed, 9 Jan 2019 23:57:15 +0000 (23:57 +0000)]
[llvm-mca] Display masks in hex
Display the resources masks as hexadecimal. Otherwise, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350777
91177308-0d34-0410-b5e6-
96231b3b80d8
Eli Friedman [Wed, 9 Jan 2019 23:39:26 +0000 (23:39 +0000)]
[SimplifyLibCalls] Fix memchr expansion for constant strings.
The C standard says "The memchr function locates the first
occurrence of c (converted to an unsigned char)[...]". The expansion
was missing the conversion to unsigned char.
Fixes https://bugs.llvm.org/show_bug.cgi?id=39041 .
Differential Revision: https://reviews.llvm.org/D55947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350775
91177308-0d34-0410-b5e6-
96231b3b80d8
David Major [Wed, 9 Jan 2019 23:36:32 +0000 (23:36 +0000)]
Don't require a null terminator when loading objects
When a null terminator is required and the file size is a multiple of the system page size, MemoryBuffer will prefer pread() over mmap(), which can result in excessive memory usage.
Patch by Mike Hommey!
Differential Revision: https://reviews.llvm.org/D56475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350774
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Wed, 9 Jan 2019 23:05:21 +0000 (23:05 +0000)]
[WebAssembly] Print a debug message at the start of each pass
Summary:
Looks like many passes print its pass description as a debug message at
the start of each pass, so added that to (mostly newly added) other
passes as well.
Reviewers: dschuff
Subscribers: jgravelle-google, sbc100, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D56142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350771
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Wed, 9 Jan 2019 21:04:36 +0000 (21:04 +0000)]
[AArch64] Add test for constant shrinking with multiple users (NFC).
Test to avoid regression fixed by rL350684.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350762
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Wed, 9 Jan 2019 20:10:27 +0000 (20:10 +0000)]
Refactor synthetic profile count computation. NFC.
Summary:
Instead of using two separate callbacks to return the entry count and the
relative block frequency, use a single callback to return callsite
count. This would allow better supporting hybrid mode in the future as
the count of callsite need not always be derived from entry count (as in
sample PGO).
Reviewers: davidxl
Subscribers: mehdi_amini, steven_wu, dexonsmith, dang, llvm-commits
Differential Revision: https://reviews.llvm.org/D56464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350755
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 9 Jan 2019 19:46:15 +0000 (19:46 +0000)]
[CodeGen] Ignore return sext/zext attributes of unused results for tail calls
If the caller's return type does not have a zeroext attribute but the
callee does a tail call zeroext, we won't consider the tail call during
CodeGenPrepare because the attributes don't match.
However, if the result of the tail call has no uses, it makes sense to
drop the sext/zext attributes.
Differential Revision: https://reviews.llvm.org/D56486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350753
91177308-0d34-0410-b5e6-
96231b3b80d8
Easwaran Raman [Wed, 9 Jan 2019 19:26:17 +0000 (19:26 +0000)]
[Inliner] Assert that the computed inline threshold is non-negative.
Reviewers: chandlerc
Subscribers: haicheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D56409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350751
91177308-0d34-0410-b5e6-
96231b3b80d8
David Callahan [Wed, 9 Jan 2019 19:12:38 +0000 (19:12 +0000)]
refactor BlockFrequencyInfo::view to take a title parameter
Summary: All a non-default title for the debugging this debugging aide
Reviewers: twoh, Kader, modocache
Reviewed By: twoh
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350749
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Wed, 9 Jan 2019 18:59:56 +0000 (18:59 +0000)]
Fix visualization of intrusive reference counted objects in MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350748
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Lively [Wed, 9 Jan 2019 18:13:11 +0000 (18:13 +0000)]
[WebAssembly] Standardize order of SIMD bitselect arguments
Summary:
For some reason the backend assumed that the condition mask would be
the first argument to the LLVM intrinsic, but everywhere else the
condition mask is the third argument.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D56412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350746
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Wed, 9 Jan 2019 17:29:18 +0000 (17:29 +0000)]
[x86] use 'nounwind' to remove test noise; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350745
91177308-0d34-0410-b5e6-
96231b3b80d8
Hubert Tong [Wed, 9 Jan 2019 16:00:39 +0000 (16:00 +0000)]
[unittests][Support] AIX: Skip sticky bit file tests
On AIX, attempting (without root) to set the sticky bit on a file with
the `chmod` utility will give:
```
chmod: not all requested changes were made to <file>
```
The same occurs when modifying other permission bits on a file with the
sticky bit already set.
It seems that the `chmod` function will report success despite failing
to set the sticky bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350735
91177308-0d34-0410-b5e6-
96231b3b80d8
Aleksandar Beserminji [Wed, 9 Jan 2019 15:58:02 +0000 (15:58 +0000)]
[mips][micrompis] Emit 16bit NOPs by default
Emit 16bit NOPs by default.
Use 32bit NOPs in delay slots where necessary.
Differential https://reviews.llvm.org/D55323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350733
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Wed, 9 Jan 2019 15:41:44 +0000 (15:41 +0000)]
[DEBUGINFO][NVPTX]Make tests more strict, NFC.
NVPTX format requires that no labels/label arithmetics is used in the
debug info sections. To avoid possible problems with the adding/modifying the debug info functionality, made these tests more strict.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350731
91177308-0d34-0410-b5e6-
96231b3b80d8
Valery Pykhtin [Wed, 9 Jan 2019 15:21:53 +0000 (15:21 +0000)]
Revert "[AMDGPU] Fix DPP combiner"
This reverts commit
e3e2923a39cbec3b3bc3a7d3f0e9a77a4115080e, svn revision rL350721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350730
91177308-0d34-0410-b5e6-
96231b3b80d8
Kristof Beyls [Wed, 9 Jan 2019 15:13:34 +0000 (15:13 +0000)]
Initial AArch64 SLH implementation.
This is an initial implementation for Speculative Load Hardening for
AArch64. It builds on top of the recently introduced
AArch64SpeculationHardening pass.
This doesn't implement (yet) some of the optimizations implemented for
the X86SpeculativeLoadHardening pass. I thought introducing the
optimizations incrementally in follow-up patches should make this easier
to review.
Differential Revision: https://reviews.llvm.org/D55929
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350729
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Wed, 9 Jan 2019 14:43:33 +0000 (14:43 +0000)]
[llvm-objdump] - Print symbol addressed when dumping disassembly output (-d)
When GNU objdump dumps the input with -d it prints the symbol addresses,
for example:
0000000000000031 <foo>:
31: 00 00 add %al,(%rax)
...
llvm-objdump currently does not do that.
Patch changes the behavior to match the GNU objdump.
That is useful for implementing -z/--disassemble-zeroes (D56083),
it allows omitting first zero bytes and keep the information
about the symbol address in the output.
Differential revision: https://reviews.llvm.org/D56123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350726
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 9 Jan 2019 14:20:20 +0000 (14:20 +0000)]
Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350725
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 9 Jan 2019 13:46:14 +0000 (13:46 +0000)]
[X86][SSE] Cleanup shuffle combining test check prefixes
Share prefixes whenever possible, use X86 instead of X32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350722
91177308-0d34-0410-b5e6-
96231b3b80d8
Valery Pykhtin [Wed, 9 Jan 2019 13:43:32 +0000 (13:43 +0000)]
[AMDGPU] Fix DPP combiner
Fixed issue with identity values and other cases, f32/f16 identity values to be added later. fma/mac instructions is disabled for now.
Test is fully reworked, added comments. Other fixes:
1. dpp move with uses and old reg initializer should be in the same BB.
2. bound_ctrl:0 is only considered when bank_mask and row_mask are fully enabled (0xF). Othervise the old register value is checked for identity.
3. Added add, subrev, and, or instructions to the old folding function.
4. Kill flag is cleared for the src0 (DPP register) as it may be copied into more than one user.
Differential revision: https://reviews.llvm.org/D55444
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350721
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Wed, 9 Jan 2019 13:32:16 +0000 (13:32 +0000)]
Revert r350647: "[NewPM] Port tsan"
This patch breaks thread sanitizer on some macOS builders, e.g.
http://green.lab.llvm.org/green/job/clang-stage1-configure-RA/52725/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350719
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 9 Jan 2019 13:23:28 +0000 (13:23 +0000)]
[X86] Enable combining shuffles to PACKSS/PACKUS for 256/512-bit vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350716
91177308-0d34-0410-b5e6-
96231b3b80d8
Anton Korobeynikov [Wed, 9 Jan 2019 13:03:01 +0000 (13:03 +0000)]
[MSP430] Optimize 'shl x, 8[+ N] -> swpb(zext(x)) [<< N]' for i16
Perform additional simplification to reduce shift amount.
Patch by Kristina Bessonova!
Differential Revision: https://reviews.llvm.org/D56016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350712
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 9 Jan 2019 12:57:52 +0000 (12:57 +0000)]
[gn build] Run `git ls-files '*.gn' '*.gni' | xargs -n 1 gn format`
Looks like I forgot to do that for the PowerPC target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350711
91177308-0d34-0410-b5e6-
96231b3b80d8
Anton Korobeynikov [Wed, 9 Jan 2019 12:52:15 +0000 (12:52 +0000)]
[MSP430] Fix crash while lowering llvm.stacksave/stackrestore
Perform the usual expansion of stacksave / restore intrinsics.
Patch by Kristina Bessonova!
Differential Revision: https://reviews.llvm.org/D54890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350710
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 9 Jan 2019 12:48:06 +0000 (12:48 +0000)]
[gn build] Merge r350669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350709
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Wed, 9 Jan 2019 12:46:04 +0000 (12:46 +0000)]
[gn build] Add a TODO.txt file
Differential Revision: https://reviews.llvm.org/D56420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350708
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 9 Jan 2019 12:34:10 +0000 (12:34 +0000)]
[X86] Add extra test coverage for combining shuffles to PACKSS/PACKUS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350707
91177308-0d34-0410-b5e6-
96231b3b80d8
Diogo N. Sampaio [Wed, 9 Jan 2019 11:24:15 +0000 (11:24 +0000)]
[AArch64] Move feature predctrl to predres
Follow up patch of rL350385, for adding predres
command line option. This patch renames the
feature as to keep it aligned with the option
passed by/to clang
Differential Revision: https://reviews.llvm.org/D56484
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350702
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 9 Jan 2019 11:18:49 +0000 (11:18 +0000)]
[X86] Fix gcc7 -Wunused-but-set-variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350701
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexander Kornienko [Wed, 9 Jan 2019 10:49:44 +0000 (10:49 +0000)]
Make the write_cmake_config.py script python3-compatible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350700
91177308-0d34-0410-b5e6-
96231b3b80d8
David Stenberg [Wed, 9 Jan 2019 09:58:59 +0000 (09:58 +0000)]
[DebugInfo] Omit location list entries with empty ranges
Summary:
This fixes PR39710. In that case we emitted a location list looking like
this:
.Ldebug_loc0:
.quad .Lfunc_begin0-.Lfunc_begin0
.quad .Lfunc_begin0-.Lfunc_begin0
.short 1 # Loc expr size
.byte 85 # DW_OP_reg5
.quad .Lfunc_begin0-.Lfunc_begin0
.quad .Lfunc_end0-.Lfunc_begin0
.short 1 # Loc expr size
.byte 85 # super-register DW_OP_reg5
.quad 0
.quad 0
As seen, the first entry's beginning and ending addresses evalute to 0,
which meant that the entry inadvertently became an "end of list" entry,
resulting in the location list ending sooner than expected.
To fix this, omit all entries with empty ranges. Location list entries
with empty ranges do not have any effect, as specified by DWARF, so we
might as well drop them:
"A location list entry (but not a base address selection or end of list
entry) whose beginning and ending addresses are equal has no effect
because the size of the range covered by such an entry is zero."
Reviewers: davide, aprantl, dblaikie
Reviewed By: aprantl
Subscribers: javed.absar, JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D55919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350698
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 9 Jan 2019 07:51:52 +0000 (07:51 +0000)]
GlobalISel: Implement fewerElements for implicit_def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350697
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 9 Jan 2019 07:34:14 +0000 (07:34 +0000)]
GlobalISel: Implement widenScalar for implicit_def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350695
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Wed, 9 Jan 2019 07:28:13 +0000 (07:28 +0000)]
[IPT] Drop cache less eagerly in GVN and LoopSafetyInfo
Current strategy of dropping `InstructionPrecedenceTracking` cache is to
invalidate the entire basic block whenever we change its contents. In fact,
`InstructionPrecedenceTracking` has 2 internal strictures: `OrderedInstructions`
that is needed to be invalidated whenever the contents changes, and the map
with first special instructions in block. This second map does not need an
update if we add/remove a non-special instuction because it cannot
affect the contents of this map.
This patch changes API of `InstructionPrecedenceTracking` so that it now
accounts for reasons under which we invalidate blocks. This should lead
to much less recalculations of the map and should save us some compile time
because in practice we don't typically add/remove special instructions.
Differential Revision: https://reviews.llvm.org/D54462
Reviewed By: efriedma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350694
91177308-0d34-0410-b5e6-
96231b3b80d8
Zi Xuan Wu [Wed, 9 Jan 2019 06:12:24 +0000 (06:12 +0000)]
Revert "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"
This reverts commit r350685.
See compile assert in compiler-rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350693
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Inoue [Wed, 9 Jan 2019 05:11:10 +0000 (05:11 +0000)]
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350690
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Wed, 9 Jan 2019 04:39:29 +0000 (04:39 +0000)]
gn build: Copy file permissions from input file in configure_file() emulation.
Most significantly, this makes bin/llvm-lit executable so that it
can be run in the usual way.
Differential Revision: https://reviews.llvm.org/D56423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350688
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 9 Jan 2019 04:21:12 +0000 (04:21 +0000)]
[X86] Correct the MaskVT for avx512 gather/scatter intrinsics to use the min of the number of index and data elements.
When the result type is v2i64/v2f64 and the index element size is i32, the index vector has two unused elements making the type v4i32. The mask VT should match the number of memory accesses that will be made.
This is consistent with the isel patterns used for the target independent gather/scatter intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350687
91177308-0d34-0410-b5e6-
96231b3b80d8
Peter Collingbourne [Wed, 9 Jan 2019 04:05:07 +0000 (04:05 +0000)]
gn build: Fix a Python2ism in write_vcsrevision.py.
Convert the output of "git rev-parse --short HEAD" to a string before
substituting it into the output file. Without this the output file
will look like this on Python 3:
#define LLVM_REVISION "git-b'
6a4895a025f'"
Differential Revision: https://reviews.llvm.org/D56459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350686
91177308-0d34-0410-b5e6-
96231b3b80d8
Zi Xuan Wu [Wed, 9 Jan 2019 02:31:10 +0000 (02:31 +0000)]
[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel
Bad machine code: Illegal virtual register for instruction
function: TestULE
basic block: %bb.0 entry (0x1000a39b158)
instruction: %2:crrc = FCMPUD %1:vsfrc, %3:f8rc
operand 1: %1:vsfrc
Fix assert about missing match between fcmp instruction and register class.
We should use vsx related cmp instruction xvcmpudp instead of fcmpu when vsx is opened.
add -verifymachineinstrs option into related test cases to enable the verify pass.
Differential Revision: https://reviews.llvm.org/D55686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350685
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Wed, 9 Jan 2019 02:24:22 +0000 (02:24 +0000)]
Remove check for single use in ShrinkDemandedConstant
This removes check for single use from general ShrinkDemandedConstant
to the BE because of the AArch64 regression after D56289/rL350475.
After several hours of experiments I did not come up with a testcase
failing on any other targets if check is not performed.
Moreover, direct call to ShrinkDemandedConstant is not really needed
and superceed by SimplifyDemandedBits.
Differential Revision: https://reviews.llvm.org/D56406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350684
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 8 Jan 2019 23:22:18 +0000 (23:22 +0000)]
RegisterCoalescer: Assume CR_Replace for SubRangeJoin
Currently it's possible for following
check on V.WriteLanes (which is not really meaningful
during SubRangeJoin) to pass for one half of the pair,
and then fall through to to one of the impossible
or unresolved states. This then fails as inconsistent
on the other half.
During the main range join, the check between V.WriteLanes
and OtherV.ValidLanes must have passed, meaning this
should be a CR_Replace.
Fixes most of the testcases in bugs 39542 and 39602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350678
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 8 Jan 2019 23:10:47 +0000 (23:10 +0000)]
RegisterCoalescer: Defer clearing implicit_def lanes
We can't go back and recover the lanes if it turns
out the implicit_def really can't be erased.
Assume all lanes are valid if an unresolved conflict
is encountered. There aren't any tests where this
seems to matter either way, but this seems like a
safer option.
Fixes bug 39602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350676
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 8 Jan 2019 22:52:08 +0000 (22:52 +0000)]
[InstCombine] remove stale comments; NFC
These changed with rL350672.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350674
91177308-0d34-0410-b5e6-
96231b3b80d8
Rong Xu [Tue, 8 Jan 2019 22:41:48 +0000 (22:41 +0000)]
[llvm-profdata] add value-cutoff functionality in show command
This patch improves llvm-profdata show command:
(1) add -value-cutoff=<N> option: Show only those functions whose max count
values are greater or equal to N.
(2) add -list-below-cutoff option: Only output names of functions whose max
count value are below the cutoff.
(3) formats value-profile counts and prints out percentage.
Differential Revision: https://reviews.llvm.org/D56342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350673
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 8 Jan 2019 22:39:55 +0000 (22:39 +0000)]
[InstCombine] canonicalize another raw IR rotate pattern to funnel shift
This is matching the equivalent of the DAG expansion,
so it should never end up with worse perf than the
original code even if the target doesn't have a rotate
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350672
91177308-0d34-0410-b5e6-
96231b3b80d8
Rong Xu [Tue, 8 Jan 2019 22:39:47 +0000 (22:39 +0000)]
[PGO] Use SourceFileName rather module name in PGOFuncName
In LTO or Thin-lto mode (though linker plugin), the module
names are of temp file names which are different for
different compilations. Using SourceFileName avoids the issue.
This should not change any functionality for current PGO as
all the current callers of getPGOFuncName() is before LTO.
Differential Revision: https://reviews.llvm.org/D56327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350671
91177308-0d34-0410-b5e6-
96231b3b80d8
Rong Xu [Tue, 8 Jan 2019 22:37:12 +0000 (22:37 +0000)]
[PGO] Revert r350579 to fix commit message.
Will re-commit it using the correct commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350670
91177308-0d34-0410-b5e6-
96231b3b80d8
Heejin Ahn [Tue, 8 Jan 2019 22:35:18 +0000 (22:35 +0000)]
[WebAssembly] Rename StoreResults to MemIntrinsicResults
Summary:
StoreResults pass does not optimize store instructions anymore because
store instructions don't return results values anymore. Now this pass is
used solely for memory intrinsics, so update the pass name accordingly
and fix outdated pass descriptions as well.
This patch does not change any meaningful behavior, but not marked as
NFC because it changes a comment check line in a test case.
Reviewers: dschuff
Subscribers: mgorny, sbc100, jgravelle-google, sunfiish, llvm-commits
Differential Revision: https://reviews.llvm.org/D56093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350669
91177308-0d34-0410-b5e6-
96231b3b80d8
Rong Xu [Tue, 8 Jan 2019 22:33:29 +0000 (22:33 +0000)]
[PGO] Revert r350442 to fix commit message.
Will re-commit it using the correct commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350667
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Tue, 8 Jan 2019 22:29:58 +0000 (22:29 +0000)]
[AArch64] Adjust the cost model for Exynos
Improve the modeling of ALU instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350663
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Tue, 8 Jan 2019 22:29:56 +0000 (22:29 +0000)]
[llvm-mca] Update the Exynos test cases (NFC)
Add more entropy to the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350662
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Tue, 8 Jan 2019 22:29:38 +0000 (22:29 +0000)]
[llvm-mca] Improve debugging (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350661
91177308-0d34-0410-b5e6-
96231b3b80d8
Jorge Gorbe Moya [Tue, 8 Jan 2019 21:45:42 +0000 (21:45 +0000)]
Fix go bindings for r350647: missed a function rename
Differential Revision: https://reviews.llvm.org/D56452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350657
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Tue, 8 Jan 2019 21:05:51 +0000 (21:05 +0000)]
[llvm-undname] Add support for demangling msvc's noexcept types.
Starting in C++17, MSVC introduced a new mangling for function
parameters that are themselves noexcept functions. This patch
makes llvm-undname properly demangle them.
Patch by Zachary Henkel
Differential Revision: https://reviews.llvm.org/D55769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350656
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Tue, 8 Jan 2019 21:05:34 +0000 (21:05 +0000)]
Don't write #include "Windows/WindowsSupport.h" from the Windows dir.
This generates -Wnonportable-include-dir warnings, and doesn't need
to be there. It seems this was just checked in on accident.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350655
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Tue, 8 Jan 2019 21:05:10 +0000 (21:05 +0000)]
Revert "Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into header and cpp files""""
This reverts commit D56084.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350654
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Tue, 8 Jan 2019 21:05:08 +0000 (21:05 +0000)]
Revert "Work around a linker error caused by https://reviews.llvm.org/D56084."
This reverts commit r350650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350653
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Tue, 8 Jan 2019 20:38:22 +0000 (20:38 +0000)]
Work around a linker error caused by https://reviews.llvm.org/D56084.
This unbreaks all bots that build with -DLLVM_ENABLE_MODULES=1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350650
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Pfaffe [Tue, 8 Jan 2019 19:21:57 +0000 (19:21 +0000)]
[NewPM] Port tsan
A straightforward port of tsan to the new PM, following the same path
as D55647.
Differential Revision: https://reviews.llvm.org/D56433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350647
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 8 Jan 2019 19:15:21 +0000 (19:15 +0000)]
[x86] add tests for PR40243; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350646
91177308-0d34-0410-b5e6-
96231b3b80d8
Paul Robinson [Tue, 8 Jan 2019 17:52:29 +0000 (17:52 +0000)]
Rename DIFlagFixedEnum to DIFlagEnumClass. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350641
91177308-0d34-0410-b5e6-
96231b3b80d8
Anna Thomas [Tue, 8 Jan 2019 17:16:25 +0000 (17:16 +0000)]
[UnrollRuntime] Fix domTree failures in multiexit unrolling
Summary:
This fixes the IDom for exit blocks and all blocks reachable from the exit blocks, when runtime unrolling under multiexit/exiting case.
We initially had a restrictive check that the IDom is only updated when
it is the header of the loop.
However, we also need to update the IDom to the correct one when the
IDom is any block within the original loop. See added test cases (which
fail dom tree verification without the patch).
Reviewers: reames, mzolotukhin, mkazantsev, hfinkel
Reviewed by: brzycki, kuhar
Subscribers: zzheng, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D56284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350640
91177308-0d34-0410-b5e6-
96231b3b80d8
Yonghong Song [Tue, 8 Jan 2019 16:36:06 +0000 (16:36 +0000)]
[BPF] Fix .BTF.ext reloc type assigment issue
Commit
f1db33c5c1a9 ("[BPF] Disable relocation for .BTF.ext section")
assigned relocation type R_BPF_NONE if the fixup type
is FK_Data_4 and the symbol is temporary.
The reason is we use FK_Data_4 as a fixup type
for insn offsets in .BTF.ext section.
Just checking whether the symbol is temporary is not enough.
For example, .debug_info may reference some strings whose
fixup is FK_Data_4 with a temporary symbol as well.
To truely reflect the case for .BTF.ext section,
this patch further checks that the section associateed with the symbol
must be SHF_ALLOC and SHF_EXECINSTR, i.e., in the text section.
This fixed the above-mentioned problem.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350637
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 8 Jan 2019 15:19:00 +0000 (15:19 +0000)]
[gn build] Update readme
Differential Revision: https://reviews.llvm.org/D56375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350632
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 8 Jan 2019 15:17:19 +0000 (15:17 +0000)]
[gn build] Make sync_source_lists_from_cmake.py check that all LLVM unittests are present
Now that the PowerPC and WebAssembly targets are added, this check passes.
Differential Revision: https://reviews.llvm.org/D56417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350631
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Tue, 8 Jan 2019 15:16:23 +0000 (15:16 +0000)]
[MachineVerifier] Include offending register in allocatable live-in error msg.
This patch adds a convenience report() method for physical registers and
uses it to print the offending register with the 'MBB has allocatable
live-in' error.
Reviewers: MatzeB, rtereshin, dsanders
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D55946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350630
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 8 Jan 2019 15:16:14 +0000 (15:16 +0000)]
[gn build] Add build files for llvm/lib/Target/PowerPC + tests
The PowerPC target itself is similar to the X86 target in https://reviews.llvm.org/rL348903
The llvm-exegesis unittests bits are similar to the corresponding AArch64 in https://reviews.llvm.org/rL350499
The whole patch is very similar to the WebAssembly target being added in https://reviews.llvm.org/rL350628
Also add a dep from tools/llvm-exegesis/lib to the AArch64 subdir, which I
failed to do in r350499.
The motivation for this target is solely that it has a unit test and I want to
enable the GN<->CMake unittest syncing check for llvm.
Differential Revision: https://reviews.llvm.org/D56416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350629
91177308-0d34-0410-b5e6-
96231b3b80d8
Nico Weber [Tue, 8 Jan 2019 15:12:42 +0000 (15:12 +0000)]
[gn build] Add build files for llvm/lib/Target/WebAssembly + tests
The WebAssembly target itself is similar to the X86 target in https://reviews.llvm.org/rL348903
The unittests bits are similar to the corresponding AArch64 in https://reviews.llvm.org/rL350499
The motivation for this target is solely that it has a unit test and I want to
enable the GN<->CMake unittest syncing check for llvm. (After this, only the
PowerPC target is needed and I can turn it on.)
Differential Revision: https://reviews.llvm.org/D56374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350628
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Pavlu [Tue, 8 Jan 2019 14:19:06 +0000 (14:19 +0000)]
[GlobalISel] Fix choice of instruction selector for AArch64 at -O0 with -global-isel=0
Commit rL347861 introduced an unintentional change in the behaviour when
compiling for AArch64 at -O0 with -global-isel=0. Previously, explicitly
disabling GlobalISel resulted in using FastISel but an updated condition
in the commit changed it to using SelectionDAG. The patch fixes this
condition and slightly better organizes the code that chooses the
instruction selector.
Fixes PR40131.
Differential Revision: https://reviews.llvm.org/D56266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350626
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Pfaffe [Tue, 8 Jan 2019 14:06:58 +0000 (14:06 +0000)]
[DA][NewPM] Add a printerpass and port the testsuite
The new-pm version of DA is untested. Testing requires a printer, so
add that and use it in the existing DA tests.
Differential Revision: https://reviews.llvm.org/D56386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350624
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Tue, 8 Jan 2019 13:53:15 +0000 (13:53 +0000)]
[X86][Darwin] Emit compact-unwind for register-sized stack adjustments
For stack frames on the size of a register in x86, a code size optimization
emits "push rax/eax" instead of "sub" for stack allocation. For example:
foo:
.cfi_startproc
BB#0:
pushq %rax
Ltmp0:
.cfi_def_cfa_offset 16
...
.cfi_endproc
However, we are falling back to DWARF in this case because we cannot
encode %rax as a saved register.
This requirement is wrong, since we don't care about the contents of
%rax, it is the equivalent of a sub.
In order to specify that we care about the contents of %rax, we would
need a .cfi_offset %rax, <offset>.
It's also overzealous in the case where there are pushes for callee saved
registers followed by a "push rax/eax" instead of "sub", in which case we should
also be able to encode the callee saved regs and everything else using compact
unwind.
Patch authored by Bruno Cardoso Lopes.
Differential Revision: https://reviews.llvm.org/D13793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350623
91177308-0d34-0410-b5e6-
96231b3b80d8
Lama Saba [Tue, 8 Jan 2019 13:30:36 +0000 (13:30 +0000)]
Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into header and cpp files"""
This reverts commit rL350497
reported remaining issues seem to be unrelated to modules or this change.
more info: https://reviews.llvm.org/D56084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350621
91177308-0d34-0410-b5e6-
96231b3b80d8