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Eric Anholt [Thu, 28 Aug 2014 21:44:54 +0000 (14:44 -0700)]
vc4: Claim ARB_fbo.
This gets a ton of piglit working that crashes in waffle context
management stuff otherwise. Actually supporting mismatched FB sizes is at
best going to require some more load/store generals for color buffers, but
if I can't manage to do that I'll want to just have state_tracker reject
those FBOs as unsupported, rather than deny GL 2.1.
Eric Anholt [Mon, 15 Sep 2014 18:48:02 +0000 (11:48 -0700)]
vc4: Fix memory leaks in register allocation.
Eric Anholt [Mon, 15 Sep 2014 18:45:56 +0000 (11:45 -0700)]
vc4: Move register allocation to a separate file.
I'm going to be rewriting it all, and having it mixed up with the
QIR-to-QPU opcode translation was messy.
Chris Forbes [Tue, 9 Sep 2014 07:55:29 +0000 (19:55 +1200)]
glsl: fix error message for redeclaring gl_PerVertex as output
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Forbes [Tue, 9 Sep 2014 07:55:28 +0000 (19:55 +1200)]
i965/vec4: slightly improve insn dumping with no srcs
Previously, we would get a trailing ', ' which looked strange.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 16 Sep 2014 19:55:16 +0000 (12:55 -0700)]
vc4: Add support for computed depth writes.
Fixes piglit glsl-1.10-fragdepth and early-z.
Eric Anholt [Tue, 16 Sep 2014 18:20:52 +0000 (11:20 -0700)]
vc4: Restructure depth input/output in fragment shaders.
The goal here is to have an argument for the depth write opcode so that I
can do computed depth. In the process, this makes the calculations that
will be emitted more obvious in the QIR.
Ilia Mirkin [Tue, 16 Sep 2014 01:42:01 +0000 (21:42 -0400)]
freedreno: add a standalone ir3_compiler binary for building TGSI
Compiler taken from the combo old/new compiler comparer + simulator.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 16 Sep 2014 01:42:00 +0000 (21:42 -0400)]
freedreno: add default .dir-locals.el for emacs settings
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Gwenole Beauchesne [Tue, 9 Sep 2014 08:56:24 +0000 (10:56 +0200)]
i965: add support for RGBA dma_buf imports.
This allows for importing foreign buffers in RGB32 native endian
byte order, i.e. DRM_FORMAT_XBGR8888, and DRM_FORMAT_ABGR8888.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Sat, 13 Sep 2014 00:45:30 +0000 (17:45 -0700)]
i965: Mark delta_x/y as BAD_FILE if remapped away completely.
Commit
afe3d1556f6b77031f7025309511a0eea2a3e8df (i965: Stop doing
remapping of "special" regs.) stopped remapping delta_x/delta_y, and
additionally stopped considering them always-live. We later realized
delta_x was used in register allocaiton, so we actually needed to remap
it, which was fixed in commit
23d782067ae834ad53522b46638ea21c62e94ca3
(i965/fs: Keep track of the register that hold delta_x/delta_y.).
However, that commit didn't restore the "always consider it live" part.
If all the code using delta_x was eliminated, fs_visitor::delta_x would
be left pointing at its old register number. Later code in register
allocation would handle that register number specially...even though it
wasn't actually delta_x.
To combat this, set delta_x/y to BAD_FILE if they're eliminated, and
check for that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83127
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Dave Airlie [Mon, 1 Sep 2014 23:51:56 +0000 (09:51 +1000)]
st_glsl_to_tgsi: init have_sqrt field.
Coverity reported this.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 15 Sep 2014 04:41:04 +0000 (14:41 +1000)]
llvmpipe: fix rast debugging output
The triangle_32_ rast functions never made it into the debug output,
confused me for a few seconds.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:32:38 +0000 (16:32 +0100)]
util: Add big-endian layout for a number of formats.
This patch builds on
6c8f547f66e68b495c708f8ffcb67370caa5ffe8 and
previous patches by allowing u_format.csv to specify separate big-endian
and little-endian layouts. It then uses this to specify the correct layouts
for various depth/stencil formats. Later patches handle other formats.
To recap, the idea is that u_format.csv lists the channels for an N-byte
value as though it were an N-byte integer. For little-endian targets
the channels are listed starting at the least-significant bit of the
integer while for big-endian targets the channels are listed starting
at the most-significant bit. This means that for something like
PIPE_FORMAT_B8G8R8A8_UNORM (blue in first byte of memory, alpha in last
byte of memory) the orders are the same for both endiannesses. But for
something like PIPE_FORMAT_S8_UINT_Z24_UNORM, where the stencil is in
the least significant byte of a 32-bit integer, there need to be separate
channel definitions for each endianness.
The effect of this patch is to make the affected PIPE_FORMAT_*s have
the same layout as the associated MESA_FORMAT_*s for big-endian.
The MESA_FORMAT_*s are already handled correctly.
Fixes various piglit tests on z. No regressions on x86_64.
[airlied: squash subsequent patches]
util: Add big-endian layout for 5551 and 565 formats
util: Add big-endian layout for 10/10/10/2 formats
util: Add big-endian layout for 4444 formats
util: Add big-endian layout for 233 format
util: Add big-endian layout for 44 formats
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:53:36 +0000 (16:53 +0100)]
llvmpipe: Fix PIPE_FORMAT_Z32_FLOAT_S8X24_UINT handling for big-endian.
llvmpipe treats PIPE_FORMAT_Z32_FLOAT_S8X24_UINT as a bit of a special case,
handling it as two 32-bit pieces rather than a single 64-bit block:
/* 64bit d/s format is special already extracted 32 bits */
total_bits = format_desc->block.bits > 32 ? 32 : format_desc->block.bits;
The format_desc describes the whole 64-bit block, so the z shift
will be 32 for big-endian. But since we're accessing the z channel
as a 32-bit value rather than a 64-bit value, we need to mask the shift
with 31.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:53:35 +0000 (16:53 +0100)]
gallivm: Fix uses of 2^24
Fallback cases in lp_bld_arit.c used 2^24 to mean "2 to the power 24",
but in C it's "2 xor 24", i.e. 26. Fixed by using 1<< instead.
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Richard Sandiford [Mon, 21 Jul 2014 15:53:34 +0000 (16:53 +0100)]
gallivm: Add SNORM clamping to lp_build_{add, sub}
...fixing the associated TODO.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Rafael Ávila de Espíndola [Tue, 16 Sep 2014 01:46:02 +0000 (03:46 +0200)]
gallivm: attach DataLayout to module too, not just pass manager.
It looks like it was possible to attach it to both for a long time, however
since llvm r217548 attaching it to just the pass manager is no longer
sufficient and causes bugs (see http://llvm.org/bugs/show_bug.cgi?id=20903).
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 15 Sep 2014 17:10:10 +0000 (19:10 +0200)]
gallivm: handle SAMPLE opcode in aos sampling
This is just a very limited version, in particular sampler and sampler view
index must be the same. It cannot handle any modifiers neither.
Works much the same as soa version otherwise, to figure out the target we
need to store the sampler view dcls.
While here, also handle (no-op) RET and get rid of a couple bogus deprecated
comments.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 15 Sep 2014 16:44:57 +0000 (18:44 +0200)]
tgsi: accept offsets for sample opcodes too in the text parser
sample opcodes are a little oddly represented in the opcode_info, since
they don't count as texture instructions - they don't have valid target
information, but they may have offsets (unlike "ordinary" texture
instructions, the texture token may be optional for them).
So just make sure with these opcodes the optional offsets are accepted.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Fri, 12 Sep 2014 22:29:56 +0000 (00:29 +0200)]
tgsi: don't print texture target for sample opcodes
sample opcodes don't encode a texture target, it would thus always
print UNKNOWN, which is not helpful (and wouldn't parse when giving
back the shader text to tgsi).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Eric Anholt [Mon, 15 Sep 2014 20:32:18 +0000 (13:32 -0700)]
vc4: Bump maximum ARB program temporaries to match Intel/AMD.
This query has always been useless, but we could potentially reject
well-formed, runnable programs if we expose a value that's too low.
Eric Anholt [Mon, 15 Sep 2014 20:26:24 +0000 (13:26 -0700)]
vc4: Bump maximum uniforms count to match other drivers.
We don't have any specific limits in the hardware, just like the other
GPUs, so match their behavior. Fixes minmax_gles2 and several other
piglit tests relying on the specced uniform minmax values.
Eric Anholt [Mon, 15 Sep 2014 19:02:43 +0000 (12:02 -0700)]
vc4: Dynamically allocate the TGSI-to-qreg arrays.
Fixes buffer overflows in some piglit tests (which are still failing to
register allocate anyway).
Eric Anholt [Mon, 15 Sep 2014 19:19:28 +0000 (12:19 -0700)]
vc4: Fix memory leaks of struct qinst.
Eric Anholt [Mon, 15 Sep 2014 19:15:02 +0000 (12:15 -0700)]
vc4: Fix memory leaks of some vc4_compile contents.
Eric Anholt [Mon, 15 Sep 2014 19:04:32 +0000 (12:04 -0700)]
vc4: Reuse the util header instead of defining our own ARRAY_SIZE.
Fixes redefinition warnings if you end up including this header before
util stuff.
Brian Paul [Fri, 12 Sep 2014 16:00:09 +0000 (10:00 -0600)]
mesa: move i, j var decls into SWIZZLE_CONVERT_LOOP() macro
Put macro code in do {} while loop and put semicolons on macro calls
so auto indentation works properly.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Fri, 12 Sep 2014 14:31:15 +0000 (08:31 -0600)]
mesa: break up _mesa_swizzle_and_convert() to reduce compile time
This reduces gcc -O3 compile time to 1/4 of what it was on my system.
Reduces MSVC release build time too.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kalyan Kondapally [Thu, 11 Sep 2014 03:20:23 +0000 (20:20 -0700)]
Generate a warning when not writing gl_Position with GLES.
With GLES we don't give any kind of warning in case we don't
write to gl_position. This patch makes changes so that we
generate a warning in case of GLES (VER < 300) and an error
in case of GL.
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tapani Pälli [Fri, 12 Sep 2014 07:36:08 +0000 (10:36 +0300)]
mesa: check that uniform exists in glUniform* functions
Remap table for uniforms may contain empty entries when using explicit
uniform locations. If no active/inactive variable exists with given
location, remap table contains NULL.
v2: move remap table bounds check before existence check (Ian Romanick)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Erik Faye-Lund <kusmabite@gmail.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83574
Chia-I Wu [Mon, 15 Sep 2014 01:09:54 +0000 (09:09 +0800)]
ilo: clean up 3D/media functions
Mostly style changes to set dw[0] directly.
Chia-I Wu [Mon, 15 Sep 2014 01:00:26 +0000 (09:00 +0800)]
ilo: fix gen6_3DSTATE_MULTISAMPLE()
There was a typo introduced by
90f4b131fccae3a950864ed9ba15eea8edce915f.
Rob Clark [Sat, 13 Sep 2014 12:25:51 +0000 (08:25 -0400)]
freedreno/a3xx: 3d/array textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 13 Sep 2014 02:20:07 +0000 (22:20 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Chia-I Wu [Sat, 13 Sep 2014 16:15:20 +0000 (00:15 +0800)]
ilo: trust vertex element count more
We might run into ve->count == 0 and last_velement_edgeflag == true in
gen6_3DSTATE_VERTEX_ELEMENTS() when the state tracker sets an invalid
combination of VS and VE (does not seem to happen with st/mesa). Do not
assume ve->count is positive when last_velement_edgeflag is true.
Reported by Coverity.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Sat, 13 Sep 2014 14:15:46 +0000 (22:15 +0800)]
ilo: simplify src operand gathering in disassembler
Always initialize the operand array to point to src0, src1, and src2.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Chia-I Wu [Sat, 13 Sep 2014 15:10:42 +0000 (23:10 +0800)]
ilo: derive 3-src instructions from the opcode table
One less switch statement to maintain.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Ilia Mirkin [Sat, 13 Sep 2014 15:28:28 +0000 (11:28 -0400)]
nouveau: check for mesa context init failure
Reported by Coverity
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 13 Sep 2014 15:06:17 +0000 (11:06 -0400)]
nouveau: avoid leaking screen on initialization fail
Reported by Coverity
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 13 Sep 2014 14:45:08 +0000 (10:45 -0400)]
nouveau: change internal variables to avoid conflicts with macro args
Reported by Coverity
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Chia-I Wu [Sat, 13 Sep 2014 00:54:41 +0000 (08:54 +0800)]
ilo: clean up 3DPRIMITIVE functions
Add ILO_PRIM_RECTANGLES to replace the rectlist bool.
Chia-I Wu [Fri, 12 Sep 2014 17:31:45 +0000 (01:31 +0800)]
ilo: clean up 3D/media common functions
Rename ilo_builder_batch_state_base_address() to gen6_state_base_address() for
consistency and remove unused gen6_STATE_BASE_ADDRESS(). Reorder the code in
gen6_PIPE_CONTROL() a bit. Finally, some mostly cosmetic changes.
Chia-I Wu [Fri, 12 Sep 2014 15:44:19 +0000 (23:44 +0800)]
ilo: move 3D functions to ilo_builder_3d*.h
Move functions for the 3D pipeline to the new headers. We artificially split
the functions into top (vertex processing) and bottom (pixel processing), to
keep the headers at reasonable sizes.
Chia-I Wu [Fri, 12 Sep 2014 15:28:39 +0000 (23:28 +0800)]
ilo: move media functions to ilo_builder_media.h
Move functions for the media pipeline to the new header.
Chia-I Wu [Fri, 12 Sep 2014 15:09:27 +0000 (23:09 +0800)]
ilo: move GPE common functions to ilo_builder_render.h
Move 3D/media common functions to the new header.
Kenneth Graunke [Fri, 12 Sep 2014 22:16:57 +0000 (15:16 -0700)]
glsl: Speed up constant folding for swizzles.
ir_rvalue::constant_expression_value() recursively walks down an IR
tree, attempting to reduce it to a single constant value. This is
useful when you want to know whether a variable has a constant
expression value at all, and if so, what it is.
The constant folding optimization pass attempts to replace rvalues with
their constant expression value from the bottom up. That way, we can
optimize subexpressions, and ideally stop as soon as we find a
non-constant subexpression.
In order to obtain the actual value of an expression, the optimization
pass calls constant_expression_value(). But it should only do so if it
knows the value can be combined into a constant. Otherwise, at each
step of walking back up the tree, it will walk down the tree again, only
to discover what it already knew: it isn't constant.
We properly avoided this call for ir_expression nodes, but not for
ir_swizzle nodes. This patch fixes that, drastically reducing compile
times on certain shaders where tree grafting has given us huge
expression trees. It also fixes SuperTuxKart.
Thanks to Iago and Mike for help in tracking this down.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78468
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Fri, 12 Sep 2014 05:07:41 +0000 (22:07 -0700)]
i965/vec4: Make type_size() return 0 for samplers.
The FS backend has always used 0, and the VS backend has always used 1.
I think 1 is just working around other problems, and is incorrect.
Samplers are baked in; nothing uses the UNIFORM register we would
create, and we shouldn't upload any constant values for them.
Fixes ES3-CTS.shaders.struct.uniform.sampler_array_vertex.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 12 Sep 2014 05:07:40 +0000 (22:07 -0700)]
i965: Skip allocating UNIFORM file storage for uniforms of size 0.
Samplers take up zero slots and therefore don't exist in the params
array, nor are they included in stage_prog_data->nr_params. There's no
need to store their size in param_size, as it's only used for dealing
with arrays of "real" uniforms (ones uploaded as shader constants).
We run into all kinds of problems trying to refer to the uniform storage
for variables that don't have uniform storage. For one, we may use some
other variable's index, or access out of bounds in arrays. In the FS
backend, our extra 2 * MaxSamplerImageUnits params for texture rectangle
rescaling paper over a lot of problems. In the VS backend, we claim
samplers take up a slot, which also papers over problems.
Instead, just skip allocating storage for variables that don't have any.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 10 Sep 2014 22:41:40 +0000 (15:41 -0700)]
i965: Separate gl_InstanceID and gl_VertexID uploading.
We always uploaded them together, mostly out of laziness - both required
an additional vertex element. However, gl_VertexID now also requires an
additional vertex buffer for storing gl_BaseVertex; for non-indirect
draws this also means uploading (a small amount of) data. This is extra
overhead we don't need if the shader only uses gl_InstanceID.
In particular, our clear shaders currently use gl_InstanceID for doing
layered clears, but don't need gl_VertexID.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 10 Sep 2014 22:41:39 +0000 (15:41 -0700)]
i965: Fix reference counting in new basevertex upload code.
In the non-indirect draw case, we call intel_upload_data to upload
gl_BaseVertex. It makes brw->draw.draw_params_bo point to the upload
buffer, and increments the upload BO reference count.
So, we need to unreference it when making brw->draw.draw_params_bo point
at something else, or else we'll retain a reference to stale upload
buffers and hold on to them forever.
This also means that the indirect case should increment the reference
count on the indirect draw buffer when making brw->draw.draw_params_bo
point at it. That way, both paths increment the reference count, so
we can safely unreference it every time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Rob Clark [Fri, 12 Sep 2014 20:52:38 +0000 (16:52 -0400)]
freedreno: "fix" problems with excessive flushes
4f338c9b introduced logic to trigger a flush rather than overflowing
cmdstream buffer. But the threshold was too low, triggering flushes
where they were not needed. This caused problems with games like
xonotic.
Part of the problem is that we need to mark all state dirty between
cmdstream submit ioctls, because we cannot rely on state being
preserved across ioctls. But even with that, there are still some
problems that are still being debugged. For now:
1) correctly mark all state dirty
2) introduce FD_MESA_DEBUG flush flag to force rendering to be flushed
between each draw, to trigger problems (so that I can debug)
3) use a more reasonable threshold so for normal usecases we don't
trigger the problems
This at least corrects the regression, but there is still more debugging
to do.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Marek Olšák [Sat, 6 Sep 2014 15:07:50 +0000 (17:07 +0200)]
r600g,radeonsi: add debug option which forces DMA for copy_region and blit
Ilia Mirkin [Thu, 11 Sep 2014 17:14:14 +0000 (13:14 -0400)]
freedreno/ir3: implement UMUL correctly
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Thu, 11 Sep 2014 14:32:55 +0000 (10:32 -0400)]
freedreno/ir3: fix UCMP handling
UCMP does not require a compare, only a select.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 10 Sep 2014 04:59:30 +0000 (00:59 -0400)]
freedreno/ir3: add TXL support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 11 Sep 2014 15:42:00 +0000 (11:42 -0400)]
freedreno/ir3: add missing put_dst
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 11 Sep 2014 15:41:12 +0000 (11:41 -0400)]
freedreno/ir3: catch incorrect usage of tmp-dst
Each get_dst() should have a matching put_dst(). Add a bit of checking
to catch mistakes.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 10 Sep 2014 02:52:56 +0000 (22:52 -0400)]
freedreno/ir3: use unsigned comparison for UIF
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 10 Sep 2014 02:52:55 +0000 (22:52 -0400)]
freedreno/ir3: negate result of USLT/etc
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 10 Sep 2014 02:52:54 +0000 (22:52 -0400)]
freedreno/ir3: add UARL support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 10 Sep 2014 02:52:53 +0000 (22:52 -0400)]
freedreno/ir3: INEG operates on src0, not src1
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 10 Sep 2014 02:52:52 +0000 (22:52 -0400)]
freedreno/ir3: fix FSLT/etc handling to return 0/-1 instead of 0/1.0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 12 Sep 2014 13:01:25 +0000 (09:01 -0400)]
freedreno/a3xx: alpha render-target shenanigans
We need the .w component to end up in .x, since the hw appears to fetch
gl_FragColor starting with the .x coordinate regardless of MRT format.
As long as we are doing this, we might as well throw out the remaining
unneeded components.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 12 Sep 2014 12:42:03 +0000 (08:42 -0400)]
util/u_format: add _is_alpha()
Because of render-to-alpha (000x) shenanigans, freedreno needs to do
some special handling when rendering to alpha-only formats. And I
noticed that while we had _is_luminance(), _is_intensity(), etc, an
_is_alpha() helper was missing. So fix that.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 10 Sep 2014 22:51:35 +0000 (18:51 -0400)]
freedreno/a3xx: format fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 10 Sep 2014 22:50:50 +0000 (18:50 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 10 Sep 2014 17:44:14 +0000 (13:44 -0400)]
freedreno/a3xx: handle rendering to layer != 0
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Brian Paul [Fri, 12 Sep 2014 12:29:04 +0000 (06:29 -0600)]
mesa: fix _mesa_free_pipeline_data() use-after-free bug
Unreference the ctx->_Shader object before we delete all the pipeline
objects in the hash table. Before, ctx->_Shader could point to freed
memory when _mesa_reference_pipeline_object(ctx, &ctx->_Shader, NULL)
was called.
Fixes crash when exiting the piglit rendezvous_by_location test on
Windows.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Connor Abbott [Sat, 6 Sep 2014 00:59:32 +0000 (20:59 -0400)]
ra: assert against unsigned underflow in q_total
q_total should never go below 0 (which is why it's defined as unsigned),
and if it does, then something is seriously wrong.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Sat, 6 Sep 2014 00:59:31 +0000 (20:59 -0400)]
ra: note a restriction in the interfence graph API
As noted in the previous commit, this was introduced in
567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q test more
efficient"), but I forgot to mention it.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Sat, 6 Sep 2014 00:59:30 +0000 (20:59 -0400)]
r300g: set register classes before interferences
In commit
567e2769b81863b6dffdac3826a6b729ce6ea37c ("ra: make the p, q
test more efficient") I unknowingly introduced a new requirement to the
register allocator API: the user must set the register class of all
nodes before setting up their interferences, because
ra_add_conflict_list() now uses the classes of the two interfering
nodes. i965 already did this, but r300g was setting up register classes
interleaved with setting up the interference graph. This led to us
calculating the wrong q total, and in certain cases
e78a01d5e6f77e075fe667a0f0ccb10d89c0dd58 (" ra: optimistically color
only one node at a time") made it so that this bug caused a segfault. In
particular, the error occurred if the q total was decremented to 1 below
0 for the last node to be pushed onto the stack. Since q_total is an
unsigned integer, it overflowed to 0xffffffff, which is what
lowest_q_total happens to be initialzed to. This means that we would
fail the "new_q_total < lowest_q_total" check on line 476 of
register_allocate.c, and so the node would never be pushed onto the
stack, which led to segfaults in ra_select() when we failed to ever give
it a register.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82828
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Pavel Ondračka <pavel.ondracka@email.cz>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Andreas Boll [Fri, 12 Sep 2014 08:11:24 +0000 (10:11 +0200)]
gallium/util: add missing u_debug include
Needed for assert.
Fixes build on BE archs with -Werror=implicit-function-declaration.
In file included from
../../../../../src/gallium/auxiliary/draw/draw_fs.c:30:0:
../../../../../src/gallium/auxiliary/util/u_math.h: In function
'util_memcpy_cpu_to_le32':
../../../../../src/gallium/auxiliary/util/u_math.h:810:4: error:
implicit declaration of function 'assert'
[-Werror=implicit-function-declaration]
assert(n % 4 == 0);
^
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Chia-I Wu [Fri, 12 Sep 2014 06:37:40 +0000 (14:37 +0800)]
ilo: fix builder size checks for BLT buffer clear/copy
In buf_clear_region() and buf_copy_region(), max_cmd_size was set to 0. If
either of the functions is called and there is not enough space in the
builder, the next ilo_cp_flush() will fail silently in a release build.
Replace magic numbers by size defines in tex_clear_region()/tex_copy_region()
for consistency and readability.
Chia-I Wu [Fri, 12 Sep 2014 04:20:31 +0000 (12:20 +0800)]
ilo: reduce BLT function parameters
Intruduce gen6_blt_bo and gen6_blt_xy_bo to describe BOs. In the extreme case
of gen6_XY_SRC_COPY_BLT(), the number of parameters goes down from 18 to 8.
Chia-I Wu [Fri, 12 Sep 2014 03:54:36 +0000 (11:54 +0800)]
ilo: clean up BLT functions
Follow the changes for MI functions, but for BLT this time.
Chia-I Wu [Fri, 12 Sep 2014 03:20:55 +0000 (11:20 +0800)]
ilo: clean up MI functions
With ilo_builder in place, some conventions we had to build commands are no
longer needed.
Chia-I Wu [Fri, 12 Sep 2014 03:47:04 +0000 (11:47 +0800)]
ilo: move BLT functions to ilo_builder_blt.h
Follow the changes for MI functions, but for BLT this time.
Chia-I Wu [Fri, 12 Sep 2014 03:11:47 +0000 (11:11 +0800)]
ilo: move MI functions to ilo_builder_mi.h
Have a centralized place for MI functions, and remove the duplicated
gen6_MI_LOAD_REGISTER_IMM().
Chia-I Wu [Fri, 12 Sep 2014 03:06:39 +0000 (11:06 +0800)]
ilo: add ILO_DEV_ASSERT()
It replaces ILO_GPE_VALID_GEN().
Chia-I Wu [Fri, 12 Sep 2014 02:55:58 +0000 (10:55 +0800)]
ilo: use an accessor for dev->gen
It should enable us to do specialized builds by making the accessor return a
constant.
Chia-I Wu [Fri, 12 Sep 2014 02:08:31 +0000 (10:08 +0800)]
ilo: add GEN_EXTRACT() and GEN_SHIFT32()
They replace READ() and SET_FIELD() that we have been using.
Chia-I Wu [Fri, 12 Sep 2014 02:43:42 +0000 (10:43 +0800)]
ilo: remove ILO_GEN_GET_MAJOR()
The last user has gone away.
Chia-I Wu [Fri, 12 Sep 2014 08:53:48 +0000 (16:53 +0800)]
ilo: careful with empty fb state in ilo_gpe_set_fb()
We cannot pass 0 as the width or height to ilo_gpe_init_view_surface_null().
Ilia Mirkin [Thu, 21 Aug 2014 00:19:38 +0000 (20:19 -0400)]
nv50,nvc0: enable ARB_texture_view
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 20 Aug 2014 06:12:10 +0000 (02:12 -0400)]
mesa/st: add ARB_texture_view support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Ilia Mirkin [Wed, 20 Aug 2014 23:45:10 +0000 (19:45 -0400)]
gallium: add a texture target to sampler view and a CAP to use it
This allows a sampler view to have a different texture target than the
underlying resource. This will be used to implement the type casting
between 2d arrays and cube maps as specified in ARB_texture_view.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sat, 16 Aug 2014 16:48:09 +0000 (12:48 -0400)]
nouveau: only enable stencil func if the visual has stencil bits
The _Enabled property already has the relevant information.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Fri, 15 Aug 2014 05:25:06 +0000 (01:25 -0400)]
nouveau: only enable the depth test if there actually is a depth buffer
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Maarten Lankhorst [Wed, 10 Sep 2014 15:06:34 +0000 (17:06 +0200)]
nouveau: remove unneeded assert
No idea why it was added, but the code runs fine even on videos
where it triggers.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Maarten Lankhorst [Wed, 10 Sep 2014 11:20:53 +0000 (13:20 +0200)]
nouveau: rework reference frame handling
Fixes a regression from "nouveau/vdec: small fixes to h264 handling"
New picking order for frames:
1. Vidbuf pointer matches.
2. Take the first kicked ref.
3. If that fails, take a ref that has a different last_used.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Maarten Lankhorst [Wed, 10 Sep 2014 11:18:54 +0000 (13:18 +0200)]
nouveau: fix MPEG4 hw decoding
Reorder some fields to make I-frame decoding work correctly.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Maarten Lankhorst [Wed, 10 Sep 2014 11:17:13 +0000 (13:17 +0200)]
nouveau: re-allocate bo's on overflow
The BSP bo might be too small to contain all of the bsp data,
bump its size on overflow. Also bump inter_bo when this happens,
it might be too small otherwise.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Chia-I Wu [Fri, 12 Sep 2014 01:44:44 +0000 (09:44 +0800)]
ilo: fix a compile error with -Werror=format-security
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83777
Ian Romanick [Thu, 11 Sep 2014 00:57:54 +0000 (17:57 -0700)]
i965/vec4: Only examine virtual_grf_end for GRF sources
If the source is not a GRF, it could have a register >= virtual_grf_count.
Accessing virtual_grf_end with such a register would lead to
out-of-bounds access. Make sure the source is a GRF before accessing
virtual_grf_end.
Fixes Valgrind complaints while compiling some shaders.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Brian Paul [Tue, 9 Sep 2014 15:56:47 +0000 (09:56 -0600)]
st/mesa: handle failed context creation for core profile
If the glx/wgl state tracker requested a core profile but the gallium
driver did not support some feature of GL 3.1 or later, we were setting
ctx->Version=0 and then failing the assertion in
_mesa_initialize_exec_table().
With this change we check for ctx->Version=0 and tear down the context
and return NULL from st_create_context().
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Iago Toral Quiroga [Wed, 10 Sep 2014 08:16:13 +0000 (10:16 +0200)]
i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.
So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage.
From ARB_transform_feedback3:
"When a generated primitive query for a vertex stream is active, the
primitives-generated count is incremented every time a primitive emitted to
that stream reaches the Discarding Rasterization stage (see Section 3.x)
right before rasterization. This counter is incremented whether or not
transform feedback is active."
Unfortunately, we don't have any registers that provide the number of primitives
written to a specific stream other than the ones that track the number of
primitives written to transform feedback in the SOL stage, so we can't
implement this exactly as specified.
In the past we implemented this feature by activating the SOL unit even if
transform feeback was disabled, but making it so that all buffers were
disabled and it only recorded statistics, which gave us the right semantics
(see
3178d2474ae5bdd1102fb3d76a60d1d63c961ff5). Unfortunately, this came with
a significant performance impact and had to be reverted.
This new take does not intend to implement the exact semantics required by
the spec, but improves what we have now, since now we return the primitive
count for stream 0 in all cases. With this patch we use
GEN7_SO_PRIM_STORAGE_NEEDED to resolve GL_PRIMITIVES_GENERATED queries
for non-zero streams. This would return the number of primitives written
to transform feedback for each stream instead. Since non-zero streams are
only useful in combination with transform feedback this should not be too
bad, and the only case that I think we would not be supporting would be
the one in which we want to use both GL_PRIMITIVES_GENERATED and
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN on the same non-zero stream to
detect buffer overflow.
This patch also fixes the following piglit test:
arb_gpu_shader5-xfb-streams-without-invocations
This test uses both GL_PRIMITIVES_GENERATED and
GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries on non-zero streams, but it
does never hit the overflow case, so both queries are always expected to return
the same value.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Christian König [Thu, 11 Sep 2014 07:50:00 +0000 (09:50 +0200)]
radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffers
That better matches the actual userspace use case, the
kernel will force it to VRAM if the hardware requires it.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Christian König [Thu, 11 Sep 2014 07:38:50 +0000 (09:38 +0200)]
radeon/video: use the hw to initial clear the buffers
Less CPU overhead and avoids contention over CPU accessible memory on startup.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Christian König [Thu, 11 Sep 2014 07:29:28 +0000 (09:29 +0200)]
radeon/video: use more of the common buffer code v2
In preparation to using buffers clears with the hw engine(s).
v2: split out flipping to using hw buffer clears.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>