[InstCombine] simplify getBinOpsForFactorization(); NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330129 91177308-0d34-0410-b5e6-96231b3b80d8

SmallVectorMemoryBuffer: Fix some comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330128 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] simplify fneg+fadd folds; NFC

Two cleanups:
1. As noted in D45453, we had tests that don't need FMF that were misplaced in the 'fast-math.ll' test file.
2. This removes the final uses of dyn_castFNegVal, so that can be deleted. We use 'match' now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330126 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] fix formatting; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330124 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32

See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356

Differential Revision: https://reviews.llvm.org/D45446

Reviewers: artem.tamazov, arsenm, timcorringham

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330123 91177308-0d34-0410-b5e6-96231b3b80d8

[test] Avoid spurious failure in debug-names-find.s. NFC.

Have llvm-dwarfdump take input from stdin to avoid leaking the host paths into
the tests, causing nondeterministic failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330121 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) load instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330120 91177308-0d34-0410-b5e6-96231b3b80d8

[LatencyPriorityQueue] Fix build: missing override

[10/260] Building CXX object lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/PostRASchedulerList.cpp.o
FAILED: lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/PostRASchedulerList.cpp.o
/usr/local/bin/clang++  -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/CodeGen -I/build/llvm/lib/CodeGen -I/usr/include/libxml2 -Iinclude -I/build/llvm/include -g0 -fPIC -fvisibility-inlines-hidden -Werror -Werror=date-time -Werror=unguarded-availability-new -std=c++11 -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fcolor-diagnostics -ffunction-sections -fdata-sections -O3 -g0  -fPIC   -UNDEBUG  -fno-exceptions -fno-rtti -MD -MT lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/PostRASchedulerList.cpp.o -MF lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/PostRASchedulerList.cpp.o.d -o lib/CodeGen/CMakeFiles/LLVMCodeGen.dir/PostRASchedulerList.cpp.o -c /build/llvm/lib/CodeGen/PostRASchedulerList.cpp
In file included from /build/llvm/lib/CodeGen/PostRASchedulerList.cpp:26:
/build/llvm/include/llvm/CodeGen/LatencyPriorityQueue.h:87:27: error: 'dump' overrides a member function but is not marked 'override' [-Werror,-Winconsistent-missing-override]
    LLVM_DUMP_METHOD void dump(ScheduleDAG *DAG) const {
                          ^
/build/llvm/include/llvm/CodeGen/ScheduleDAG.h:547:18: note: overridden virtual function is here
    virtual void dump(ScheduleDAG *) const {}
                 ^
1 error generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330119 91177308-0d34-0410-b5e6-96231b3b80d8

[LatencyPriorityQueue] The LatencyPriorityQueue class is missing the implementation for the dump function

Added implementation of the dump function for LatencyPriorityQueue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330117 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) load instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330116 91177308-0d34-0410-b5e6-96231b3b80d8

[MIR-Canon] Fixing a test failure caused by COPY Folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330115 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Restrict certain trap instructions for micromipsr6

Instructions removed from micromipsr6:
teqi, tgei, tgeiu, tlti, tltiu, tnei

Differential Revision: https://reviews.llvm.org/D45318

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330114 91177308-0d34-0410-b5e6-96231b3b80d8

[MIR-Canon] Adding ISA-Agnostic COPY Folding.

Transforms the following:

    %vreg1234:gpr32 = COPY %42
    %vreg1235:gpr32 = COPY %vreg1234
    %vreg1236:gpr32 = COPY %vreg1235
    $w0 = COPY %vreg1236

into:

    $w0 = COPY %42

Assuming %42 is also a gpr32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330113 91177308-0d34-0410-b5e6-96231b3b80d8

[NFC][MIR-Canon] clang-format cleanup of Mir Canonicalizer Pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330111 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Introduce archs: goldmont-plus & tremont

Using Goldmont's cost tables for these two upcoming
atom archs.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45612

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330109 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for structured LD2 (scalar+imm) load instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330108 91177308-0d34-0410-b5e6-96231b3b80d8

Rename ObjectMemoryBuffer to SmallVectorMemoryBuffer; NFCI

Summary: As discussed in https://reviews.llvm.org/D45606, it makes more sense to name the class as SmallVectorMemoryBuffer

Reviewers: bkramer, dblaikie

Reviewed By: dblaikie

Subscribers: mehdi_amini, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330107 91177308-0d34-0410-b5e6-96231b3b80d8

[BasicAA] Return MayAlias for the pointer plus variable offset to
structure object member

Differential Revision: https://reviews.llvm.org/D45510

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330106 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Use APInt::isSubsetof instead of APInt::intersects to avoid a negation of an APInt value. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330105 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Use uint32_t instead of unsigned in GetLo32XForm for readability. NFC

GetLo8XForm right next to it uses uint8_t so uint32_t is consistent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330104 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] Simplify 'xor' to 'or' if no common bits are set.

Summary:
In order to get the whole fold as specified in [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]],
let's first handle the simple straight-forward things.
Let's start with the `and` -> `or` simplification.

The one obvious thing missing here: the constant mask is not handled.
I have an idea how to handle it, but it will require some thinking,
and is not strictly required here, so i've left that for later.

https://rise4fun.com/Alive/Pkmg

Reviewers: spatel, craig.topper, eli.friedman, jingyue

Reviewed By: spatel

Subscribers: llvm-commits

Was reviewed as part of https://reviews.llvm.org/D45631

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330103 91177308-0d34-0410-b5e6-96231b3b80d8

[SelectionDAG][NFC] haveNoCommonBitsSet(): add FIXME notes

As suggested in https://reviews.llvm.org/D45631#1068338

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330102 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] Simplify 'add' to 'or' if no common bits are set.

Summary:
In order to get the whole fold as specified in [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]],
let's first handle the simple straight-forward things.
Let's start with the `and` -> `or` simplification.

The one obvious thing missing here: the constant mask is not handled.
I have an idea how to handle it, but it will require some thinking,
and is not strictly required here, so i've left that for later.

https://rise4fun.com/Alive/Pkmg

Reviewers: spatel, craig.topper, eli.friedman, jingyue

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45631

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330101 91177308-0d34-0410-b5e6-96231b3b80d8

[NFC] ConstantOffsetExtractor::CanTraceInto(): add FIXME: no tests

As suggested in https://reviews.llvm.org/D45631#1068338,
looking at haveNoCommonBitsSet() users, and *trying* to
show the change effect elsewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330100 91177308-0d34-0410-b5e6-96231b3b80d8

[MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel.

TargetSchedModel now always delegates to MCSchedModel the computation of
instruction latency and reciprocal throughput.
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330099 91177308-0d34-0410-b5e6-96231b3b80d8

[DAGCombiner, PowerPC] allow X - (fpext(-Y) --> X + fpext(Y) with multiple uses

This is a transform that I limited in instcombine in rL329821 because it was
creating more instructions in IR when the cast has multiple uses.

But if the cast is free, then we can do the transform regardless of other
uses because it improves the potential throughput of the calculation by
removing a dependency on the fneg.

Differential Revision: https://reviews.llvm.org/D45598

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330098 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] simplify more code for distributive property; NFCI

Also, fix capitalization to current style. Follow-up to:
rL330096

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330097 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] simplify code for distributive property; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330096 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Extend WithColor helpers

Although printing warnings and errors to stderr is by far the most
common case, this patch makes it possible to specify any stream.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330094 91177308-0d34-0410-b5e6-96231b3b80d8

NFC: Move ObjectMemoryBuffer to support

Summary:
Since the class is used by both MCJIT and LTO, it makes more sense to move it to Support lib.
This is a follow up patch to r329929 and https://reviews.llvm.org/D45244

Reviewers: bkramer, dblaikie

Reviewed By: bkramer

Subscribers: mehdi_amini, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45606

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330093 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo] Use WithColor to print errors/warnings

Use the convenience methods from WithColor to consistently print errors
and warnings in libDebugInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330092 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Add convenience functions to WithColor. NFC.

Create convenience functions for printing error, warning and note to
stdout. Previously we had similar functions being used in dsymutil, but
given that this pattern is so common it makes sense to make it available
globally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330091 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Tests for unsigned saturation downconvert detection.

One more test for smax(smin(x, C2), C1) pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330090 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] Enable Add/Sub simplifications with only 'reassoc' FMF

These simplifications were previously enabled only with isFast(), but that
is more restrictive than required. Since r317488, FMF has 'reassoc' to
control these cases at a finer level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330089 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Tests for unsigned saturation downconvert detection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330088 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine] add shift+logic tests (PR37098); NFC

It debateable whether instcombine should be in the business of
reassociation, but it is currently.

These tests and PR37098 demonstrate a missing ability to do a
simple reassociation that allows eliminating shifts.

If we decide that functionality belongs somewhere else, then we
should still have some tests to show that we've intentionally
limited instcombine to *not* include this ability.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330086 91177308-0d34-0410-b5e6-96231b3b80d8

[X86][MMX] Set PAVG/PHADD/PMIN/PMAX/PSIGN instructions to use same scheduler classes as SSE/AVX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330085 91177308-0d34-0410-b5e6-96231b3b80d8

[NFC] fix trivial typos in document and comments

"not not" -> "not" etc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330083 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU] Add gfx902 product names

Differential Revision: https://reviews.llvm.org/D45609

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330081 91177308-0d34-0410-b5e6-96231b3b80d8

[WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() call

Summary:
InsertPos is within the bacic block `Header`, so `findDebugLoc()` should
be called on not `MBB` but `Header` instead.

Reviewers: yurydelendik

Subscribers: jfb, dschuff, aprantl, sbc100, jgravelle-google, sunfish, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330079 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Add the bizarro movsww and movzww mnemonics for the disassembler.

The destination size of the movzx/movsx instruction is controlled by the normal operand size mechanisms. Only the input type is fixed.

This means that a 0x66 prefix on the encoding for zext/sext 16->32 should really produce a 16->16 instruction. Functionally this is equivalent to a GR16->GR16 move since bits 16 and above will be preserved. So nothing is actually extended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330078 91177308-0d34-0410-b5e6-96231b3b80d8

MachO: trap unreachable instructions

Debugability is more important than saving 4 bytes to let us to fall
through to nonense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330073 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] masked-merge: add 'and' tests, too.

(and plain 'or', for completeness sake.)

After submitting D45631, i have realized that it will *already*
affect 'and' pattern, and it was obvious that there were no
good test patterns to show that.

Since the masked-merge.ll is getting kinda big,
unify naming schemes a bit, and split into 'xor'/'and'/'or'
testfiles, with the only difference being the last operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330072 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI duplication bugs of CloneModule"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330070 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo][OPT] Fixing a couple of DI duplication bugs of CloneModule

As demonstrated by the regression tests added in this patch, the
following cases are valid cases:

1. A Function with no DISubprogram attached, but various debug info
  related to its instructions, coming, for instance, from an inlined
  function, also defined somewhere else in the same module;
2. ... or coming exclusively from the functions inlined and eliminated
  from the module entirely.

The ValueMap shared between CloneFunctionInto calls within CloneModule
needs to contain identity mappings for all of the DISubprogram's to
prevent them from being duplicated by MapMetadata / RemapInstruction
calls, this is achieved via DebugInfoFinder collecting all the
DISubprogram's. However, CloneFunctionInto was missing calls into
DebugInfoFinder for functions w/o DISubprogram's attached, but still
referring DISubprogram's from within (case 1). This patch fixes that.

The fix above, however, exposes another issue: if a module contains a
DISubprogram referenced only indirectly from other debug info
metadata, but not attached to any Function defined within the module
(case 2), cloning such a module causes a DICompileUnit duplication: it
will be moved in indirecty via a DISubprogram by DebugInfoFinder first
(because of the first bug fix described above), without being
self-mapped within the shared ValueMap, and then will be copied during
named metadata cloning. So this patch makes sure DebugInfoFinder
visits DICompileUnit's referenced from DISubprogram's as it goes w/o
re-processing llvm.dbg.cu list over and over again for every function
cloned, and makes sure that CloneFunctionInto self-maps
DICompileUnit's referenced from the entire function, not just its own
DISubprogram attached that may also be missing.

The most convenient way of tesing CloneModule I found is to rely on
CloneModule call from `opt -run-twice`, instead of writing tedious
unit tests. That feature has a couple of properties that makes it hard
to use for this purpose though:

1. CloneModule doesn't copy source filename, making `opt -run-twice`
  report it as a difference.
2. `opt -run-twice` does the second run on the original module, not
  its clone, making the result of cloning completely invisible in opt's
  actual output with and without `-run-twice` both, which directly
  contradicts `opt -run-twice`s own error message.

This patch fixes this as well.

Reviewed By: aprantl

Reviewers: loladiro, GorNishanov, espindola, echristo, dexonsmith

Subscribers: vsk, debug-info, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D45593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330069 91177308-0d34-0410-b5e6-96231b3b80d8

[Hexagon] Initial instruction cost model for auto-vectorization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330065 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r329956, "AArch64: Introduce a DAG combine for folding offsets into addresses."

Caused a hang and eventually an assertion failure in LTO builds
of 7zip-benchmark on aarch64 iOS targets.
http://green.lab.llvm.org/green/job/lnt-ctmark-aarch64-O3-flto/2024/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330063 91177308-0d34-0410-b5e6-96231b3b80d8

[LV] Introduce TTI::getMinimumVF

The function getMinimumVF(ElemWidth) will return the minimum VF for
a vector with elements of size ElemWidth bits. This value will only
apply to targets for which TTI::shouldMaximizeVectorBandwidth returns
true. The value of 0 indicates that there is no minimum VF.

Differential Revision: https://reviews.llvm.org/D45271

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330062 91177308-0d34-0410-b5e6-96231b3b80d8

[DebugInfo] Change std::sort to llvm::sort in response to r327219

r327219 added wrappers to std::sort which randomly shuffle the container before
sorting.  This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort.  Refer the comments section in D44363 for a list of all the
required patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330061 91177308-0d34-0410-b5e6-96231b3b80d8

[Power9] Add the TLS store instructions to the Power 9 model

The Power 9 scheduler model should now include the TLS instructions.
We can now, once again, mark the model as complete.
From now on, if instructions are added to Power 9 but are not
added to the model the build should produce an error. Hopefully
that will alert the developer who is adding new instructions
that they should also be added to the scheulder model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330060 91177308-0d34-0410-b5e6-96231b3b80d8

[Transforms] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: kcc, pcc, danielcdh, jmolloy, sanjoy, dberlin, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45142

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330059 91177308-0d34-0410-b5e6-96231b3b80d8

[MC] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: grosbach, void, ruiu

Reviewed By: ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330058 91177308-0d34-0410-b5e6-96231b3b80d8

[ProfileData] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: bogner, vsk, eraman, ruiu

Reviewed By: ruiu

Subscribers: ruiu, llvm-commits

Differential Revision: https://reviews.llvm.org/D45139

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330057 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Add some specific cpu targets to the cost models

We're mostly testing with generic isa attributes, but PR36550 will require testing of specific target's scheduler models as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330056 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Split fma arith costs tests from other fp tests

Was proving cumbersome to test with/without fma

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330054 91177308-0d34-0410-b5e6-96231b3b80d8

[LTO] Change std::sort to llvm::sort in response to r327219

Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.

Reviewers: pcc, mehdi_amini, ruiu

Reviewed By: ruiu

Subscribers: ruiu, inglorion, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D45137

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330053 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Regenerate latency/codesize cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330052 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Regenerate cast conversion cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330051 91177308-0d34-0410-b5e6-96231b3b80d8

[CostModel][X86] Regenerate masked intrinsic cost tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330050 91177308-0d34-0410-b5e6-96231b3b80d8

Define InitLLVM to do common initialization all at once.

We have a few functions that virtually all command wants to run on
process startup/shutdown. This patch adds InitLLVM class to do that
all at once, so that we don't need to copy-n-paste boilerplate code
to each llvm command's main() function.

Differential Revision: https://reviews.llvm.org/D45602

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330046 91177308-0d34-0410-b5e6-96231b3b80d8

hwasan: add -fsanitize=kernel-hwaddress flag

This patch adds -fsanitize=kernel-hwaddress flag, that essentially enables
-hwasan-kernel=1 -hwasan-recover=1 -hwasan-match-all-tag=0xff.

Differential Revision: https://reviews.llvm.org/D45046

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330044 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] masked-merge: commutativity tests: ensure the ordering.

This was intended since initially, but i did not really think
about it, and did not know how to force that. Now that the
xor->or fold is working (patch upcoming), this came up
to improve the test coverage.

A followup for rL330003, rL330007
https://bugs.llvm.org/show_bug.cgi?id=6773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330039 91177308-0d34-0410-b5e6-96231b3b80d8

Add PPC64_GLINK dynamic tag.

Add support for the PPC64_GLINK dynamic tag which is used in the ElfV2 abi.

Differential Revision: https://reviews.llvm.org/D45574

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330038 91177308-0d34-0410-b5e6-96231b3b80d8

[mips] Materialize constants for multiplication

Previously, the MIPS backend would alwyas break down constant multiplications
into a series of shifts, adds, and subs. This patch changes that so the cost of
doing so is estimated.

The cost is estimated against worst case constant materialization and retrieving
the results from the HI/LO registers.

For cases where the value type of the multiplication is not legal, the cost of
legalization is estimated and is accounted for before performing the
optimization of breaking down the constant

This resolves PR36884.

Thanks to npl for reporting the issue!

Reviewers: abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D45316

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330037 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove remaining itinerary support from instructions and target (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330035 91177308-0d34-0410-b5e6-96231b3b80d8

[ARM] FP16 vmaxnm/vminnm scalar instructions

This adds code generation support for the FP16 vmaxnm/vminnm scalar
instructions.

Differential Revision: https://reviews.llvm.org/D44675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330034 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r330027: "[llvm-exegesis] re-enable failing tests after r330026."

The tests are still failing on some bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330033 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-mca] Ensure that instructions with a schedule read-advance are always issued in the right order.

Normally, the Scheduler prioritizes older instructions over younger instructions
during the instruction issue stage. In one particular case where a dependent
instruction had a schedule read-advance associated to one of the input operands,
this rule was not correctly applied.

This patch fixes the issue and adds a test to verify that we don't regress that
particular case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330032 91177308-0d34-0410-b5e6-96231b3b80d8

[ARC] Add LImm support for J/JL

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330031 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Generalize X86FixupLEAs to work with TargetSchedModel

Similar to rL329834, don't rely on itinerary scheduler model to determine latencies for LEA thresholds, use the generic TargetSchedModel::computeInstrLatency call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330030 91177308-0d34-0410-b5e6-96231b3b80d8

[profile] Fix binary format reader error propagation.

Summary:
This was originally part of rL328132, and led to the discovery
of the issues addressed in rL328987. Re-landing.

Reviewers: xur, davidxl, bkramer

Reviewed By: bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45545

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330029 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] re-enable failing tests after r330026.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330027 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] Fix use after free.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D45625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330026 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comment reference to itineraries. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330025 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45618

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330024 91177308-0d34-0410-b5e6-96231b3b80d8

[X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not WriteFAdd

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330023 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330022 91177308-0d34-0410-b5e6-96231b3b80d8

Remove comment references to itineraries. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330021 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis][NFC] Add more logging in case target creation fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330020 91177308-0d34-0410-b5e6-96231b3b80d8

Remove out of data comment. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330019 91177308-0d34-0410-b5e6-96231b3b80d8

[PostRASink]Add register dependency check for implicit operands

Summary:
This change extend the register dependency check for implicit operands in Copy instructions.
Fixes PR36902.

Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB

Reviewed By: thegameg

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330018 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] Regenerate logical-select.ll test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330017 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] Create test files in temporary directory.

Currently the test fails in sandboxed environnements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330015 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.

Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: rengolin

Subscribers: tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D45432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330014 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330013 91177308-0d34-0410-b5e6-96231b3b80d8

[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction

Differential Revision: https://reviews.llvm.org/D45514

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330011 91177308-0d34-0410-b5e6-96231b3b80d8

Partially revert r330008.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330010 91177308-0d34-0410-b5e6-96231b3b80d8

[llvm-exegesis] Run unit tests on more platforms.

Summary:
 - Target-independent tests are run all the time.
 - Tests that codegen X86 code are run when X86 is in build targets.
 - Tests that run X86 jitted code are run only on X86 hosts.

Reviewers: gchatelet

Subscribers: mgorny, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D45614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330008 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] Add last few tests with constant mask for masked merge folding.

A followup for rL330003
https://bugs.llvm.org/show_bug.cgi?id=6773

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330007 91177308-0d34-0410-b5e6-96231b3b80d8

[NFC] fix trivial typos in comments

"the the" -> "the", "we we" -> "we", etc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine][NFC] Add tests for masked merge folding.

https://bugs.llvm.org/show_bug.cgi?id=6773

As discussed there, some backends may want to undo this fold
(x86+bmi for scalars, x86+sse for vectors, ...)
https://bugs.llvm.org/show_bug.cgi?id=37104

https://rise4fun.com/Alive/JXt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330003 91177308-0d34-0410-b5e6-96231b3b80d8

[InstCombine]: foldSelectICmpAndAnd(): and is commutative

Summary:
The fold added in D45108 did not account for the fact that
the and instruction is commutative, and if the mask is a variable,
the mask variable and the fold variable may be swapped.

I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]]

This extends/generalizes that fold, so it is handled too.

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45539

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330001 91177308-0d34-0410-b5e6-96231b3b80d8

[AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.

Summary:
Added Z_(b|h|s|d) vector list RegisterOperands along with support to
add/print the vector lists.

This is patch [5/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro

Reviewed By: fhahn

Subscribers: tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45431

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330000 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Introduce cldemote instruction

Hint to hardware to move the cache line containing the
address to a more distant level of the cache without
writing back to memory.

Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329992 91177308-0d34-0410-b5e6-96231b3b80d8

[Support] Fix building for Windows on ARM

The commit in SVN r310001 that added support for this actually didn't
use the right struct field for the frame pointer - for ARM, there is
no register named Fp in the CONTEXT struct. On Windows, the R11
register is used as frame pointer.

Differential Revision: https://reviews.llvm.org/D45590

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329991 91177308-0d34-0410-b5e6-96231b3b80d8

[X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.

This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics.

We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329990 91177308-0d34-0410-b5e6-96231b3b80d8

Enable debug fission for thinLTO linked via gold-plugin

Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user.

Reviewers: tejohnson, pcc, dblaikie

Reviewed By: pcc

Subscribers: JDevlieghere, mehdi_amini, inglorion

Differential Revision: https://reviews.llvm.org/D44792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329988 91177308-0d34-0410-b5e6-96231b3b80d8

[CallSiteSplit] Fix comment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329987 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another bot failure from r329951.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329986 91177308-0d34-0410-b5e6-96231b3b80d8

[AMDGPU] Update relocation record description

Document which relocation records are static and dynamic.

Differential Revision: https://reviews.llvm.org/D45587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329981 91177308-0d34-0410-b5e6-96231b3b80d8