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Samuel Pitoiset [Fri, 12 Oct 2018 12:04:39 +0000 (14:04 +0200)]
radv: do not support blitting surfaces for R32G32B32 formats
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jose Fonseca [Tue, 9 Oct 2018 15:46:21 +0000 (16:46 +0100)]
scons: Allow building with custom MSVC_USE_SCRIPT script.
SCons MSVC support relies on vcvarsall.bat to extract the PATH, CPP
includes, library paths, etc.
And SCons also has an build env var named MSVC_USE_SCRIPT which one can
use to point to alternative vcvarsall.bat script.
This change exposes this MSVC_USE_SCRIPT build env variable as a SCons
command line variable. This will enable using MSVC outside Program
Files (e.g, network shares, etc.)
This change also links advapi32 library, necessary for the Windows
Registry API used by WGL state tracker, avoiding missing symbols.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Samuel Pitoiset [Wed, 3 Oct 2018 21:06:34 +0000 (23:06 +0200)]
radv: emit the GLC bit for SSBO loads/stores when needed
This fixes some new memory model tests:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108112
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 10 Oct 2018 08:42:19 +0000 (10:42 +0200)]
spirv/nir: handle memory access qualifiers for SSBO loads/stores
v2: - change how the access qualifiers are accumulated
v3: - duplicate members in struct_member_decoration_cb()
- handle access qualifiers on variables
- remove access qualifiers handling in _vtn_variable_load_store()
- fix setting access qualifiers on type->array_element
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net
Tapani Pälli [Wed, 3 Oct 2018 10:46:42 +0000 (13:46 +0300)]
anv/android: we need git_sha1.h in include paths
Fixes:
e4538b9 "anv: Implement VK_KHR_driver_properties"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Nanley Chery [Thu, 11 Oct 2018 23:31:08 +0000 (16:31 -0700)]
anv: Clear WM_HZ_OP overrides in init_device_state
This is basically a port of commit,
3ade766684933ac84e41634429fb693f85353c11
("i965: Disable 3DSTATE_WM_HZ_OP fields.")
The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in
the section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
Clear." It mentions that the packet overrides GPU state for the clear
operation and needs to be reset to 0s to clear the overrides. Depending
on the kernel, we may not get a context with the GPU state for this
packet zeroed. Do it ourselves just in case.
Prevents a number of GPU hangs when running crucible on ICL. I tried to
get the exact number of hangs that occurs without this patch, but was
unsuccessful. The test machine became unresponsive before completing the
full run.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 10 Oct 2018 09:31:00 +0000 (02:31 -0700)]
i965/gen10+: Initialize new fields in STATE_BASE_ADDRESS
Ref:
263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake."
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Jordan Justen [Wed, 28 Mar 2018 08:29:18 +0000 (01:29 -0700)]
anv/gen9+: Initialize new fields in STATE_BASE_ADDRESS
Ref:
263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake."
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Jason Ekstrand [Thu, 11 Oct 2018 03:36:52 +0000 (22:36 -0500)]
nir: Add a bunch of b2[if] optimizations
The b2f and b2i conversions always produce zero or one which are both
representable in every type and size. Since b2i and b2f support all bit
sizes, we can just get rid of the conversion opcode.
total instructions in shared programs:
15089335 ->
15084368 (-0.03%)
instructions in affected programs: 212564 -> 207597 (-2.34%)
helped: 896
HURT: 0
total cycles in shared programs:
369831123 ->
369826267 (<.01%)
cycles in affected programs:
2008647 ->
2003791 (-0.24%)
helped: 693
HURT: 216
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Thu, 11 Oct 2018 03:04:17 +0000 (22:04 -0500)]
intel/vec4: Fix nir_op_b2[fi] with 64-bit result
This is valid NIR but you can't actually hit this case today. GLSL IR
doesn't have a bool to double opcode; it does f2d(b2f(x)). In SPIR-V we
don't have any to/from bool conversion opcodes at all. However, the
next commit will make us start generating it so we should be ready.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Wed, 10 Oct 2018 22:17:11 +0000 (15:17 -0700)]
intel/fs: Fix nir_op_b2[fi] with 64-bit result on Gen8 LP and Gen9 LP
Several of the Atom GPUs have additional restrictions on alignment when
moving < 64-bit source to a 64-bit destination. All of the nir_op_*2*64
code generation paths respected this, but nir_op_b2[fi] did not.
Previous to commit
a68dd47b911 it was not possible to generate such an
instruction from the GLSL path. It may have been possible from SPIR-V,
but it's not clear. The aforementioned patch converts a 64-bit
nir_op_fsign into a sequence of operations including a nir_op_b2f with a
64-bit result. This "just works" everywhere except these Atom parts.
This problem was not detected during normal CI testing because the Atom
parts are not included in developer builds.
v2 (idr): Make the patch compile, and make some cosmetic changes. Add a
commit message.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108319
Fixes:
a68dd47b911 "nir/algebraic: Simplify fsat of fsign"
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Vinson Lee [Wed, 3 Oct 2018 21:56:26 +0000 (14:56 -0700)]
egl: Use correct shared libraries suffix on macOS.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Illia Iorin [Thu, 11 Oct 2018 15:06:18 +0000 (18:06 +0300)]
mesa: Fix pack_uint_Z_FLOAT32()
Fixed pack_uint_Z_FLOAT32 by casting row data to float instead uint.
Remove code duplicate function pack_uint_Z_FLOAT32_X24S8.
Edited case in "_mesa_get_pack_uint_z_func".
Now it looks like "_mesa_get_pack_float_z_func".
Remove _mesa_problem call, which was added for debuging this issue.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91433
Signed-off-by: Illia Iorin <illia.iorin@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Rodrigo Vivi [Thu, 30 Aug 2018 21:39:57 +0000 (14:39 -0700)]
intel: Introducing Whiskey Lake platform
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.
This follows the ids and approach used on kernel's commit
b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
and commit
c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")
v2: Lionel noticed that GT{1,2,3} on kernel wasn't following
spec when looking to number of EUs, so kernel has been updated.
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Boyuan Zhang [Wed, 10 Oct 2018 19:08:44 +0000 (15:08 -0400)]
st/va: use provided sizes and coords for vlVaGetImage
vlVaGetImage should respect the width, height, and coordinates x and y that
passed in. Therefore, pipe_box should be created with the passed in values
instead of surface width/height.
v2: add input size check, return error when size out of bounds
v3: fix the size check for vaimage
v4: add size adjustment for x and y coordinates
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Christian König <christian.koenig@amd.com>
Samuel Pitoiset [Tue, 9 Oct 2018 10:26:42 +0000 (12:26 +0200)]
radv: implement clear operations for R32G32B32
This fixes crashes for some CTS:
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.linear_*_*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.*.*_linear_*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108113
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 8 Oct 2018 12:40:17 +0000 (14:40 +0200)]
radv: disallow 3D images and mipmaps/layers for R32G32B32 linear formats
R32G32B32 are weird formats and we are only going to support
some basic operations for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 10 Oct 2018 12:04:42 +0000 (14:04 +0200)]
radv: add a workaround for a VGT hang with prim restart and strips
Otherwise, Yakuza and The Evil Within hang the GPU with DXVK.
This apparently only works on Polaris.
Suggested by Marek.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Thu, 11 Oct 2018 00:25:08 +0000 (11:25 +1100)]
glsl: remove redundant es_shader checks
The es check is already covered by the is_version() check.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dave Airlie [Fri, 5 Oct 2018 00:52:51 +0000 (10:52 +1000)]
st/glsl_to_tgsi: initialise need_uarl in contructor
Found by coverity
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Thu, 4 Oct 2018 23:20:09 +0000 (09:20 +1000)]
glspirv: drop pointless assert (size_t is unsigned)
Found by coverity
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Dave Airlie [Thu, 4 Oct 2018 23:30:44 +0000 (09:30 +1000)]
radv: remove unsigned comparison against 0
The value is always >= 0 here.
Found by coverity
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Thu, 4 Oct 2018 23:24:31 +0000 (09:24 +1000)]
radv: remove dead code for master_fd close
We have never opened master_Fd at this point, so remove code to
close it.
Found by coverity.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Thu, 4 Oct 2018 23:17:45 +0000 (09:17 +1000)]
radv: don't pass shader key by copy
Coverity pointed out we were copying 168 bytes here unnecessarily.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Thu, 4 Oct 2018 23:56:19 +0000 (09:56 +1000)]
anv: add missing unlock in error path.
Not going to matter, but be consistent.
Found by coverity
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes:
caf41c78c (anv/allocator: Support softpin in the BO cache)
Jason Ekstrand [Mon, 8 Oct 2018 17:22:35 +0000 (12:22 -0500)]
intel: Don't propagate conditional modifiers if a UD source is negated
This fixes a bug uncovered by my NIR integer division by constant
optimization series.
Fixes:
19f9cb72c8b "i965/fs: Add pass to propagate conditional..."
Fixes:
627f94b72e0 "i965/vec4: adding vec4_cmod_propagation..."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Thu, 13 Sep 2018 14:56:20 +0000 (09:56 -0500)]
util: Add tests for fast integer division by constants
While I generally trust rediculousfish to have done his homework, we've
made some adjustments to suit the needs of mesa and it'd be good to
test those. Also, there's no better place than unit tests to clearly
document the different edge cases of the different methods.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sat, 6 Oct 2018 01:42:16 +0000 (20:42 -0500)]
util: Add power-of-two divisor support to compute_fast_udiv_info
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Sat, 6 Oct 2018 01:29:31 +0000 (20:29 -0500)]
util: Generalize fast integer division to be variable bit-width
There's nothing inherently fixed-width in the code. All that's required
to generalize it is to make everything internally 64-bit and pass
UINT_BITS in as a parameter to util_compute_fast_[us]div_info. With
that, it can now handle 8, 16, 32, and 64-bit integer division by a
constant.
We also add support for division by 1 and by other powers of 2. This is
useful if you want to divide by a uniform value in a shader where you
have the opportunity to adjust the uniform on the CPU before passing it
in.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sat, 6 Oct 2018 01:28:40 +0000 (20:28 -0500)]
util: Add fast division helpers
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Sun, 23 Sep 2018 16:57:51 +0000 (12:57 -0400)]
util: import public domain code for integer division by a constant
Compilers can use this to generate optimal code for integer division
by a constant.
Additionally, an unsigned division by a uniform that is constant but not
known at compile time can still be optimized by passing 2-4 division
factors to the shader as uniforms and executing one of the fast_udiv*
variants. The signed division algorithm doesn't have this capability.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Fri, 29 Dec 2017 21:30:32 +0000 (13:30 -0800)]
util: Add a simple big math library
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dylan Baker [Mon, 1 Oct 2018 19:40:34 +0000 (12:40 -0700)]
meson: Don't allow building EGL on Windows or MacOS
Currently mesa only supports EGL on Unix like systems, cygwin, and
haiku. Meson should actually enforce this. This fixes the default build
on MacOS.
v2: - invert the condition, mark darwin and windows as not supported
instead of trying to mark what is supported.
v3: - add missing )
v3: - Update comment to reflect condition change in v2
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Timothy Arceri [Wed, 10 Oct 2018 00:03:47 +0000 (11:03 +1100)]
glsl: ignore trailing whitespace when define redefined
The Nvidia/AMD binary drivers allow this, as does GCC.
This fixes shader compilation issues in the latest update of
No Mans Sky.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Sun, 9 Sep 2018 21:06:43 +0000 (14:06 -0700)]
intel/compiler: Don't handle fsign.sat
No shader-db or CI changes on any Intel platform.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Ian Romanick [Sun, 9 Sep 2018 20:40:02 +0000 (13:40 -0700)]
nir/algebraic: Simplify fsat of fsign
These allows us to not support fsign.sat in the Intel compiler backend,
and that will simplify some later changes.
No shader-db changes on any Intel platform.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Ian Romanick [Mon, 10 Sep 2018 17:39:42 +0000 (10:39 -0700)]
nir/algebraic: sign(x)*x*x is abs(x)*x
shader-db results:
All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs:
15106023 ->
15105981 (<.01%)
instructions in affected programs: 300 -> 258 (-14.00%)
helped: 6
HURT: 0
helped stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7
helped stats (rel) min: 14.00% max: 14.00% x̄: 14.00% x̃: 14.00%
95% mean confidence interval for instructions value: -7.00 -7.00
95% mean confidence interval for instructions %-change: -14.00% -14.00%
Instructions are helped.
total cycles in shared programs:
566050327 ->
566050075 (<.01%)
cycles in affected programs: 2826 -> 2574 (-8.92%)
helped: 6
HURT: 0
helped stats (abs) min: 40 max: 44 x̄: 42.00 x̃: 42
helped stats (rel) min: 8.89% max: 8.94% x̄: 8.92% x̃: 8.92%
95% mean confidence interval for cycles value: -44.30 -39.70
95% mean confidence interval for cycles %-change: -8.95% -8.88%
Cycles are helped.
No changes on Gen6 or earlier.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Ian Romanick [Wed, 6 Jun 2018 02:19:39 +0000 (19:19 -0700)]
nir: Add helper functions to get the instruction that generated a nir_src
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Brian Paul [Tue, 9 Oct 2018 14:55:46 +0000 (08:55 -0600)]
svga: change svga_destroy_shader_variant() to return void
svga_destroy_shader_variant() itself flushes and retries the command
if there's a failure. So no need for the callers to do it. Other
callers of the function were already ignoring the return value.
This also fixes a corner-case double-free reported by Coverity
(and reported by Dave Airlie).
Tested with various OpenGL apps.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Dylan Baker [Fri, 5 Oct 2018 16:37:32 +0000 (09:37 -0700)]
meson: Don't build glsl compiler tests unless OpenGL is enabled
Since there are no other users of the glsl compiler.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 5 Oct 2018 16:36:05 +0000 (09:36 -0700)]
meson: Only build gallium state tracker tests with shared_glapi
This has always been a requirement, it's just somehow been missed in the
meson build.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dylan Baker [Fri, 5 Oct 2018 16:33:59 +0000 (09:33 -0700)]
meson: only build clapi tests when OpenGL is being built
Otherwise building just vulkan (among other things) will build these
tests, pull in a bunch of stuff they shouldn't, and potentially fail to
compile.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Ilia Mirkin [Sun, 7 Oct 2018 21:45:07 +0000 (17:45 -0400)]
nvc0: fix blitting red to srgb8_alpha
For some reason the 2d engine can't handle this. Red formats get special
treatment there, so perhaps related.
Fixes dEQP-GLES3 tests of the form:
dEQP-GLES3.functional.fbo.blit.conversion.r{8,16f,32f}_to_srgb8_alpha8
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sun, 7 Oct 2018 21:43:57 +0000 (17:43 -0400)]
nv50,nvc0: guard against zero-size blits
The current state tracker can generate these sometimes. Fixing this is
more involved, and due to some integer math we can generate
divisions-by-zero.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sun, 7 Oct 2018 18:57:17 +0000 (14:57 -0400)]
nv50,nvc0: mark RGBX_UINT formats as renderable
This helps st/mesa avoid some (apparently) buggy fallbacks. Specifically
the CopyTexSubImage fallback tries to read texture A as RGBA_FLOAT and
write back that data into the target format, which fails for integer
formats which have no appropriate logic to do the conversion.
Since integer formats don't blend, there's no harm in the fact that the
"A" component gets written anyways.
Fixes, among others:
https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/canvas/tex-2d-rgb8ui-rgb_integer-unsigned_byte.html
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Eric Engestrom [Mon, 8 Oct 2018 15:23:25 +0000 (16:23 +0100)]
radv: add missing meson c++ visibility arguments
Fixes:
6f3aee40f90d725653b6 "radv: using tls to store llvm related info
and speed up compiles (v10)"
Cc: Dave Airlie <airlied@redhat.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Michel Dänzer [Fri, 5 Oct 2018 10:21:37 +0000 (12:21 +0200)]
gbm: Add GBM_FORMAT_ARGB1555 support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Michel Dänzer [Fri, 5 Oct 2018 10:17:47 +0000 (12:17 +0200)]
st/dri: Handle BGRA5551 format
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Thu, 4 Oct 2018 19:52:06 +0000 (15:52 -0400)]
freedreno/a5xx+a6xx: fix LRZ pitch alignment
Both RB_2D_DST_SIZE.PITCH (a6xx) and RB_MRT[n].PITCH (a5xx) need
alignment to 64.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 4 Oct 2018 19:06:12 +0000 (15:06 -0400)]
freedreno/a6xx: add LRZ support
As with a5xx, hidden behind FD_MESA_DEBUG=lrz due to being paranoid
about z-fighting issues with some games (in particular, this was
observed with 0ad on a5xx.. but I think the proper solution to enable
this by default is to figure out how to do driver specific driconf
options).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 4 Oct 2018 19:05:39 +0000 (15:05 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 5 Oct 2018 13:19:43 +0000 (09:19 -0400)]
freedreno/a6xx: add helper for various CP_EVENT_WRITE
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 5 Oct 2018 13:14:59 +0000 (09:14 -0400)]
freedreno/a6xx: remove unused fxns
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 2 Oct 2018 18:31:20 +0000 (14:31 -0400)]
freedreno/a6xx: remove fd6_shader_stateobj
Earlier gen's already got this cleanup, but a6xx was still off on a
branch then.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Ilia Mirkin [Fri, 5 Oct 2018 06:18:20 +0000 (02:18 -0400)]
glsl: fix array assignments of a swizzled vector
This happens in situations where we might do
vec.wzyx[i] = ...
The swizzle would get effectively ignored because of the interaction
between how ir_assignment->set_lhs works and overwriting the write_mask.
There are two cases, one where i is a constant, and another where i is
variable. We have to be extra-careful in both cases.
Fixes the following WebGL test:
https://www.khronos.org/registry/webgl/sdk/tests/conformance2/glsl3/vector-dynamic-indexing-swizzled-lvalue.html
And the new piglit tests:
swizzled-writemask-indexing-nonconst.shader_test
swizzled-writemask-indexing.shader_test
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Samuel Pitoiset [Wed, 3 Oct 2018 14:09:25 +0000 (16:09 +0200)]
radv: tidy up radv_pipeline_init_multisample_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 3 Oct 2018 14:09:24 +0000 (16:09 +0200)]
radv: always set PA_SC_MODE_CNTL_1.OUT_OF_ORDER_WATER_MARK
It has probably no effect without out of order rasterization
anyway.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 3 Oct 2018 14:09:23 +0000 (16:09 +0200)]
radv: set DB_EQAA.INCOHERENT_EQAA_READS
My attempt was to set this field instead of duplicating one.
Fixes:
6cfa321c39 ("radv: add potential missing fields for DB_EQAA")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Chystiakov, Dmytro [Wed, 3 Oct 2018 09:52:52 +0000 (12:52 +0300)]
i965: fallback RGBX to RGBA in glEGLImageTargetRenderbufferStorageOES
In the same fashion as is done for glEGLImageTextureTarget2D.
v2: share the fallback which sets baseformat and internalformat correctly
which makes both of the tests pass (Tapani)
Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests:
#SingleLayer_ColorTest_GpuColorOutputCpuRead_R8G8B8X8_UNORM
#SingleLayer_ColorTest_GpuColorOutputIsRenderable_R8G8B8X8_UNORM
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tapani Pälli [Tue, 25 Sep 2018 14:04:40 +0000 (17:04 +0300)]
glsl: do not attempt assignment if operand type not parsed correctly
v2: check types of both operands (Ian)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108012
Marek Olšák [Mon, 1 Oct 2018 19:51:06 +0000 (15:51 -0400)]
util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
Initial version discussed with Rob Clark under a different patch name.
This approach leaves his driver unaffected.
Marek Olšák [Fri, 21 Sep 2018 07:37:16 +0000 (03:37 -0400)]
radeonsi: fix a typo at CS_PARTIAL_FLUSH
harmless
Marek Olšák [Sat, 22 Sep 2018 01:30:09 +0000 (21:30 -0400)]
ac: add ac_build_round
Marek Olšák [Fri, 21 Sep 2018 07:30:18 +0000 (03:30 -0400)]
ac: correct PKT3_COPY_DATA definitions
Marek Olšák [Fri, 21 Sep 2018 07:27:06 +0000 (03:27 -0400)]
ac: simplify LLVM alloca helpers
Marek Olšák [Fri, 7 Sep 2018 22:44:54 +0000 (18:44 -0400)]
ac: define all address spaces properly
Gert Wollny [Fri, 5 Oct 2018 13:08:51 +0000 (15:08 +0200)]
gallivm: Make it possible to disable some optimization shortcuts in release builds
For testing it is of interest that all tests of dEQP pass, e.g. to test
virglrenderer on a host only providing software rendering like in a CI.
Hence make it possible to disable certain optimizations that make tests fail.
While we are there also add some documentation to the flags to make it clear
that this is opt-out.
Setting the environment variable "GALLIVM_PERF=no_filter_hacks" can be used to make
the following tests pass in release mode:
dEQP-GLES2.functional.texture.mipmap.2d.affine.*_linear_*
dEQP-GLES2.functional.texture.mipmap.cube.generate.*
dEQP-GLES2.functional.texture.vertex.2d.filtering.*_mipmap_linear_*
dEQP-GLES2.functional.texture.vertex.2d.wrap.*
Related:
https://bugs.freedesktop.org/show_bug.cgi?id=94957
v2: rename optimization disabling flag to 'safemath' and also move the
nopt flag to the perf flags.
v3: rename flag "safemath" to "no_filter_hacks" since safemath is usually
associated with floating point operations (Roland)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tomeu Vizoso [Thu, 4 Oct 2018 14:40:08 +0000 (16:40 +0200)]
virgl: Pass resource size and transfer offsets
Pass the size of a resource when creating it so a backing can be kept in
the other side.
Also pass the required offset to transfer commands.
This moves vtest closer to how virtio-gpu works, making it more useful
for testing.
v2: - Use new messages for creation and transfers, as changing the
behavior of the existing messages would be messy given that we don't
want to break compatibility with older servers.
v3: - Use correct strides: The resource corresponding to the output display
might have a differnt line stride then the IOVs, so when reading back
to this resource take the resource stride and the the IOV stride
into account.
v4: Fix transfer size calculation (Andrey Simiklit)
v5: Add comment about transfer size value in the PUT commend (Gurchetan).
Add a comment about the size correction for transfers for reading and
writing the resource. Fixing this by correctly evaluating the size
upfront will need some work also on the virglrenderer side.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (v2)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Gert Wollny [Thu, 4 Oct 2018 14:40:07 +0000 (16:40 +0200)]
virgl, vtest: Correct the transfer size calculation
The transfer size used in virglrenderer refers to uint32_t, so one
must add 3 and then divide by 4 instead of adding 3/4 which is a no-op
with integers.
Fixes:
b3b82fe8ea virgl/vtest: add vtest driver
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Alan Coopersmith [Fri, 5 Oct 2018 23:34:35 +0000 (16:34 -0700)]
util: Make xmlconfig.c build on Solaris without d_type in dirent (v2)
v2: check for lstat() failing
Fixes:
04bdbbcab3c "xmlconfig: read more config files from drirc.d/"
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Reviewed-by: Roland Mainz <roland.mainz@nrubsig.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Sonny Jiang [Wed, 3 Oct 2018 15:53:14 +0000 (11:53 -0400)]
radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Wed, 3 Oct 2018 15:53:13 +0000 (11:53 -0400)]
radeonsi:optimizing SET_CONTEXT_REG for shaders Tessellation
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Wed, 3 Oct 2018 15:53:12 +0000 (11:53 -0400)]
radeonsi:optimizing SET_CONTEXT_REG for shaders PS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Wed, 3 Oct 2018 15:53:11 +0000 (11:53 -0400)]
radeonsi:optimizing SET_CONTEXT_REG for shaders VS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Wed, 3 Oct 2018 15:53:10 +0000 (11:53 -0400)]
radeonsi:optimizing SET_CONTEXT_REG for shaders GS
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Fri, 5 Oct 2018 22:09:37 +0000 (18:09 -0400)]
radeonsi: optimize and allow reg > 31 in radeon_opt_set_context_reg functions
reg_saved will have 64 bits, and (1 << reg) where reg > 31 has undefined
behavior. (1ull << reg) would be correct for 64 bits.
This commit shifts the other way in order to merge the conditions.
Sonny Jiang [Wed, 3 Oct 2018 15:53:09 +0000 (11:53 -0400)]
radeonsi: optimizing SET_CONTEXT_REG for shaders ES
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Fri, 5 Oct 2018 12:39:01 +0000 (14:39 +0200)]
spirv: mark variables decorated with XfbBuffer as always active
Otherwise, they are removed during NIR linking or in some
lowering passes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Juan A. Suarez Romero [Fri, 5 Oct 2018 10:51:34 +0000 (12:51 +0200)]
docs: update calendar, add news and link release notes to 18.2.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Fri, 5 Oct 2018 10:45:35 +0000 (12:45 +0200)]
docs: add sha256 checksums for 18.2.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
cb63a4e1144d9cd8feda3799c68a32a769417b5f)
Juan A. Suarez Romero [Fri, 5 Oct 2018 10:13:33 +0000 (12:13 +0200)]
docs: add release notes for 18.2.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
abaeb79eb2c16d7abad06719f24d1e59ad775aa6)
Jason Ekstrand [Wed, 3 Oct 2018 17:14:20 +0000 (12:14 -0500)]
nir/alu_to_scalar: Use ssa_for_alu_src in hand-rolled expansions
The ssa_for_alu_src helper will correctly handle swizzles and other
source modifiers for you. The expansions for unpack_half_2x16,
pack_uvec2_to_uint, and pack_uvec4_to_uint were all broken with regards
to swizzles. The brokenness of unpack_half_2x16 was causing rendering
errors in Rise of the Tomb Raider on Intel ever since
c11833ab24dcba26
which added an extra copy propagation to the optimization pipeline and
caused us to start seeing swizzles where we hadn't seen any before.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926
Fixes:
9ce901058f3d "nir: Add lowering of nir_op_unpack_half_2x16."
Fixes:
9b8786eba955 "nir: Add lowering support for packing opcodes."
Tested-by: Alex Smith <asmith@feralinteractive.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Vadym Shovkoplias [Wed, 3 Oct 2018 08:39:04 +0000 (11:39 +0300)]
glsl/linker: Check the subroutine associated functions names
>From Section 6.1.2 (Subroutines) of the GLSL 4.00 specification
"A program will fail to compile or link if any shader
or stage contains two or more functions with the same
name if the name is associated with a subroutine type."
v2:
- error out earlier (Tapani)
- style fixes (Iago)
Fixes:
* no-overloads.vert
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108109
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tomeu Vizoso [Tue, 2 Oct 2018 07:07:31 +0000 (09:07 +0200)]
virgl: Negotiate version with vtest server
Check if server supports version negotation by sending a PING_PROTOCOL_VERSION
message right before a dummy RESOURCE_BUSY_WAIT. If we don't get a reply
for the first, we know the server doesn't support it.
If it does support it, we can query the max protocol version supported
by the server and fall back if needed.
v2: - Send a new message to negotiate the protocol version, checking if
the server supports this message by immediately sending a busy wait
message. (Dave Airlie)
v3: - Send a zero-arg command PING_PROTOCOL_VERSION so we actually keep
compatibility with older servers. (Code by Dave Airlie)
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Sagar Ghuge [Wed, 5 Sep 2018 17:19:47 +0000 (10:19 -0700)]
intel: aubinator: Fix memory leaks
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sagar Ghuge [Thu, 6 Sep 2018 04:14:23 +0000 (21:14 -0700)]
intel/decoder: construct correct xml filename
construct correct gen xml filename when we try to load hardware xml
description from a given path
v2: remove temporary variable (Francesco Ansanelli)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sagar Ghuge [Thu, 6 Sep 2018 19:37:28 +0000 (12:37 -0700)]
intel/decoder: Avoid freeing invalid pointer
v2: Free ctx.spec if error while reading genxml (Lionel Landwerlin)
v3: Handle case where genxml is empty (Lionel Landwerlin)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sagar Ghuge [Thu, 6 Sep 2018 04:05:21 +0000 (21:05 -0700)]
intel/decoder: add gen_spec_init method
Initialize gen_spec instance properly when loading hardware xml
description from specifc directory to avoid segmentation fault.
v2: correct function definition (Lionel Landwerlin)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset [Thu, 4 Oct 2018 08:37:09 +0000 (10:37 +0200)]
radv: fix resetting the pool for timestamp queries
Since the driver no longer uses the availability bit for
timestamp queries it shouldn't reset it. Instead, it should
reset the query values to UINT32_MAX. This fixes VM faults.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108164
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Guido Günther [Mon, 1 Oct 2018 16:37:28 +0000 (18:37 +0200)]
etnaviv: Use write combine instead of unached mappings for shader bo
The later are sensitive to unaligned accesses on arm64[1] and we don't
need an uncached mapping here.
[1]: https://lists.freedesktop.org/archives/etnaviv/2018-September/001956.html
Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Marek Olšák [Thu, 4 Oct 2018 04:55:52 +0000 (00:55 -0400)]
drirc: add a workaround for ARMA 3
Cc: 18.2 <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 2 Oct 2018 22:19:32 +0000 (17:19 -0500)]
anv/batch_chain: Don't start a new BO just for BATCH_BUFFER_START
Previously, we just went ahead and emitted MI_BATCH_BUFFER_START as
normal. If we are near enough to the end, this can cause us to start a
new BO just for the MI_BATCH_BUFFER_START which messes up chaining. We
always reserve enough space at the end for an MI_BATCH_BUFFER_START so
we can just increment cmd_buffer->batch.end prior to emitting the
command.
Fixes:
a0b133286a3 "anv/batch_chain: Simplify secondary batch return..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107926
Tested-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 9 Jul 2018 21:21:33 +0000 (14:21 -0700)]
anv: Use separate MOCS settings for external BOs
On Broadwell and above, we have to use different MOCS settings to allow
the kernel to take over and disable caching when needed for external
buffers. On Broadwell, this is especially important because the kernel
can't disable eLLC so we have to do it in userspace. We very badly
don't want to do that on everything so we need separate MOCS for
external and internal BOs.
In order to do this, we add an anv-specific BO flag for "external" and
use that to distinguish between buffers which may be shared with other
processes and/or display and those which are entirely internal. That,
together with an anv_mocs_for_bo helper lets us choose the right MOCS
settings for each BO use.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99507
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Emil Velikov [Fri, 7 Sep 2018 13:58:03 +0000 (14:58 +0100)]
meson: remove invalid "opencl" llvm component
Seeming copy/paste mistake from configure.ac which uses $2 for the
component and $3 for the fancy name printing.
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Emil Velikov [Mon, 24 Sep 2018 15:01:38 +0000 (16:01 +0100)]
Revert "mesa: remove unnecessary 'sort by year' for the GL extensions"
This reverts commit
3d81e11b49366b5636b8524ba0f8c7076e3fdf34.
As reported by Federico, some games require the 'sort by year' since
they truncate the extensions which do not fit the fixed size string
array.
Seemingly I did not consider that, as the documentation (both Mesa and
Nvidia) mentions about program crashes ... which are worked around by
setting the env. variable.
This commit reinstates the workaround and enhances the documentation.
Cc: Marek Olšák <maraeo@gmail.com>
Cc: Ian Romanick <idr@freedesktop.org>
Reported-by: Federico Dossena <info@fdossena.com>
Fixes:
3d81e11b493 ("mesa: remove unnecessary 'sort by year' for the GL
extensions")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Federico Dossena <info@fdossena.com>
Emil Velikov [Wed, 5 Sep 2018 16:35:17 +0000 (17:35 +0100)]
mesa: reorder and document the tokens in glheader.h
Split into different sections, document each one as well as strange
cases like GL_ATI_texture_compression_3dc.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Emil Velikov [Wed, 5 Sep 2018 16:35:16 +0000 (17:35 +0100)]
mesa: remove duplicate declarations from glheader.h
Remove all the desktop GL and GLX entries from the list.
Former are pulled by the gl.h and glext.h includes at the top while the
latter are no longer needed.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Emil Velikov [Wed, 5 Sep 2018 16:35:15 +0000 (17:35 +0100)]
i965: reference __DRI_ATTRIB_SWAP_COPY token over the GLX one
Earlier commit updated the code to use the DRI tokens, yet forgot to
update the comment.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Emil Velikov [Wed, 5 Sep 2018 16:35:14 +0000 (17:35 +0100)]
i915: reference __DRI_ATTRIB_SWAP_COPY token over the GLX one
Earlier commit updated the code to use the DRI tokens, yet forgot to
update the comment.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Emil Velikov [Wed, 5 Sep 2018 16:35:13 +0000 (17:35 +0100)]
dri/common: move the required GLX_* token definitions locally
Will allow us to remove even bigger hack elsewhere. But more
importantly, we should not be using _any_ GLX tokens in DRI.
Document the gory details about the current side-effects.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>