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Florian Hahn [Fri, 25 May 2018 23:32:02 +0000 (23:32 +0000)]
Revert r333268: [IPSCCP] Use PredicateInfo to propagate facts from...
Reverting this to see if this is causing the failures of the
clang-with-thin-lto-ubuntu bot.
[IPSCCP] Use PredicateInfo to propagate facts from cmp instructions.
This patch updates IPSCCP to use PredicateInfo to propagate
facts to true branches predicated by EQ and to false branches
predicated by NE.
As a follow up, we should be able to extend it to also propagate additional
facts about nonnull.
Reviewers: davide, mssimpso, dberlin, efriedma
Reviewed By: davide, dberlin
Differential Revision: https://reviews.llvm.org/D45330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333323
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George Burgess IV [Fri, 25 May 2018 21:16:58 +0000 (21:16 +0000)]
Replace AA's uses of uint64_t with LocationSize; NFC.
The uint64_ts that we pass around AA to represent MemoryLocation sizes
are logically an Optional<uint64_t>. In D44748, we want to add an extra
'imprecise' bit to this Optional<uint64_t> to represent whether a given
MemoryLocation size is an upper-bound or an exact size. For more context
on why, please see D44748.
That patch is quite large, but reviewers seem to be OK with the
approach. In D45581 (my first attempt to split 'noise' out of D44748),
reames asked that I land a precursor that is solely replacing uint64_t
with LocationSize, which starts out as `using LocationSize = uint64_t;`.
He also gave me the OK to submit this rename without further review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333314
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Petr Hosek [Fri, 25 May 2018 20:39:37 +0000 (20:39 +0000)]
[Support] Avoid normalization in sys::getDefaultTargetTriple
The return value of sys::getDefaultTargetTriple, which is derived from
-DLLVM_DEFAULT_TRIPLE, is used to construct tool names, default target,
and in the future also to control the search path directly; as such it
should be used textually, without interpretation by LLVM.
Normalization of this value may lead to unexpected results, for example
if we configure LLVM with -DLLVM_DEFAULT_TARGET_TRIPLE=x86_64-linux-gnu,
normalization will transform that value to x86_64--linux-gnu. Driver will
use that value to search for tools prefixed with x86_64--linux-gnu- which
may be confusing. This is also inconsistent with the behavior of the
--target flag which is taken as-is without any normalization and overrides
the value of LLVM_DEFAULT_TARGET_TRIPLE.
Users of sys::getDefaultTargetTriple already perform their own
normalization as needed, so this change shouldn't impact existing logic.
Differential Revision: https://reviews.llvm.org/D47153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333307
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Guozhi Wei [Fri, 25 May 2018 20:30:26 +0000 (20:30 +0000)]
[CodeGenPrepare] Revert r331783
The patch r331783 caused regression in one of our internal application. So revert it now, will investigate it further.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333305
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Mark Searles [Fri, 25 May 2018 20:24:08 +0000 (20:24 +0000)]
[AMDGPU][Waitcnt] Remove obsolete waitcnt option
With the removal of the old waitcnt pass, the '-enable-si-insert-waitcnts' option is obsolete. Remove it.
Differential Revision: https://reviews.llvm.org/D47378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333303
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Craig Topper [Fri, 25 May 2018 19:18:09 +0000 (19:18 +0000)]
Recommit r333226 "[ValueTracking] Teach computeKnownBits that the result of an absolute value pattern that uses nsw flag is always positive."
Libfuzzer tests have been fixed to prevent being optimized.
Original commit message:
If the nsw flag is used in the absolute value then it is undefined for INT_MIN. For all other value it will produce a positive number. So we can assume the result is positive.
This breaks some InstCombine abs/nabs combining tests because we simplify the second compare from known bits rather than as the whole pattern. Looks like we can probably fix it by adding a neg+abs/nabs combine to just swap the select operands. N
Differential Revision: https://reviews.llvm.org/D47041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333300
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Stanislav Mekhanoshin [Fri, 25 May 2018 18:46:58 +0000 (18:46 +0000)]
[AMDGPU] Fixed test failure with AMDGPUPerfHint
We shall not keep iterator to a map while map is modified,
this leads to a broken map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333298
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Matt Davis [Fri, 25 May 2018 18:45:43 +0000 (18:45 +0000)]
[llvm-mca] Update the header's guard name. NFC.
This patch also places a comment at the end of the header guard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333297
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Matt Davis [Fri, 25 May 2018 18:31:28 +0000 (18:31 +0000)]
[llvm-mca] Update DispatchStage header comment. NFC.
Updated the comment to be a wee bit more descriptive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333296
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Andrea Di Biagio [Fri, 25 May 2018 18:25:54 +0000 (18:25 +0000)]
[Tablegen][SubtargetEmitter] Add a default case to the auto-generated switch in MCSubtargetInfo::resolveVariantSchedClass(). NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333293
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Matt Davis [Fri, 25 May 2018 18:00:25 +0000 (18:00 +0000)]
[llvm-mca] Add the RetireStage.
Summary:
This class maintains the same logic as the original RetireControlUnit.
This is just an intermediate patch to make the RCU a Stage. Future patches will remove the dependency on the DispatchStage, and then more properly populate the pre/execute/post Stage interface.
Reviewers: andreadb, RKSimon, courbet
Reviewed By: andreadb, courbet
Subscribers: javed.absar, mgorny, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333292
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Reid Kleckner [Fri, 25 May 2018 17:46:24 +0000 (17:46 +0000)]
Fix -Winconsistent-missing-overrides in AMDGPU code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333291
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Stanislav Mekhanoshin [Fri, 25 May 2018 17:25:12 +0000 (17:25 +0000)]
[AMDGPU] Add perf hints to functions
This is adoption of HSAIL perfhint pass. Two types of hints are produced:
1. Function is memory bound.
2. Kernel can use wave limiter.
Currently these hints are used in the scheduler. If a function is suspected
to be memory bound we allow occupancy to decrease to 4 waves in the course
of scheduling.
Differential Revision: https://reviews.llvm.org/D46992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333289
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Simon Dardis [Fri, 25 May 2018 16:15:48 +0000 (16:15 +0000)]
[mips] Fix the definitions of lwp, swp
Rather than using a regpair operand of these instructions, use two seperate
operands and a custom converter to handle the implicit second register operand.
Additionally, remove the microMIPS32R6 definition as its redundant.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D47255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333288
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Andrea Di Biagio [Fri, 25 May 2018 16:02:43 +0000 (16:02 +0000)]
[RFC][Patch 2/3] Add a MCSubtargetInfo hook to resolve variant scheduling classes.
This patch is the second of a sequence of three patches related to LLVM-dev RFC
"MC support for varinat scheduling classes".
https://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html
The goal of this patch is to enable the resolution of variant classes in MC with
the help of a new method named `MCSubtargetInfo::resolveVariantSchedClass()`.
This patch also teaches the SubtargetEmitter how to automatically generate the
definition of method resolveVariantSchedClass(). That definition is emitted
within a sub-class of MCSubtargetInfo named XXXGenMCSubtargetInfo (where XXX is
the name of the Target).
Differential Revision: https://reviews.llvm.org/D47077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333286
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Andrea Di Biagio [Fri, 25 May 2018 15:55:37 +0000 (15:55 +0000)]
[RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes.
This patch is the first of a sequence of three patches described by the LLVM-dev
RFC "MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html
The goal of this patch is to introduce a new class of scheduling predicates for
SchedReadVariant and SchedWriteVariant.
An MCSchedPredicate can be used instead of a normal SchedPredicate to model
checks on the instruction (either a MachineInstr or a MCInst).
Internally, an MCSchedPredicate encapsulates an MCInstPredicate definition.
MCInstPredicate allows the definition of expressions with a well-known semantic,
that can be used to generate code for both MachineInstr and MCInst.
This is the first step toward teaching to tools like lllvm-mca how to resolve
variant scheduling classes.
Differential Revision: https://reviews.llvm.org/D46695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333282
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Teresa Johnson [Fri, 25 May 2018 15:15:39 +0000 (15:15 +0000)]
[NFC] Restructure linkage name printing in AsmWriter
This restructuring was suggested in the review for D46699, which
prepares the linkage type printer for use in printing the ThinLTO
summary index (where we want to print "external" and also don't
want a space after the linkage type as it is printed by the caller).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333281
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Krzysztof Parzyszek [Fri, 25 May 2018 14:53:14 +0000 (14:53 +0000)]
[Hexagon] Fix packing source vectors in shufflevector selection
When the shuffle mask selected a subvector of the second input vector,
and aligning of the source was performed, the shuffle mask was updated
incorrectly, resulting in an ICE further in the selection process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333279
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David Stenberg [Fri, 25 May 2018 13:02:59 +0000 (13:02 +0000)]
[MustExecute] Fix a debug invariant issue in isGuaranteedToExecute()
Summary:
Look past debug intrinsics when querying whether an instruction is the
first instruction in the header block. The commit includes a reproducer
for a case where LICM would not hoist an instruction, due to the presence
of the intrinsic.
A caveat with this commit is that the check will not work properly if
the instruction at hand is a debug intrinsic. I assume that no one
depends on isGuaranteedToExecute() to return true for debug intrinsics
for these cases (and that this might be an indication of another debug
invariant issue), so I thought that it was not worth adding that extra
bit of complexity.
Reviewers: reames, anna
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333274
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Simon Pilgrim [Fri, 25 May 2018 12:18:11 +0000 (12:18 +0000)]
[X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286)
As confirmed by llvm-exegesis, there is no scheduler difference between MOVDQA/MOVDQU and VMOVDQA/VMOVDQU xmm reg-reg moves
Another chapter in the never ending crusade to remove useless InstRW overrides from the x86 scheduler models......
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333271
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Sander de Smalen [Fri, 25 May 2018 11:41:04 +0000 (11:41 +0000)]
Fix ubsan errors introduced by r333263 re. left-shifting negative values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333270
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Florian Hahn [Fri, 25 May 2018 11:12:33 +0000 (11:12 +0000)]
[IPSCCP] Use PredicateInfo to propagate facts from cmp instructions.
This patch updates IPSCCP to use PredicateInfo to propagate
facts to true branches predicated by EQ and to false branches
predicated by NE.
As a follow up, we should be able to extend it to also propagate additional
facts about nonnull.
Reviewers: davide, mssimpso, dberlin, efriedma
Reviewed By: davide, dberlin
Differential Revision: https://reviews.llvm.org/D45330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333268
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Paul Semel [Fri, 25 May 2018 11:01:25 +0000 (11:01 +0000)]
[llvm-objcopy] Add --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D46896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333267
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Krasimir Georgiev [Fri, 25 May 2018 10:10:02 +0000 (10:10 +0000)]
Fix ODR violation from r333230
This is an ODR violation, for example in ExecutionEngine/MCJIT/MCJIT.o: multiple definition of 'LLVMCreateIntelJITEventListener'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333265
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Sander de Smalen [Fri, 25 May 2018 09:47:52 +0000 (09:47 +0000)]
[AArch64][SVE] Asm: Support for DUP (immediate) instructions.
Unpredicated copy of optionally-shifted immediate to SVE vector,
along with MOV-aliases.
This patch contains parsing and printing support for
cpy_imm8_opt_lsl_(i8|i16|i32|i64). This operand allows a signed value in
the range -128 to +127. For element widths of 16 bits or higher it may
also be a signed multiple of 256 in the range -32768 to +32512.
For element-width of 8 bits a range of -128 to 255 is accepted, since a copy
of a byte can be considered either signed/unsigned.
Note: This patch renames tryParseAddSubImm() -> tryParseImmWithOptionalShift()
and moves the behaviour of trying to shift a plain immediate by an allowed
shift-value to its addImmWithOptionalShiftOperands() method, so that the
parsing itself is generic and allows immediates from multiple shifted operands.
This is done because an immediate can be divisible by both shifted operands.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333263
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Jonas Paulsson [Fri, 25 May 2018 09:01:23 +0000 (09:01 +0000)]
[SystemZ] Bugfix in combineSTORE().
Remember to check if store is truncating before calling
combineTruncateExtract().
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333262
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Jonas Paulsson [Fri, 25 May 2018 08:42:02 +0000 (08:42 +0000)]
[RegUsageInfoCollector] Bugfix for callee saved registers.
Previously, this pass would look at the (static) set returned by
getCallPreservedMask() and add those back as preserved in the case when
isSafeForNoCSROpt() returns false.
A problem is that a target may have to save some registers even when NoCSROpt
takes place. For instance, on SystemZ, the return register is needed upon
return from a function.
Furthermore, getCallPreservedMask() only includes the registers that the
target actually wishes to emit save/restore instructions for. This means that
subregs and (fully saved) superregs are missing.
This patch instead takes the (dynamic) set returned by target for the
function from determineCalleeSaves() and then adds sub/super regs to build
the set to be used when building the RegMask for the function.
Review: Quentin Colombet, Ulrich Weigand
https://reviews.llvm.org/D46315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333261
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Tim Renouf [Fri, 25 May 2018 07:55:04 +0000 (07:55 +0000)]
[AMDGPU] Fixed incorrect break from loop
Summary:
Lower control flow did not correctly handle the case that a loop break
in if/else was on a condition that was not guaranteed to be masked by
exec. The first test kernel shows an example of this going wrong; after
exiting the loop, exec is all ones, even if it was not before the loop.
The fix is for lowering of if-break and else-break to insert an
S_AND_B64 to mask the break condition with exec. This commit also
includes the optimization of not inserting that S_AND_B64 if it is
obviously not needed because the break condition is the result of a
V_CMP in the same basic block.
V2: Addressed some review comments.
V3: Test fixes.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D44046
Change-Id: I0fc56a01209a9e99d1d5c9b0ffd16f111caf200c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333258
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Gabor Buella [Fri, 25 May 2018 06:32:05 +0000 (06:32 +0000)]
[x86] invpcid LLVM intrinsic
Re-add the feature flag for invpcid, which was removed in r294561.
Add an intrinsic, which always uses a 32 bit integer as first argument,
while the instruction actually uses a 64 bit register in 64 bit mode
for the INVPCID_TYPE argument.
Reviewers: craig.topper
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D47141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333255
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Tom Stellard [Fri, 25 May 2018 04:57:02 +0000 (04:57 +0000)]
AMDGPU: Remove AMDGPUMCInstLower.h
Summary:
The AMDGPUMCInstLower class is not used outside AMDGPUMCInstLower.cpp,
so we don't need a header file.
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333254
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Craig Topper [Fri, 25 May 2018 04:01:56 +0000 (04:01 +0000)]
Revert r333226 "[ValueTracking] Teach computeKnownBits that the result of an absolute value pattern that uses nsw flag is always positive."
This breaks some libFuzzer tests. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/15589/steps/check-fuzzer/logs/stdio
Reverting to investigate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333253
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Chandler Carruth [Fri, 25 May 2018 01:32:36 +0000 (01:32 +0000)]
Restore the LoopInstSimplify pass, reverting r327329 that removed it.
The plan had always been to move towards using this rather than so much
in-pass simplification within the loop pipeline, but we never got around
to it.... until only a couple months after it was removed due to disuse.
=/
This commit is just a pure revert of the removal. I will add tests and
do some basic cleanup in follow-up commits. Then I'll wire it into the
loop pass pipeline.
Differential Revision: https://reviews.llvm.org/D47353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333250
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Chris Matthews [Fri, 25 May 2018 00:31:36 +0000 (00:31 +0000)]
Use quoteattr to ensure we make well formed attributes
We were making malformed XML on tests with ' in the name. Switch to
using saxutils to set all of our attributes, so it can handle quotes
etc correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333249
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Fangrui Song [Fri, 25 May 2018 00:11:15 +0000 (00:11 +0000)]
[llvm-symbolizer] Simplify. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333247
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Vedant Kumar [Thu, 24 May 2018 23:00:23 +0000 (23:00 +0000)]
[Debugify] Set a DI version module flag for llc compatibility
Setting the "Debug Info Version" module flag makes it possible to pipe
synthetic debug info into llc, which is useful for testing backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333237
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Vedant Kumar [Thu, 24 May 2018 23:00:22 +0000 (23:00 +0000)]
[Debugify] Avoid printing unnecessary square braces, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333236
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Vedant Kumar [Thu, 24 May 2018 23:00:21 +0000 (23:00 +0000)]
[DebugInfo] Maintain DI when converting GEP to bitcast
When a GEP with all zero indices is converted to bitcast, its DI wasn't
copied over to the newly created instruction. This patch fixes that bug.
Patch by Kareem Ergawy!
Differential Revision: https://reviews.llvm.org/D47347
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333235
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Florian Hahn [Thu, 24 May 2018 21:33:17 +0000 (21:33 +0000)]
[LegacyPM] Use MapVector for OnTheFlyPassManagers.
Currently the iteration order of OnTheFlyManagers is not deterministic
between executions, which means some of test/Other/opt-*-pipeline.ll
tests fail non-deterministically if an additional on-the-fly manager is
added, as in D45330.
By using MapVector, we always iterate in the insertion order. As we are
not removing elements, there shouldn't be a performance hit, except that
we store an additional vector with the keys.
Reviewers: efriedma, chandlerc, pcc, jhenderson
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D47317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333231
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Andres Freund [Thu, 24 May 2018 21:32:54 +0000 (21:32 +0000)]
[C-API] Add functions to create GDB, Intel, Oprofile event listeners.
The additions of Intel, Oprofile listeners were done blindly.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D44890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333230
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Andres Freund [Thu, 24 May 2018 21:32:52 +0000 (21:32 +0000)]
[ORC][C-API] Expose LLVMOrc{Unr,R}egisterJITEventListener().
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D44890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333229
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Andres Freund [Thu, 24 May 2018 21:32:50 +0000 (21:32 +0000)]
[ORC] Add ability [un]register JITEventListener on Orc C stack.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D44890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333228
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Andres Freund [Thu, 24 May 2018 21:32:48 +0000 (21:32 +0000)]
[ORC] Extend object layer callbacks so JITEventListener can be supported.
Currently RTDyldObjectLinkingLayer makes it hard to support
JITEventListeners. Which in turn means debugging and profiling JIT
generated code hard.
Supporting JITEventListeners at minimum requries a freed
callback (added).
As listeners expect the ObjectFile to be passed as well, an adaptor
between RTDyldObjectLinkingLayer and JITEventListeners would currently
need to also maintain ObjectFiles for all loaded modules. To make that
less awkward, extend the callbacks to pass the ObjectFile to both
Finalized and Freed callbacks. That requires extending the lifetime
of the object file when callbacks are present.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D44890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333227
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Craig Topper [Thu, 24 May 2018 21:22:51 +0000 (21:22 +0000)]
[ValueTracking] Teach computeKnownBits that the result of an absolute value pattern that uses nsw flag is always positive.
If the nsw flag is used in the absolute value then it is undefined for INT_MIN. For all other value it will produce a positive number. So we can assume the result is positive.
This breaks some InstCombine abs/nabs combining tests because we simplify the second compare from known bits rather than as the whole pattern. Looks like we can probably fix it by adding a neg+abs/nabs combine to just swap the select operands. Need to check alive to make sure there are no corner cases.
Differential Revision: https://reviews.llvm.org/D47041
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333226
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Warren Ristow [Thu, 24 May 2018 20:16:43 +0000 (20:16 +0000)]
[InstCombine] Enable more reassociations using FMF 'reassoc' + 'nsz'
Reassociation of math ops in some contexts (especially vector contexts)
has generally only been happening when the 'fast' FMF was set. This
enables reassoication when only the finer grained controls 'reassoc' and
'nsz' are set.
Differential Revision: https://reviews.llvm.org/D47335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333221
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Tom Stellard [Thu, 24 May 2018 20:02:01 +0000 (20:02 +0000)]
AMDGPU: Split R600 AsmPrinter code into its own class
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D47245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333219
91177308-0d34-0410-b5e6-
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Eli Friedman [Thu, 24 May 2018 19:38:23 +0000 (19:38 +0000)]
[AArch64] Improve orr+movk sequences for MOVi64imm.
The existing code has three different ways to try to lower a 64-bit
immediate to the sequence ORR+MOVK. The result is messy: it misses
some possible sequences, and the order of the checks means we sometimes
emit two MOVKs when we only need one.
Instead, just use a simple loop to try all possible two-instruction
ORR+MOVK sequences.
Differential Revision: https://reviews.llvm.org/D47176
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333218
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Lang Hames [Thu, 24 May 2018 19:07:34 +0000 (19:07 +0000)]
Add handling for GlobalAliases in ExecutionEngine::getConstantValue.
Patch by Brad Moody. Thanks Brad!
https://reviews.llvm.org/D42160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333217
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Andres Freund [Thu, 24 May 2018 18:44:34 +0000 (18:44 +0000)]
[ORC] Add findSymbolIn() wrapper to C bindings, take #2.
Re-appply r333147, reverted in r333152 due to a pre-existing bug. As
D47308 has been merged in r333206, the OSX issue should now be
resolved.
In many cases JIT users will know in which module a symbol
resides. Avoiding to search other modules can be more efficient. It
also allows to handle duplicate symbol names between modules.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D44889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333215
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Geoff Berry [Thu, 24 May 2018 18:29:42 +0000 (18:29 +0000)]
[AArch64] Take advantage of variable shift/rotate amount implicit mod operation.
Summary:
Optimize code generated for variable shifts/rotates by taking advantage
of the implicit and/mod done on the variable shift amount register.
Resolves bug 27582 and bug 37421.
Reviewers: t.p.northover, qcolombet, MatzeB, javed.absar
Subscribers: rengolin, kristof.beyls, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D46844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333214
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Teresa Johnson [Thu, 24 May 2018 17:42:25 +0000 (17:42 +0000)]
[ThinLTO/CFI] Minor comment clarification
Summary: Suggested by Duncan on the review thread for D46699.
Reviewers: pcc
Subscribers: inglorion, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D47338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333212
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Andrea Di Biagio [Thu, 24 May 2018 17:22:14 +0000 (17:22 +0000)]
[llvm-mca] Fix a rounding problem in SummaryView.cpp exposed by r333204.
Before printing the block reciprocal throughput, ensure that the floating point
number is always rounded the same way on every target.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333210
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Andres Freund [Thu, 24 May 2018 17:03:06 +0000 (17:03 +0000)]
[ORC] Perform name mangling in findSymbolIn(), as done in findSymbol().
The lack of name mangling caused a unittest failure after r333147 (in
TestEagerIRCompilation), as OSX prefixes symbol names with '_'. The
lack of name mangling therefore leads to a NULL pointer being returned
and then called, hence the failure.
While it may look like it, this isn't an actual behavioral change, as
findSymbolIn() previously was not exposed externally, and essentially
dead code. Which explains why nobody noticed the issue previously.
Reviewers: lhames
Reviewed By: lhames
Subscribers: chandlerc, llvm-commits
Differential Revision: https://reviews.llvm.org/D47308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333206
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Greg Bedwell [Thu, 24 May 2018 16:36:44 +0000 (16:36 +0000)]
[UpdateTestChecks] Improved update_mca_test_checks block analysis
Previously update_mca_test_checks worked entirely at "block" level where
a block is some sequence of lines delimited by at least one empty line.
This generally worked well, but could sometimes lead to excessive
repetition of check lines for various prefixes if some block was almost
identical between prefixes, but not quite (for example, due to a
different dispatch width in the otherwise identical summary views).
This new analyis attempts to split blocks further in the case where the
following conditions are met:
a) There is some prefix common to every RUN line (typically 'ALL').
b) The first line of the block is common to the output with every prefix.
c) The block has the same number of lines for the output with every prefix.
Also, regenerated all llvm-mca test files with the following command:
update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s"
The new analysis showed a "multiple lines not disambiguated by prefixes" warning
for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some
explicit prefixes to each of the RUN lines in that test.
Differential Revision: https://reviews.llvm.org/D47321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333204
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Simon Pilgrim [Thu, 24 May 2018 16:16:42 +0000 (16:16 +0000)]
[X86][SSE] Pull out (AND (XOR X, -1), Y) matching into a helper function. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333201
91177308-0d34-0410-b5e6-
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Sean Fertile [Thu, 24 May 2018 16:02:05 +0000 (16:02 +0000)]
Add R_PPC64_IRELATIVE to PPC64 relocations.
Relocation is needed for use in lld, which has the accompanying test.
Differential Review: https://reviews.llvm.org/D46876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333200
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Jun Bum Lim [Thu, 24 May 2018 15:58:34 +0000 (15:58 +0000)]
[LICM] Preserve DT and LoopInfo specifically
Summary:
In LICM, CFG could be changed in splitPredecessorsOfLoopExit(), which update
only DT and LoopInfo. Therefore, we should preserve only DT and LoopInfo specifically,
instead of all analyses that depend on the CFG (setPreservesCFG()).
This change should fix PR37323.
Reviewers: uabelho, davide, dberlin, Ka-Ka
Reviewed By: dberlin
Subscribers: mzolotukhin, bjope, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D46775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333198
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Simon Pilgrim [Thu, 24 May 2018 15:34:50 +0000 (15:34 +0000)]
Fix unused variable warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333195
91177308-0d34-0410-b5e6-
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Chad Rosier [Thu, 24 May 2018 15:26:42 +0000 (15:26 +0000)]
[InstCombine] Combine XOR and AES instructions on ARM/ARM64.
The ARM/ARM64 AESE and AESD instructions have a builtin XOR as the first step in
the instruction. Therefore, if the AES key is zero and the AES data was
previously XORed, it can be combined into a single instruction.
Differential Revision: https://reviews.llvm.org/D47239
Patch by Michael Brase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333193
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Nicola Zaghen [Thu, 24 May 2018 15:15:27 +0000 (15:15 +0000)]
FastMathFlags: Make it easier to unset individual ones.
This makes the various flags similar to current setAllowContract.
Differential Revision: https://reviews.llvm.org/D47323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333192
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 24 May 2018 15:12:48 +0000 (15:12 +0000)]
[X86][SSE] Pull out OR(AND(~MASK,X),AND(MASK,Y)) matching into a helper function. NFC.
First stage towards matching more variants of the bitselect pattern for combineLogicBlendIntoPBLENDV (PR37549)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333191
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Simon Pilgrim [Thu, 24 May 2018 14:54:32 +0000 (14:54 +0000)]
[X86][BtVer2] Added Jaguar cpu cycle counter to permit llvm-exegesis latency testing
Ideally we'd be able to test a CPU by using __builtin_readcyclecounter()/RDTSC instead (PR37193) if a model/cycle-counter is not specified.
NOTE: Jaguar PMCs don't give good coverage of resource pipes specified in the model (at the macro-vs-micro-op levels) but we should be able to cover at least a few resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333190
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Andrei Elovikov [Thu, 24 May 2018 14:31:00 +0000 (14:31 +0000)]
[NFC][VPlan] Wrap PlainCFGBuilder with an anonymous namespace.
Summary:
It's internal to the VPlanHCFGBuilder and should not be visible outside of its
translation unit.
Reviewers: dcaballe, fhahn
Reviewed By: fhahn
Subscribers: rengolin, bollu, tschuett, llvm-commits, rkruppe
Differential Revision: https://reviews.llvm.org/D47312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333187
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Sanjay Patel [Thu, 24 May 2018 13:49:57 +0000 (13:49 +0000)]
[x86] add vector load-cmp-select tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333185
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Clement Courbet [Thu, 24 May 2018 12:41:02 +0000 (12:41 +0000)]
[llvm-exegesis] Analysis: Show value extents.
Summary: Screenshot attached in phabricator.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333181
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Jonas Devlieghere [Thu, 24 May 2018 11:47:20 +0000 (11:47 +0000)]
[Support] Move header to WithColor header
Forgot to move the CommandLine.h include form the implementation to the
header and didn't notice the failure with my local modules build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333177
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Jonas Devlieghere [Thu, 24 May 2018 11:36:57 +0000 (11:36 +0000)]
[Support] Add color cl category.
This commit adds a color category so tools can document this option and
enables it for dwarfdump and dsymuttil.
rdar://problem/
40498996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333176
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Clement Courbet [Thu, 24 May 2018 11:26:00 +0000 (11:26 +0000)]
[llvm-exegesis] Analysis: show debug string instead of raw key if provided.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333175
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Clement Courbet [Thu, 24 May 2018 10:47:05 +0000 (10:47 +0000)]
[llvm-exegesis] Show sched class details in analysis.
Summary: And update docs.
Reviewers: gchatelet
Subscribers: tschuett, craig.topper, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D47254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333169
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Ekaterina Romanova [Thu, 24 May 2018 08:45:15 +0000 (08:45 +0000)]
Added a testcase for PR31593. A patch (r291535) that fixed this bug didn't have a testcase.
Differential Revision: https://reviews.llvm.org/D47129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333167
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Jonas Paulsson [Thu, 24 May 2018 08:38:06 +0000 (08:38 +0000)]
[ScheduleDAGInstrs / buildSchedGraph] Clear subregister entries also.
In addPhysRegDeps, subregister entries of the defined register were previously
not removed from Uses or Defs, which resulted in extra redundant edges for
subregs around the register definition.
This is principally NFC (in very rare cases some node got a different height).
This makes the DAG more readable and efficient in some cases.
Review: Andy Trick
https://reviews.llvm.org/D46838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333165
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Simon Atanasyan [Thu, 24 May 2018 07:36:18 +0000 (07:36 +0000)]
[mips] Remove duplicated code from the expandLoadInst. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333164
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Thu, 24 May 2018 07:36:11 +0000 (07:36 +0000)]
[mips] Remove redundant argument from expandLoadInst/expandStoreInst. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333163
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Simon Atanasyan [Thu, 24 May 2018 07:36:06 +0000 (07:36 +0000)]
[mips] Add precondition asserts to the expandLoadInst/expandStoreInst. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333162
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Thu, 24 May 2018 07:36:00 +0000 (07:36 +0000)]
[mips] Cleanup the code a bit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333161
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Fangrui Song [Thu, 24 May 2018 06:57:57 +0000 (06:57 +0000)]
[demangler] Add ItaniumPartialDemangler::isCtorOrDtor
Reviewers: erik.pilkington, ruiu, echristo, pcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333159
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Shiva Chen [Thu, 24 May 2018 06:21:23 +0000 (06:21 +0000)]
[RISCV] Support linker relax function call from auipc and jalr to jal
To do this:
1. Add fixup_riscv_relax fixup types which eventually will
transfer to R_RISCV_RELAX relocation types.
2. Insert R_RISCV_RELAX relocation types to auipc function call
expression when linker relaxation enabled.
Differential Revision: https://reviews.llvm.org/D44886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333158
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Karl-Johan Karlsson [Thu, 24 May 2018 06:09:02 +0000 (06:09 +0000)]
[NaryReassociate] Detect deleted instr with WeakVH
Summary:
If NaryReassociate succeed it will, when replacing the old instruction
with the new instruction, also recursively delete trivially
dead instructions from the old instruction. However, if the input to the
NaryReassociate pass contain dead code it is not save to recursively
delete trivially deadinstructions as it might lead to deleting the newly
created instruction.
This patch will fix the problem by using WeakVH to detect this
rare case, when the newly created instruction is dead, and it will then
restart the basic block iteration from the beginning.
This fixes pr37539
Reviewers: tra, meheff, grosser, sanjoy
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333155
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Tom Stellard [Thu, 24 May 2018 05:28:34 +0000 (05:28 +0000)]
AMDGPU/R600: Remove code for handling AMDGPUISD::CLAMP
Summary:
We don't generate AMDGPUISD::CLAMP for R600 now that llvm.AMDGPU.clamp
is gone.
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47181
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333153
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Andres Freund [Thu, 24 May 2018 05:10:19 +0000 (05:10 +0000)]
Revert r333147 "[ORC] Add findSymbolIn() wrapper to C bindings."
This reverts r333147 until https://reviews.llvm.org/D47308 is ready to
be reviewed. r333147 exposed a behavioural difference between
OrcCBindingsStack::findSymbolIn() and OrcCBindingsStack::findSymbol(),
where only the latter does name mangling. After r333147 that causes a
test failure on OSX, because the new test looks for main using
findSymbolIn() but the mangled name is _main.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333152
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Lei Huang [Thu, 24 May 2018 03:20:28 +0000 (03:20 +0000)]
[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
The match pattern in the definition of LXSDX is xoaddr, so the Pseudo
instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post
RA based on the register pressure. To avoid ambiguity, we need to remove the
select pattern for LXSDX, same as what was done for LXSD. STXSDX also have
the same issue.
Patch by Qing Shan Zhang (steven.zhang).
Differential Revision: https://reviews.llvm.org/D47178
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333150
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Andres Freund [Thu, 24 May 2018 01:01:42 +0000 (01:01 +0000)]
[ORC] Add findSymbolIn() wrapper to C bindings.
In many cases JIT users will know in which module a symbol
resides. Avoiding to search other modules can be more efficient. It
also allows to handle duplicate symbol names between modules.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D44889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333147
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Roman Tereshin [Thu, 24 May 2018 00:24:15 +0000 (00:24 +0000)]
[GlobalISel][InstructionSelect] Switching over root LLTs, perf patch 10
This patch continues a series of patches started by r332907 (reapplied
as r332917).
In this commit we introduce new matching opcode for the MatchTable:
GIM_SwitchType, similar to GIM_SwitchOpcode, and use it to switch over
LLTs of def operands of root instructions on the 2nd level of the
MatchTable within GIM_SwitchOpcode's cases.
This is expected to decrease time GlobalISel spends in its
InstructionSelect pass by about 6.5% for an -O0 build as measured on
sqlite3-amalgamation (http://sqlite.org/download.html) targeting
AArch64 (cross-compile on x86).
Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar
Reviewed By: qcolombet
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333146
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Roman Tereshin [Wed, 23 May 2018 23:58:10 +0000 (23:58 +0000)]
[GlobalISel][InstructionSelect] Moving Reg Bank Checks forward, perf patch 9
This patch continues a series of patches started by r332907 (reapplied
as r332917).
In this commit we move register bank checks back from epilogue of
every rule matcher to a position locally close to the rest of the
checks for a particular (nested) instruction.
This increases the number of common conditions within 2nd level
groups.
This is expected to decrease time GlobalISel spends in its
InstructionSelect pass by about 2% for an -O0 build as measured on
sqlite3-amalgamation (http://sqlite.org/download.html) targeting
AArch64 (cross-compile on x86).
Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar
Reviewed By: qcolombet
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333144
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Roman Tereshin [Wed, 23 May 2018 22:50:53 +0000 (22:50 +0000)]
[GlobalISel][InstructionSelect] Maximizing # of Group's common conditions, perf patch 8
This patch continues a series of patches started by r332907 (reapplied
as r332917).
In this commit we greedily stuff 2nd level GroupMatcher's common
conditions with as many predicates as possible. This is purely
post-processing and it doesn't change which rules are put into the
groups in the first place: that decision is made by looking at the
first common predicate only.
The compile time improvements are minor and well within error margin,
however, it's highly improbable that this transformation could
pessimize performance, thus I'm still committing it for potential
gains for targets not implementing GlobalISel yet and out of tree
targets.
Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar
Reviewed By: qcolombet
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333139
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Vedant Kumar [Wed, 23 May 2018 22:50:45 +0000 (22:50 +0000)]
Move a debug info test into the X86 directory
This test triggers a code path which does not appear to fire on some
targets:
http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/3028
I've made the test X86-specific in an attempt to address the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333138
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Mandeep Singh Grang [Wed, 23 May 2018 22:44:08 +0000 (22:44 +0000)]
[RISCV] Lower the tail pseudoinstruction
This patch lowers the tail pseudoinstruction. This has been modeled after ARM's
tail call opt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333137
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Roman Tereshin [Wed, 23 May 2018 22:10:21 +0000 (22:10 +0000)]
[GlobalISel][Tablegen] Assign small opcodes to pseudos
Sort pseudo instructions first while emitting enum's for target
instructions info. That puts them close to each other and to generic
G_* opcodes for GlobalISel. This makes it easier to build small jump
tables over opcodes that could be directly embedded into MatchTable's
Tablegen'erated for GlobalISel's InstructionSelect.
Reviewed By: bogner
Differential Revision: https://reviews.llvm.org/D47240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333135
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Vedant Kumar [Wed, 23 May 2018 22:03:48 +0000 (22:03 +0000)]
[DebugInfo] Maintain DI for sunken bitcasts
When a bitcast is being sunk in -codegenprepare pass, its DI wasn't
copied over to the newly created instruction. This patch fixes that
bug.
Patch by Kareem Ergawy!
Differential Revision: https://reviews.llvm.org/D47282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333133
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Sameer AbuAsal [Wed, 23 May 2018 21:34:30 +0000 (21:34 +0000)]
[RISCV] Set CostPerUse for registers
Summary:
Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
Differential Revision: https://reviews.llvm.org/D47039
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333132
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Roman Tereshin [Wed, 23 May 2018 21:30:16 +0000 (21:30 +0000)]
[GlobalISel][InstructionSelect] Sorting MatchTable's 2nd level by root LLT, perf patch 7
This patch continues a series of patches started by r332907 (reapplied
as r332917).
In this commit we sort rules within their 2nd level by the type check
on def operand of the root instruction, which allows for better
nesting grouping on the level.
This is expected to decrease time GlobalISel spends in its
InstructionSelect pass by roughly 22% for an -O0 build as measured on
sqlite3-amalgamation (http://sqlite.org/download.html) targeting
AArch64 (cross-compile on x86).
Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar
Reviewed By: qcolombet
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333131
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Lang Hames [Wed, 23 May 2018 21:27:07 +0000 (21:27 +0000)]
[RuntimeDyld][MachO] Add support for MachO::ARM64_RELOC_POINTER_TO_GOT reloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333130
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Lang Hames [Wed, 23 May 2018 21:27:07 +0000 (21:27 +0000)]
[LKH] Add a new IRTransformLayer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333129
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Lang Hames [Wed, 23 May 2018 21:27:06 +0000 (21:27 +0000)]
[LKH] Add ObjectTransformLayer2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333128
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Lang Hames [Wed, 23 May 2018 21:27:01 +0000 (21:27 +0000)]
[LKH] Add a new IRCompileLayer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333127
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Roman Tereshin [Wed, 23 May 2018 21:12:02 +0000 (21:12 +0000)]
[GlobalISel] NFCI, Getting GlobalISel ~5% faster
by replacing DenseMap with IndexedMap for LLTs within MRI, as
benchmarked by cross-compiling sqlite3 amalgamation for AArch64
on x86 machine.
Reviewed By: qcolombet
Differential Revision: https://reviews.llvm.org/D46809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333125
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Roman Tereshin [Wed, 23 May 2018 20:45:43 +0000 (20:45 +0000)]
[Tablegen] Tidying up InstRegexOp a little, NFC
Differential Review: https://reviews.llvm.org/D47240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333121
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Alexander Shaposhnikov [Wed, 23 May 2018 20:39:52 +0000 (20:39 +0000)]
[llvm-strip] Minor fix of the usage of TableGen
This is a small follow-up to the revisions r333117 and r331663.
1. Avoid the name conflicts of the generated variables for prefixes.
2. Apply clang-format -i -style=llvm to llvm-objcopy.cpp once again.
3. Add a test for the flag with double dash.
Test plan: make check-all
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333120
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Alexander Shaposhnikov [Wed, 23 May 2018 19:44:19 +0000 (19:44 +0000)]
[llvm-strip] Expose --keep-symbol option
Expose --keep-symbol option in llvm-strip.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333117
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Lei Huang [Wed, 23 May 2018 19:31:54 +0000 (19:31 +0000)]
[Power9]Legalize and emit code for W vector extract and convert to QP
Implemente patterns to extract [Un]signed Word vector element and convert to
quad-precision.
Differential Revision: https://reviews.llvm.org/D46536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333115
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Roman Tereshin [Wed, 23 May 2018 19:16:59 +0000 (19:16 +0000)]
[GlobalISel][InstructionSelect] Moving type checks forward, perf patch 6
This patch continues a series of patches started by r332907 (reapplied
as r332917)
In this commit we sort type checks towards the beginning of every rule
within the MatchTable as they fail often and it's best to fail early.
This is expected to decrease time GlobalISel spends in its
InstructionSelect pass by roughly 7% for an -O0 build as measured on
sqlite3-amalgamation (http://sqlite.org/download.html) targeting
AArch64. The amalgamation is a large single-file C-source that makes
compiler backend performance improvements to stand out from frontend.
It's also a part of CTMark.
Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar
Reviewed By: qcolombet
Subscribers: rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44700
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333114
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