OSDN Git Service
Andrea Di Biagio [Fri, 6 Jul 2018 13:46:10 +0000 (13:46 +0000)]
[llvm-mca] A write latency cannot be a negative value. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336437
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Sjoerd Meijer [Fri, 6 Jul 2018 13:00:16 +0000 (13:00 +0000)]
[AArch64] Armv8.4-A: TLB support
This adds:
- outer shareable TLB Maintenance instructions, and
- TLB range maintenance instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336434
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Jonas Devlieghere [Fri, 6 Jul 2018 12:49:54 +0000 (12:49 +0000)]
[dsymutil] Emit label at the begin of a CU
When emitting a CU, store the MCSymbol pointing to the beginning of the
CU. We'll need this information later when emitting the .debug_names
section (DWARF5 accelerator table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336433
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Sjoerd Meijer [Fri, 6 Jul 2018 12:32:33 +0000 (12:32 +0000)]
Recommit: [AArch64] Armv8.4-A: Flag manipulation instructions
Now with the asm operand definition included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336432
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Diogo N. Sampaio [Fri, 6 Jul 2018 10:09:04 +0000 (10:09 +0000)]
Added missing semicolon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336428
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Diogo N. Sampaio [Fri, 6 Jul 2018 09:42:25 +0000 (09:42 +0000)]
[SelectionDAG] https://reviews.llvm.org/D48278
D48278
Allow to reduce redundant shift masks.
For example:
x1 = x & 0xAB00
x2 = (x >> 8) & 0xAB
can be reduced to:
x1 = x & 0xAB00
x2 = x1 >> 8
It only allows folding when the masks and shift values are constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336426
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Sjoerd Meijer [Fri, 6 Jul 2018 08:39:43 +0000 (08:39 +0000)]
Revert [AArch64] Armv8.4-A: Flag manipulation instructions
It's causing build errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336422
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Sjoerd Meijer [Fri, 6 Jul 2018 08:12:20 +0000 (08:12 +0000)]
[AArch64] Armv8.4-A: Flag manipulation instructions
These instructions are added to AArch64 only.
Differential Revision: https://reviews.llvm.org/D48926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336421
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Andrea Di Biagio [Fri, 6 Jul 2018 08:08:30 +0000 (08:08 +0000)]
[llvm-mca] improve the instruction issue logic implemented by the Scheduler.
This patch modifies the Scheduler heuristic used to select the next instruction
to issue to the pipelines.
The motivating example is test X86/BtVer2/add-sequence.s, for which llvm-mca
wrongly reported an estimated IPC of 1.50. According to perf, the actual IPC for
that test should have been ~2.00.
It turns out that an IPC of 2.00 for test add-sequence.s cannot possibly be
predicted by a Scheduler that only prioritizes instructions based on their
"age". A similar issue also affected test X86/BtVer2/dependent-pmuld-paddd.s,
for which llvm-mca wrongly estimated an IPC of 0.84 instead of an IPC of 1.00.
Instructions in the ReadyQueue are now ranked based on two factors:
- The "age" of an instruction.
- The number of unique users of writes associated with an instruction.
The new logic still prioritizes older instructions over younger instructions to
minimize the pressure on the reorder buffer. However, the number of users of an
instruction now also affects the overall rank. This potentially increases the
ability of the Scheduler to extract instruction level parallelism. This patch
fixes the problem with the wrong IPC reported for test add-sequence.s and test
dependent-pmuld-paddd.s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336420
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Tim Northover [Fri, 6 Jul 2018 08:04:47 +0000 (08:04 +0000)]
CallGraphSCCPass: iterate over all functions.
Previously we only iterated over functions reachable from the set of
external functions in the module. But since some of the passes under
this (notably the always-inliner and coroutine lowerer) are required for
correctness, they need to run over everything.
This just adds an extra layer of iteration over the CallGraph to keep
track of which functions we've already visited and get the next batch of
SCCs.
Should fix PR38029.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336419
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Sjoerd Meijer [Fri, 6 Jul 2018 08:03:12 +0000 (08:03 +0000)]
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction.
Differential Revision: https://reviews.llvm.org/D48918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336418
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Craig Topper [Fri, 6 Jul 2018 07:14:41 +0000 (07:14 +0000)]
[X86] Remove FMA4 scalar intrinsics. Use llvm.fma intrinsic instead.
The intrinsics can be implemented with a f32/f64 llvm.fma intrinsic and an insert into a zero vector.
There are a couple regressions here due to SelectionDAG not being able to pull an fneg through an extract_vector_elt. I'm not super worried about this though as InstCombine should be able to do it before we get to SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336416
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Sam McCall [Fri, 6 Jul 2018 05:45:45 +0000 (05:45 +0000)]
[Support] Make support types more easily printable.
Summary:
Error's new operator<< is the first way to print an error without consuming it.
formatv() can now print objects with an operator<< that works with raw_ostream.
Reviewers: bkramer
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D48966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336412
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Dave Lee [Fri, 6 Jul 2018 05:11:35 +0000 (05:11 +0000)]
Reapply: "objdump: Support newer ObjC image info flags"
Summary:
Add support for two additional ObjC image info flags: `IS_SIMULATED` and
`HAS_CATEGORY_CLASS_PROPERTIES`.
`IS_SIMULATED` indicates a Mach-O binary built for iOS simulator.
`HAS_CATEGORY_CLASS_PROPERTIES` indicates a Mach-O binary built by a compiler
that supports class properties in categories.
Reviewers: enderby, compnerd
Reviewed By: compnerd
Subscribers: keith, llvm-commits
Differential Revision: https://reviews.llvm.org/D48568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336411
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Max Kazantsev [Fri, 6 Jul 2018 04:04:13 +0000 (04:04 +0000)]
Revert "[InstCombine] Delay foldICmpUsingKnownBits until simple transforms are done"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336410
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Craig Topper [Fri, 6 Jul 2018 03:42:09 +0000 (03:42 +0000)]
[X86] Remove all of the avx512 masked packed fma intrinsics. Use llvm.fma or unmasked 512-bit intrinsics with rounding mode.
This upgrades all of the intrinsics to use fneg instructions to convert fma into fmsub/fnmsub/fnmadd/fmsubadd. And uses a select instruction for masking.
This matches how clang uses the intrinsics these days.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336409
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Craig Topper [Fri, 6 Jul 2018 03:42:06 +0000 (03:42 +0000)]
[X86] Cleanup some of the avx512 masked fma tests to prepare for removing and autoupgrading.
-Split cases that call 2 intrinsics in the same case.
-Remove testing mask3 and maskz intrinsics with an all ones mask. These won't be interesting after the upgrade.
-Restore test cases for some intrinsics that are marked for deletion, but haven't been deleted yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336408
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Zachary Turner [Fri, 6 Jul 2018 02:59:25 +0000 (02:59 +0000)]
[llvm-pdbutil] Dump more info about globals.
We add an option to dump the entire global / public symbol record
stream. Previously we would dump globals or publics, but not both.
And when we did dump them, we would always dump them in the order
they were referenced by the corresponding hash streams, not in
the order they were serialized in. This patch adds a lower level
mode that just dumps the whole stream in serialization order.
Additionally, when dumping global-extras, we now dump the hash
bitmap as well as the record offset instead of dumping all zeros
for the offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336407
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Stefan Pintilie [Fri, 6 Jul 2018 02:47:02 +0000 (02:47 +0000)]
[Power9] Add __float128 library call for frem
Power 9 does not have a hardware instruction for frem but we can call fmodf128.
Differential Revision: https://reviews.llvm.org/D48552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336406
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Zachary Turner [Fri, 6 Jul 2018 02:33:58 +0000 (02:33 +0000)]
[PDB] Sort globals symbols by name in GSI hash buckets.
It seems like the debugger first computes a symbol's bucket,
and then does a binary search of entries in the bucket using the
symbol's name in order to find it. If the bucket entries are not
in sorted order, this obviously won't work. After this patch a
couple of simple test cases show that we generate an exactly
identical GSI hash stream, which is very nice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336405
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Easwaran Raman [Fri, 6 Jul 2018 00:31:33 +0000 (00:31 +0000)]
[x86]Add a test case to show missed vfnmadd generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336404
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Dave Lee [Fri, 6 Jul 2018 00:13:21 +0000 (00:13 +0000)]
Revert "objdump: Support newer ObjC image info flags"
This reverts commit
8c4cc472e7a67bd3b2b20cc4cf32d31af29bc7e9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336402
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Mandeep Singh Grang [Thu, 5 Jul 2018 23:41:17 +0000 (23:41 +0000)]
[OpenEmbedded] Add OpenEmbedded vendor
Summary: The lib paths are not correctly picked up for OpenEmbedded sysroots
(like arm-oe-linux-gnueabi). I fix this in a follow-up clang patch. But in
order to add the correct libs I need to detect if the vendor is oe. For this
reason, it is first necessary to teach llvm to detect oe vendor, which is what
this patch does.
Reviewers: chandlerc, compnerd, rengolin, javed.absar
Reviewed By: compnerd
Subscribers: kristof.beyls, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D48861
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336401
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Maksim Panchenko [Thu, 5 Jul 2018 23:32:42 +0000 (23:32 +0000)]
[X86][Disassembler] Fix LOCK prefix disassembler support
Summary:
If LOCK prefix is not the first prefix in an instruction, LLVM
disassembler silently drops the prefix.
The fix is to select a proper instruction with a builtin LOCK prefix if
one exists.
Reviewers: craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49001
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336400
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Dave Lee [Thu, 5 Jul 2018 23:32:15 +0000 (23:32 +0000)]
objdump: Support newer ObjC image info flags
Summary:
Add support for two additional ObjC image info flags: `IS_SIMULATED` and
`HAS_CATEGORY_CLASS_PROPERTIES`.
`IS_SIMULATED` indicates a Mach-O binary built for iOS simulator.
`HAS_CATEGORY_CLASS_PROPERTIES` indicates a Mach-O binary built by a compiler
that supports class properties in categories.
Reviewers: enderby, compnerd
Reviewed By: compnerd
Subscribers: keith, llvm-commits
Differential Revision: https://reviews.llvm.org/D48568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336399
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Michael Zolotukhin [Thu, 5 Jul 2018 22:10:31 +0000 (22:10 +0000)]
Revert r332168: "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading.""
There were a couple of issues reported (PR38047, PR37929) - I'll reland
the patch when I figure out and fix the rootcause.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336393
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Heejin Ahn [Thu, 5 Jul 2018 21:27:09 +0000 (21:27 +0000)]
[WebAssembly] Add missing _S opcodes of atomic stores to InstPrinter
Summary: This was missing in D48839 (rL336145).
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D48992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336390
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Heejin Ahn [Thu, 5 Jul 2018 21:23:15 +0000 (21:23 +0000)]
[ORC] Add BitReader/BitWriter to target_link_libraries
Summary:
CompileOnDemandLayer.cpp uses function in these libraries, and builds
with `-DSHARED_LIB=ON` fail without this.
Reviewers: lhames
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D48995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336389
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Sander de Smalen [Thu, 5 Jul 2018 20:21:21 +0000 (20:21 +0000)]
This is a recommit of r336322, previously reverted in r336324 due to
a deficiency in TableGen that has been addressed in r336334.
[AArch64][SVE] Asm: Support for predicated FP rounding instructions.
This patch also adds instructions for predicated FP square-root and
reciprocal exponent.
The added instructions are:
- FRINTI Round to integral value (current FPCR rounding mode)
- FRINTX Round to integral value (current FPCR rounding mode, signalling inexact)
- FRINTA Round to integral value (to nearest, with ties away from zero)
- FRINTN Round to integral value (to nearest, with ties to even)
- FRINTZ Round to integral value (toward zero)
- FRINTM Round to integral value (toward minus Infinity)
- FRINTP Round to integral value (toward plus Infinity)
- FSQRT Floating-point square root
- FRECPX Floating-point reciprocal exponent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336387
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Lang Hames [Thu, 5 Jul 2018 19:01:27 +0000 (19:01 +0000)]
[ORC] In CompileOnDemandLayer2, clone modules on to different contexts by
writing them to a buffer and re-loading them.
Also introduces a multithreaded variant of SimpleCompiler
(MultiThreadedSimpleCompiler) for compiling IR concurrently on multiple
threads.
These changes are required to JIT IR on multiple threads correctly.
No test case yet. I will be looking at how to modify LLI / LLJIT to test
multithreaded JIT support soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336385
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Diogo N. Sampaio [Thu, 5 Jul 2018 18:49:32 +0000 (18:49 +0000)]
Testing commit permision
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336384
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Craig Topper [Thu, 5 Jul 2018 18:43:58 +0000 (18:43 +0000)]
[X86] Remove the last of the 'x86.fma.' intrinsics and autoupgrade them to 'llvm.fma'. Add upgrade tests for all.
Still need to remove the AVX512 masked versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336383
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Craig Topper [Thu, 5 Jul 2018 17:10:17 +0000 (17:10 +0000)]
[X86] Add SHUF128 to target shuffle decoding.
Differential Revision: https://reviews.llvm.org/D48954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336376
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Matt Arsenault [Thu, 5 Jul 2018 17:05:36 +0000 (17:05 +0000)]
Fix asserts in AMDGCN fmed3 folding by handling more cases of NaN
Better NaN handling for AMDGCN fmed3.
All operands are checked for NaN now. The checks
were moved before the canonicalization to provide
a better mapping from fclamp. Changed the behaviour
of fmed3(x,y,NaN) to return max(x,y) instead of
min(x,y) in light of this. Updated tests as a result
and added some new cases to cover the fix.
Patch by Alan Baker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336375
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Matt Arsenault [Thu, 5 Jul 2018 17:01:29 +0000 (17:01 +0000)]
AMDGPU: Don't use spir_kernel in a test
Also use verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336374
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Matt Arsenault [Thu, 5 Jul 2018 17:01:20 +0000 (17:01 +0000)]
AMDGPU/GlobalISel: Implement custom kernel arg lowering
Avoid using allocateKernArg / AssignFn. We do not want any
of the type splitting properties of normal calling convention
lowering.
For now at least this exists alongside the IR argument lowering
pass. This is necessary to handle struct padding correctly while
some arguments are still skipped by the IR argument lowering
pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336373
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Simon Pilgrim [Thu, 5 Jul 2018 16:56:28 +0000 (16:56 +0000)]
[CostModel][X86] Add UDIV/UREM by pow2 costs
Normally InstCombine would have simplified these to SRL/AND instructions but we may still see these during SLP vectorization etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336371
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Paul Semel [Thu, 5 Jul 2018 16:49:46 +0000 (16:49 +0000)]
[llvm-objdump] Removed archive-headers-disas test
This test is failing because of the disas part.
For the moment, I will juste remove it. I will add it again tomorrow
with a proper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336370
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Andrea Di Biagio [Thu, 5 Jul 2018 16:13:49 +0000 (16:13 +0000)]
[llvm-mca] Fix RegisterFile debug prints. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336367
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Paul Semel [Thu, 5 Jul 2018 15:24:11 +0000 (15:24 +0000)]
[llvm-objcopy] Fix timezone dependant tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336363
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Lei Huang [Thu, 5 Jul 2018 15:21:37 +0000 (15:21 +0000)]
[Power9] Add lib calls for float128 operations with no equivalent PPC instructions
Map the following instructions to the proper float128 lib calls:
pow[i], exp[2], log[2|10], sin, cos, fmin, fmax
Differential Revision: https://reviews.llvm.org/D48544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336361
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Simon Pilgrim [Thu, 5 Jul 2018 15:15:47 +0000 (15:15 +0000)]
[X86][SSE] Add srem x, (1 << c) combine tests
Now that D45806 has landed we can start trying to avoid scalarizing srem by constant - these tests demonstrate some example cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336360
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Paul Semel [Thu, 5 Jul 2018 14:43:29 +0000 (14:43 +0000)]
[llvm-objdump] Add --archive-headers (-a) option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336357
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Clement Courbet [Thu, 5 Jul 2018 13:54:51 +0000 (13:54 +0000)]
[llvm-exegesis] Add uop computation for more X87 instruction classes.
Summary:
This allows measuring comparisons (UCOM_FpIr32,UCOM_Fpr32,...),
conditional moves (CMOVBE_Fp32,...)
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D48713
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336352
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Simon Pilgrim [Thu, 5 Jul 2018 13:51:35 +0000 (13:51 +0000)]
Fix comment typo. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336351
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Sanjay Patel [Thu, 5 Jul 2018 13:16:46 +0000 (13:16 +0000)]
[AArch64, PowerPC, x86] add tests for signbit bit hacks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336348
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Simon Pilgrim [Thu, 5 Jul 2018 12:30:44 +0000 (12:30 +0000)]
[SLPVectorizer] Begin abstracting InstructionsState alternate matching away from opcodes. NFCI.
This is an early step towards matching Instructions by attributes other than the opcode. This will be necessary for cast/call alternates which share the same opcode but have different types/intrinsicIDs etc. - which we could vectorize as long as we split them using the alternate mechanism.
Differential Revision: https://reviews.llvm.org/D48945
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336344
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Clement Courbet [Thu, 5 Jul 2018 12:26:12 +0000 (12:26 +0000)]
[llvm-exegesis][NFC]clang-format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336343
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Ryan Taylor [Thu, 5 Jul 2018 12:02:07 +0000 (12:02 +0000)]
[AMDGPU] Add VALU to V_INTERP Instructions
Wait states are not properly being inserted after buffer_store for v_interp instructions.
Add VALU to V_INTERP instructions so that the GCNHazardRecognizer can
check and insert the appropriate wait states when needed.
Differential Revision: https://reviews.llvm.org/D48772
Change-Id: Id540c9b074fc69b5c1de6b182276aa089c74aa64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336339
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Chandler Carruth [Thu, 5 Jul 2018 11:56:34 +0000 (11:56 +0000)]
[ADT] Switch to indirect even the trivial case through an object pointer
that has required alignment. This avoids issues that keep coming up with
function pointers being less aligned.
I'm pretty annoyed that we can't take advantage of function alignment
even on platforms where they *are* aligned, but build modes and other
things make taking advantage of it somewhere between hard and
impossible. The best case scenario would still embed various build modes
into the ABI causing really hard to debug issues if you compiled one
object file differently from another. =/
This should at least bring the bots back that were having trouble with
this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336337
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Krasimir Georgiev [Thu, 5 Jul 2018 11:30:15 +0000 (11:30 +0000)]
Partially revert r336268 in address-offsets.ll
Summary: There the typos are intentional, explicitly introduced to disable these cases in r280285.
Reviewers: bkramer
Reviewed By: bkramer
Subscribers: dschuff, sbc100, jgravelle-google, aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D48962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336336
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Sander de Smalen [Thu, 5 Jul 2018 10:39:15 +0000 (10:39 +0000)]
[TableGen] Increase the number of supported decoder fix-ups.
The vast number of added instructions for SVE causes TableGen to fail with an assertion:
Assertion `Delta < 65536U && "disassembler decoding table too large!"'
This patch increases the number of supported decoder fix-ups.
Reviewers: dmgreen, stoklund, petpav01
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D48937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336334
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 5 Jul 2018 09:54:53 +0000 (09:54 +0000)]
[X86][SSE] Add extra v16i16 shl x,c -> pmullw test
We want to compare shifts with repeated vs non-repeated v8i16 shuffle masks (for PBLENDW ymm)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336333
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 5 Jul 2018 09:48:01 +0000 (09:48 +0000)]
Try to fix -Wimplicit-fallthrough warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336331
91177308-0d34-0410-b5e6-
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Aleksandar Beserminji [Thu, 5 Jul 2018 09:27:05 +0000 (09:27 +0000)]
[mips] Fix atomic operations at O0, v3
Similar to PR/25526, fast-regalloc introduces spills at the end of basic
blocks. When this occurs in between an ll and sc, the stores can cause the
atomic sequence to fail.
This patch fixes the issue by introducing more pseudos to represent atomic
operations and moving their lowering to after the expansion of postRA
pseudos.
This version addresses issues with the initial implementation and covers
all atomic operations.
This resolves PR/32020.
Thanks to James Cowgill for reporting the issue!
Patch By: Simon Dardis
Differential Revision: https://reviews.llvm.org/D31287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336328
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Ivan A. Kosarev [Thu, 5 Jul 2018 08:59:49 +0000 (08:59 +0000)]
[NEON] Fix combining of vldx_dup intrinsics with updating of base addresses
Resolves:
Unsupported ARM Neon intrinsics in Target-specific DAG combine
function for VLDDUP
https://bugs.llvm.org/show_bug.cgi?id=38031
Related diff: D48439
Differential Revision: https://reviews.llvm.org/D48920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336325
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Sander de Smalen [Thu, 5 Jul 2018 08:52:03 +0000 (08:52 +0000)]
Reverting r336322 for now, as it causes an assert failure
in TableGen, for which there is already a patch in Phabricator
(D48937) that needs to be committed first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336324
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Mikael Holmen [Thu, 5 Jul 2018 08:42:16 +0000 (08:42 +0000)]
Partial revert of "NFC - Various typo fixes in tests"
This partially reverts r336268 since it causes buildbot failures.
Added FIXME at the places where the CHECKs are misspelled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336323
91177308-0d34-0410-b5e6-
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Sander de Smalen [Thu, 5 Jul 2018 08:38:30 +0000 (08:38 +0000)]
[AArch64][SVE] Asm: Support for predicated FP rounding instructions.
This patch also adds instructions for predicated FP square-root and
reciprocal exponent.
The added instructions are:
- FRINTI Round to integral value (current FPCR rounding mode)
- FRINTX Round to integral value (current FPCR rounding mode, signalling inexact)
- FRINTA Round to integral value (to nearest, with ties away from zero)
- FRINTN Round to integral value (to nearest, with ties to even)
- FRINTZ Round to integral value (toward zero)
- FRINTM Round to integral value (toward minus Infinity)
- FRINTP Round to integral value (toward plus Infinity)
- FSQRT Floating-point square root
- FRECPX Floating-point reciprocal exponent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336322
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Sjoerd Meijer [Thu, 5 Jul 2018 08:21:40 +0000 (08:21 +0000)]
[ARM] ParallelDSP: only support i16 loads for now
We were miscompiling i8 loads, so reject them as unsupported narrow operations
for now.
Differential Revision: https://reviews.llvm.org/D48944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336319
91177308-0d34-0410-b5e6-
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Sander de Smalen [Thu, 5 Jul 2018 07:54:10 +0000 (07:54 +0000)]
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD
This patch implements the following varieties:
- Unpredicated signed max, e.g. smax z0.h, z1.h, #-128
- Unpredicated signed min, e.g. smin z0.h, z1.h, #-128
- Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255
- Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255
- Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h
- Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h
- Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h
- Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h
- Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h
- Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336317
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Lei Huang [Thu, 5 Jul 2018 07:46:01 +0000 (07:46 +0000)]
[Power9] Optimize codgen for conversions of int to float128
Optimize code sequences for integer conversion to fp128 when the integer is a result of:
* float->int
* float->long
* double->int
* double->long
Differential Revision: https://reviews.llvm.org/D48429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336316
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 5 Jul 2018 06:52:55 +0000 (06:52 +0000)]
[X86] Remove X86 specific scalar FMA intrinsics and upgrade to tart independent FMA and extractelement/insertelement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336315
91177308-0d34-0410-b5e6-
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Lei Huang [Thu, 5 Jul 2018 06:51:38 +0000 (06:51 +0000)]
[Power9][NFC] add back-end tests for passing homogeneous fp128 aggregates by value
Tests to verify that we are passing fp128 via VSX registers as per ABI.
These are related to clang commit rL336308.
Differential Revision: https://reviews.llvm.org/D48310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336314
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Lei Huang [Thu, 5 Jul 2018 06:29:28 +0000 (06:29 +0000)]
[Power9] Add tests for passing float128 in VSX reg for non-homogenous aggregates
Add missing testcase for rL336310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336313
91177308-0d34-0410-b5e6-
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Serge Pavlov [Thu, 5 Jul 2018 06:22:39 +0000 (06:22 +0000)]
[demangler] Avoid alignment warning
The alignment specified by a constant for the field
`BumpPointerAllocator::InitialBuffer` exceeded the alignment
guaranteed by `malloc` and `new` on Windows. This change set
the alignment value to that of `long double`, which is defined
by the used platform.
It fixes https://bugs.llvm.org/show_bug.cgi?id=37944.
Differential Revision: https://reviews.llvm.org/D48889
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336311
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Lei Huang [Thu, 5 Jul 2018 06:21:37 +0000 (06:21 +0000)]
[Power9] Ensure float128 in non-homogenous aggregates are passed via VSX reg
Non-homogenous aggregates are passed in consecutive GPRs, in GPRs and in memory,
or in memory. This patch ensures that float128 members of non-homogenous
aggregates are passed via VSX registers.
This is done via custom lowering a bitcast of a build_pari(i64,i64) to float128
to a new PPCISD node, BUILD_FP128.
Differential Revision: https://reviews.llvm.org/D48308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336310
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Lei Huang [Thu, 5 Jul 2018 04:18:37 +0000 (04:18 +0000)]
[Power9]Legalize and emit code for quad-precision convert from single-precision
Legalize and emit code for quad-precision floating point operation conversion of
single-precision value to quad-precision.
Differential Revision: https://reviews.llvm.org/D47569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336307
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Lei Huang [Thu, 5 Jul 2018 04:10:15 +0000 (04:10 +0000)]
[Power9] Implement float128 parameter passing and return values
This patch enable parameter passing and return by value for float128 types.
Passing aggregate/union which contain float128 members will be submitted in
subsequent patches.
Differential Revision: https://reviews.llvm.org/D47552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336306
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Craig Topper [Thu, 5 Jul 2018 03:01:29 +0000 (03:01 +0000)]
[X86] Remove some isel patterns for X86ISD::SELECTS that specifically looked for the v1i1 mask to have come from a scalar_to_vector from GR8.
We have patterns for SELECTS that top at v1i1 and we have a pattern for (v1i1 (scalar_to_vector GR8)). The patterns being removed here do the same thing as the two other patterns combined so there is no need for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336305
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 5 Jul 2018 02:52:56 +0000 (02:52 +0000)]
[X86] Add support for combining FMSUB/FNMADD/FNMSUB ISD nodes with an fneg input.
Previously we could only negate the FMADD opcodes. This used to be mostly ok when we lowered FMA intrinsics during lowering. But with the move to llvm.fma from target specific intrinsics, we can combine (fneg (fma)) to (fmsub) earlier. So if we start with (fneg (fma (fneg))) we would get stuck at (fmsub (fneg)).
This patch fixes that so we can also combine things like (fmsub (fneg)).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336304
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Craig Topper [Thu, 5 Jul 2018 02:52:54 +0000 (02:52 +0000)]
[X86] Remove some of the packed FMA3 intrinsics since we no longer use them in clang.
There's a regression in here due to inability to combine fneg inputs of X86ISD::FMSUB/FNMSUB/FNMADD nodes.
More removals to come, but I wanted to stop and fix the regression that showed up in this first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336303
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Lei Huang [Wed, 4 Jul 2018 21:59:16 +0000 (21:59 +0000)]
[Power9]Legalize and emit code for round & convert quad-precision values
Legalize and emit code for round & convert float128 to double precision and
single precision.
Differential Revision: https://reviews.llvm.org/D46997
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336299
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Aaron Ballman [Wed, 4 Jul 2018 21:22:28 +0000 (21:22 +0000)]
Silence an MSVC C4189 warning about a local variable being initialized but not used; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336298
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Vladimir Stefanovic [Wed, 4 Jul 2018 19:26:31 +0000 (19:26 +0000)]
[mips] Warn when crc, ginv, virt flags are used with too old revision
CRC and GINV ASE require revision 6, Virtualization requires revision 5.
Print a warning when revision is older than required.
Differential Revision: https://reviews.llvm.org/D48843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336296
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Stefan Pintilie [Wed, 4 Jul 2018 18:54:25 +0000 (18:54 +0000)]
[PowerPC] Replace the Post RA List Scheduler with the Machine Scheduler
We want to run the Machine Scheduler instead of the List Scheduler after RA.
Checked with a performance run on a Power 9 machine with SPEC 2006 and while
some benchmarks improved and others degraded the geomean was slightly improved
with the Machine Scheduler.
Differential Revision: https://reviews.llvm.org/D45265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336295
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Jakub Kuderski [Wed, 4 Jul 2018 18:37:15 +0000 (18:37 +0000)]
[Dominators] Add DomTreeUpdater constructor from DT* and PDT*
Summary:
Previously, if a function accepts an optional DT pointer,
```
void Foo (.., DominatorTree * DT = nullptr) {
...
if(DT)
DomTreeUpdater(*DT, ...).insertEdge(A, B);
if(DT){
DomTreeUpdater DTU(*DT, ...);
... // Construct the update vector and applyUpdates
}
...
if(DT){
DomTreeUpdater DTU(*DT, ...);
... // Construct the update vector and applyUpdates
}
}
```
After this patch, it can be simplified as
```
void Foo (.., DominatorTree * DT = nullptr) {
DomTreeUpdater DTU(DT, ...);
...
DTU.insertEdge(A, B);
if(DT){
... // Construct the update vector and applyUpdates
}
...
if(DT){
... // Construct the update vector and applyUpdates
}
}
```
Patch by Chijun Sima <simachijun@gmail.com>.
Reviewers: kuhar, brzycki, dmgreen
Reviewed By: kuhar
Author: NutshellySima
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336294
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Sanjay Patel [Wed, 4 Jul 2018 17:44:04 +0000 (17:44 +0000)]
[InstCombine] allow narrowing of min/max/abs
We have bailout hacks based on min/max in various places in instcombine
that shouldn't be necessary. The affected test was added for:
D48930
...which is a consequence of the improvement in:
D48584 (https://reviews.llvm.org/rL336172)
I'm assuming the visitTrunc bailout in this patch was added specifically
to avoid a change from SimplifyDemandedBits, so I'm just moving that
below the EvaluateInDifferentType optimization. A narrow min/max is still
a min/max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336293
91177308-0d34-0410-b5e6-
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Roman Lebedev [Wed, 4 Jul 2018 17:32:44 +0000 (17:32 +0000)]
[X86][BtVer2][MCA][NFC] Add CMPEQ dependency-breaking one-idioms tests
Summary: As per `Agner's Microarchitecture doc
(21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions)`,
these, like zero-idioms, are dependency-breaking,
although they produce ones and still consume resources.
FIXME: as discussed in D48877, llvm-mca handling is broken for these.
Reviewers: andreadb
Reviewed By: andreadb
Subscribers: gbedwell, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D48876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336292
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Simon Pilgrim [Wed, 4 Jul 2018 17:24:05 +0000 (17:24 +0000)]
Fix some irregular whitespace/indentation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336291
91177308-0d34-0410-b5e6-
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Sanjay Patel [Wed, 4 Jul 2018 16:56:35 +0000 (16:56 +0000)]
[InstCombine] add value names to test; NFC
That makes it easier to mix and match lines into other tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336289
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Volodymyr Turanskyy [Wed, 4 Jul 2018 16:11:15 +0000 (16:11 +0000)]
[ARM] [Assembler] Support negative immediates: cover few missing cases
Support for negative immediates was implemented in
https://reviews.llvm.org/rL298380, however few instruction options were missing.
This change adds negative immediates support and respective tests
for the following:
ADD
ADDS
ADDS.W
AND.W
ANDS
BIC.W
BICS
BICS.W
SUB
SUBS
SUBS.W
Differential Revision: https://reviews.llvm.org/D48649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336286
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Yvan Roux [Wed, 4 Jul 2018 15:37:08 +0000 (15:37 +0000)]
[MachineOutliner] Fix typo in getOutliningCandidateInfo function name
getOutlininingCandidateInfo -> getOutliningCandidateInfo
Differential Revision: https://reviews.llvm.org/D48867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336285
91177308-0d34-0410-b5e6-
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Paul Semel [Wed, 4 Jul 2018 15:25:03 +0000 (15:25 +0000)]
[llvm-objdump] Add --file-headers (-f) option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336284
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 4 Jul 2018 14:20:58 +0000 (14:20 +0000)]
[X86][SSE] Add v16i16 shl x,c -> pmullw test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336277
91177308-0d34-0410-b5e6-
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Andrew Ng [Wed, 4 Jul 2018 14:17:10 +0000 (14:17 +0000)]
[ThinLTO] Update ThinLTO cache file atimes when on Windows
ThinLTO cache file access times are used for expiration based pruning
and since Vista, file access times are not updated by Windows by
default:
https://blogs.technet.microsoft.com/filecab/2006/11/07/disabling-last-access-time-in-windows-vista-to-improve-ntfs-performance
This means on Windows, cache files are currently being pruned from
creation time. This change manually updates cache files that are
accessed by ThinLTO, when on Windows.
Patch by Owen Reynolds.
Differential Revision: https://reviews.llvm.org/D47266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336276
91177308-0d34-0410-b5e6-
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Sander de Smalen [Wed, 4 Jul 2018 14:05:33 +0000 (14:05 +0000)]
[AArch64][SVE] Asm: Support for reversed subtract (SUBR) instruction.
This patch adds both a vector and an immediate form, e.g.
- Vector form:
subr z0.h, p0/m, z0.h, z1.h
subtract active elements of z0 from z1, and store the result in z0.
- Immediate form:
subr z0.h, z0.h, #255
subtract elements of z0, and store the result in z0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336274
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 4 Jul 2018 13:58:13 +0000 (13:58 +0000)]
[X86][SSE] Add SSE2 target to some shift tests
Show the difference in behaviour cf SSE41 (no PMULLD, PBLENDW etc.)
Raised by D48936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336271
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Gabor Buella [Wed, 4 Jul 2018 13:28:39 +0000 (13:28 +0000)]
NFC - Various typo fixes in tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336268
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Wed, 4 Jul 2018 12:58:46 +0000 (12:58 +0000)]
[AArch64][SVE] Asm: Support for instructions to set/read FFR.
Includes instructions to read the First-Faulting Register (FFR):
- RDFFR (unpredicated)
rdffr p0.b
- RDFFR (predicated)
rdffr p0.b, p0/z
- RDFFRS (predicated, sets condition flags)
rdffr p0.b, p0/z
Includes instructions to set/write the FFR:
- SETFFR (no arguments, sets the FFR to all true)
setffr
- WRFFR (unpredicated)
wrffr p0.b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336267
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Jul 2018 12:31:00 +0000 (12:31 +0000)]
[llvm-exegesis] Remove dead comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336266
91177308-0d34-0410-b5e6-
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Sander de Smalen [Wed, 4 Jul 2018 12:13:17 +0000 (12:13 +0000)]
[AArch64][SVE] Asm: Support for FP conversion instructions.
The variants added are:
- fcvt (FP convert precision)
- scvtf (signed int -> FP)
- ucvtf (unsigned int -> FP)
- fcvtzs (FP -> signed int (round to zero))
- fcvtzu (FP -> unsigned int (round to zero))
For example:
fcvt z0.h, p0/m, z0.s (single- to half-precision FP)
scvtf z0.h, p0/m, z0.s (32-bit int to half-precision FP)
ucvtf z0.h, p0/m, z0.s (32-bit unsigned int to half-precision FP)
fcvtzs z0.s, p0/m, z0.h (half-precision FP to 32-bit int)
fcvtzu z0.s, p0/m, z0.h (half-precision FP to 32-bit unsigned int)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336265
91177308-0d34-0410-b5e6-
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Max Kazantsev [Wed, 4 Jul 2018 10:32:02 +0000 (10:32 +0000)]
[NFC] Add test that shows that InstCombine can do better
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336258
91177308-0d34-0410-b5e6-
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Anastasis Grammenos [Wed, 4 Jul 2018 10:16:55 +0000 (10:16 +0000)]
[DebugInfo][LoopVectorize] Preserve DL in generated phi instruction
When creating `phi` instructions to resume at the scalar part of the loop,
copy the DebugLoc from the original phi over to the new one.
Differential Revision: https://reviews.llvm.org/D48769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336256
91177308-0d34-0410-b5e6-
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Anastasis Grammenos [Wed, 4 Jul 2018 09:55:46 +0000 (09:55 +0000)]
[DebugInfo][InstCombine] Preserve DI after combining zext
When zext is EvaluatedInDifferentType, InstCombine
drops the dbg.value intrinsic. This patch tries to
preserve said DI, by inserting the zext's old DI in the
resulting instruction. (Only for integer type for now)
Differential Revision: https://reviews.llvm.org/D48331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336254
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Simon Pilgrim [Wed, 4 Jul 2018 09:12:48 +0000 (09:12 +0000)]
[X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values (REAPPLIED)
We were only doing this for basic blends, despite shuffle lowering now being good enough to handle more complex blends. This means that the two v8i16 splat shifts are performed in parallel instead of serially as the general shift case.
Reapplied with a fixed (extra null tests) version of rL336113 after reversion in rL336189 - extra test case added at rL336247.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336250
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Simon Pilgrim [Wed, 4 Jul 2018 08:55:23 +0000 (08:55 +0000)]
[X86][SSE] Add reduced crash test case for r336113 - [X86][SSE] Blend any v8i16/v4i32 shift with 2 shift unique values
The patch was reverted at r336189 due to crashes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336247
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Sander de Smalen [Wed, 4 Jul 2018 08:50:49 +0000 (08:50 +0000)]
[AArch64][SVE] Asm: Support for SVE condition code aliases
SVE overloads the AArch64 PSTATE condition flags and introduces
a set of condition code aliases for the assembler. The
details are described in section 2.2 of the architecture
reference manual supplement for SVE.
In short:
SVE alias => AArch64 name
--------------------------
NONE => EQ
ANY => NE
NLAST => HS
LAST => LO
FIRST => MI
NFRST => PL
PMORE => HI
PLAST => LS
TCONT => GE
TSTOP => LT
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336245
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Max Kazantsev [Wed, 4 Jul 2018 08:01:26 +0000 (08:01 +0000)]
[ImplicitNullChecks] Check for rewrite of register used in 'test' instruction
The following code pattern:
mov %rax, %rcx
test %rax, %rax
%rax = ....
je throw_npe
mov(%rcx), %r9
mov(%rax), %r10
gets transformed into the following incorrect code after implicit null check pass:
mov %rax, %rcx
%rax = ....
faulting_load_op("movl (%rax), %r10", throw_npe)
mov(%rcx), %r9
For implicit null check pass, if the register that is checked for null value (ie, the register used in the 'test' instruction) is written into before the condition jump, we should avoid doing the optimization.
Patch by Surya Kumari Jangala!
Differential Revision: https://reviews.llvm.org/D48627
Reviewed By: skatkov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336241
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Fangrui Song [Tue, 3 Jul 2018 23:31:19 +0000 (23:31 +0000)]
[Support] Remove SaveOr which is no longer used
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336237
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